UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF ALIFORNIA, BERELEY ollege of Egieerig Deartmet of Electrical Egieerig ad omuter Scieces Ja M. Rabaey Homework #5 EES 4 SP0) [PROBLEM Elmore Delay 30ts) Due Friday, March 5, 5m, box i 40 ory Fig. a) R Network a) A R etwork is show i Fig. a). alculate the Elmore delay from I to Out ad from I to Out. Which oe is critical ath? 0 ts) ) From I to Out: τ [ R R R) R R R) [ R 3) i out 0 From I to Out: τ [ R R R) R R R) R R R R) 3 [ R ) i out R R The Elmore delay from I to Outis 0R ad the Elmore delay from I to Outis R. So the critical ath is from I to Out. Note: Elmore Delay is just a time costat for this etwork. If you wat to calculate the roagatio delay: Td Td i out i out 69* τ 69* τ i out i out

2 Fig. b) osider the circuit i Fig.b), we will use a equivalet resistor-caacitor model ad Elmore delay to estimate roagatio delay of the circuit. The size of the trasistors is idicated as S. S meas the miimum size, WW mi ; S meas WxW mi, etc.) Assume the followig arameters for the miimum-size NMOS ad PMOS trasistors, S: R eqnmos 0kΩ, R eqpmos 0kΩ, gs gd 5; db sb. Igore overla caacitaces ad feed-through from the gates of the switchig trasistors to the circuit odes. Assume all odes excet Vi) are iitially at 0V. A voltage waveform V TRL show i Fig.b) is alied to the circuit. b) Draw the equivalet R- circuit after tt icludig all relevat resistors ad caacitors ad idicate their values. 0 ts)

3 ) After tt, the equivalet R- circuit is : omoet values: RR eqpmos 0kΩ 56 gs 8 db 5386 RR eqpmos /36.67kΩ 03 gs 3 db R3R eqpmos /0kΩ 304 gs 4 db 6 R4R eqnmos /5kΩ 404 gs 4 db 046 R5R eqpmos /0kΩ 55 gs 4 db 0 c) From the equivalet model, calculate the delay betwee tt ad the time whe VoutVDD/ Assume VDD is much larger tha V T, i.e. VDD>>V T ). 0 ts) The equivalet circuit satisfies the coditios for a R tree see g. 53). Therefore we ca use Eq. 4.3 to fid the equivalet time-costat: τ vout R R R R3) 3 R R3 R4) 4 R R3 R4) 5. 55s The roagatio delay is: T LH 0.69 vout. 76 τ s

4 [PROBLEM MOS aacitace ad Delay 40 ts) I this roblem, you are goig to lear how to calculate various caacitaces of a iverter ad use this iformatio to estimate roagatio delay. Fig. a) a) Use the followig techology arameters from the textbook to calculate the equivalet itlh, ithl, givlh, ad givhl at ode X) of a uit size iverter i show i Fig. a). Examle: itlh meas the itrisic caacitace i Low->High trasitio) Assume the suly is.5v ad the iverter switches at VDD/. Also assume for a uit-size iverter: AS AD 5µm, PS PD.5µm, AS AD 3µm, PS PD 3µm. 0 ts) NMOS PMOS ox 6 /um 6 /um o 3 /um 7 /um j /um /um mj 5 48 jsw 8 /µm /um mjsw 44 3 Φ0 0 0 g g WL. W L W W. givlh giv ox ox o o 86 givhl givlh 86 For the juctio caacitace, let s first calculate eq usig the followig equatio: m φ0 m m eq [ φ0 Vhigh ) φ0 Vlow ) V V ) m) eqhl eqlh high low [0.5).5.5) 5) 5 [0.5).5 0) 5) 0.5) ) 57 79

5 79 0) 0.5) [0 48) 0) eqhl 59.5) 0.5) [0 48).5) eqlh 6.5) 0.5) [0 44).5) eqswhl 8 0) 0.5) [0 44) 0) eqswlh 86 0) 0.5) [0 3) 0) eqswhl 70.5) 0.5) [0 3).5) eqswlh We ca therefore calculate juctio caacitaces: PD AD jsw eqswlh j eqlh dblh 7 PD AD jsw eqswhl j eqhl dbhl 54 PD AD jsw eqswlh j eqlh dblh PD AD jsw eqswhl j eqhl dbhl 79 W W dblh dblh o o LH 3. it W W dbhl dbhl o o HL 84. it

6 Fig. b) b) As show i Fig. b), the first stage ad the secod stage are coected by a 80um log, 5um wide oly wire. Assume Rw 50 Ω/, w 09 /um ad the distributed model for the oly wire; R eqnmos 0 kω ad R eqpmos kω for NMOS ad PMOS i a uit size iverter. Use the equivalet caacitaces you foud i art a) to calculate roagatio delay T dlh ad T dhl. 0 ts) The caacitace ad resistace from the oly wire: l W 0.09 *80 * 5. W w 8 RW Rw l / W ) 50*80 / 5 48Ω Td LH.38RW W 69 ReqNMOS HL ReqNMOSW ReqNMOSgiv LH RW giv LH ReqPMOS LH ) S 0 it it Td HL.38RW W 69 ReqPMOS LH ReqPMOSW ReqPMOSgiv HL RW giv HL ReqNMOS HL) 88. 4S 0 it it

7 [PROBLEM 3 MOS aacitace ad VT revisited 30 ts) A three-trasistor circuit is show i Fig.3. Assume VDD.5V ad iut sigal switches betwee 0 ad VDD with shar rise ad fall times. Use the trasistor arameters below ad igore body effect. All trasistors have miimum legth, L 5 um. The widths of trasistor M ad M: W M um, W M um. NMOS: V T 4, k 5 ua/v, V D,VSAT 6V, λ 0, γ 4 V /, φ f 6V PMOS: V T 4V, k 30 ua/v, V D,VSAT V, λ 0, γ -4 V /, φ f 6V Fig. 3 a) Fid the width of trasistor M3, W M3, such that the switchig threshold of the iverter V M ) is laced i the middle of the V X sigal swig. 0 ts) Hit: fid out the sigal swig at Vx first. Sice we igore body effect, the highest voltage at VxV DD -V T.5-4.; The lowest voltage at Vx We wat to make V M.-0)/.05 which is i the middle of Vx sigal swig. Equatig the short chael curret equatios for both NMOSM3) ad PMOSM) W3 6 W ) ) L L W /W 3 5/30)*[.05-4)*6-36//[ )*-/.46 W 3 W /.46.37um

8 b) If we icrease the width of trasistor M3 leavig the width of trasistor M fixed), i which directio will the VT shift? Exlai how the resizig of M3 affects the VT. 5 ts) The VT will shift to the left side because the NMOS with icreased width has stroger ulldow stregth. c) Fid the t LH delay of this circuit. ox 6/um. Overla caacitaces are o 3 /um. Bottom-late PN juctio caacitaces are /um of device width. Igore the sidewall caacitaces. Igore the imact of rise/fall times o roagatio delay. out 5 ts) We ca divide the delay ito two arts: from Vi to Vx ad from Vx to Vout. Part : From Vi to Vx To estimate the delay i this art, we calculate the Req of M usig this aroximatio: R eqm R eqm,begi R eqm,ed )/. R eqm, begi : Vx.5-4.V) Ix W/L) [.5-4)*6-36/ 497 ma R eqm, begi 4.5 Ω R eqm, ed : Vx.05V) Ix W/L) [.5-4)*6-36/ 497 ma R eq, ed.3 Ω R eqm R eqm,begi R eqm,ed )/ 3.69 Ω eq,vx ox LW o W ) ox LW 3 o W 3 ) db o W 6*5**3*)6*5*.37*3*.37)*3*9.377 t HL, 69*R eq,m eq,vx 50 s Part : From Vx to Vout R eqm ¾*V DD /I DSAT ¾*.5/[W/L).5-4)* Ω eq,vout db db3 * o W o W 3 )out **.37*3*3*.37) t LH, 69R eq,m eq,vout 63. s t LH,total s