EE 505. Lecture 13. String DACs
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1 EE 505 Lecture 13 Strig DACs
2 -Strig DAC V FF S 1 S 2 Simple structure Iheretly mootoe Very low DNL Challeges: S N-2 S N-1 S N S k d k Maagig INL Large umber of devices for large outig thermometer/bubble clocks Switch implemetatio Thevei impedace facig highly code depedet M k Coceptual
3 -Strig DAC V FF V FF /2 S 1 S 1 S 2 S 2 S N-2 S N-2 S N-1 S N-1 S N /2 S N Practical level shift
4 Switch Implemetatio Basic Switch Large umber required for large resolutio Simple structure ofte used φ sigle -chael device Good whe switch termials ear gd Will ot tur o whe termials ear V DD φ sigle p-chael device Good whe switch termials ear V DD Will ot tur o whe termials ear gd φ φ trasmissio gate switch Use devices where cross-over occurs Good for both high ad low term voltages Extra clock sigal required Try to avoid this complexity Other switch structures (such as bootstrapped switch) used but ot for basic strig DACs
5 Switch Assigmet V FF Challeges: S 1 p-chael regio S 2 S N-2 S N-1 -chael regio S N
6 Switch Impedaces SW V G =V DD SWp V G =0V SW_mi SWp_mi V Term V Term V DD V DD -V TH -V THp V DD φ φ
7 Switch Impedaces φ φ SWTG SWTG V Gp =0V,V G =V DD V Gp =0V,V G =V DD Crossover Crossover V Term V Term -V THp V DD -V TH V DD V DD -V THp V DD -V TH SWTG Switch impedace sigificatly both positio ad device size depedet Crossover V Gp =0V,V G =V DD V Term -V THp VDD -V TH V DD
8 Switch Parasitics S G D C GSOL C GDOL φ C BS C GB whe off C GC whe o C BD S G D φ C BS C GSOL C GB whe off C GC whe o C BD C GDOL C WELLSSUB C BD ad C BS ca be sigificat ad cause rise-fall times to be positio depedet C GDOL ca cause kickback or feed-forward C GS ca slow tur-o ad tur-off time of switch
9 -Strig DAC V FF Challeges: S 1 S 2 S N-2 S N-1 S N Maagig INL Large umber of devices for large outig thermometer/bubble clocks(2 or 2 +1 lies) Capacitace o ca be large larger for p-chael devices eve larger for TG switches Switch impedaces positio depedet Kickback from switches to -strig Capacitace o each ode (though small) of - strig from switch Thevei impedace facig highly code depedet
10 -Strig DAC V FF 2 S 1 Biary to Thermometer Decoder S 2 Challeges S N-2 S N-1 S N May output sigals to route Delay i Decoder may be sigificat Delay i Decoder may be previous code ad curret code depedet Itermediate udesired Boolea outputs may occur o o o These may cause udesired opeig ad closig of switches Could mometarily short out taps o -strig Could itroduce trasiets o all odes of -strig that are code ad previous code depedet
11 -Strig DAC V FF M 1 d 1 d 2 2 Biary to Thermometer Decoder M 2 d N-2 M N-2 d N-1 C L M N-1 d N M N Capacitive loadig due to switches
12 -Strig DAC V EF Decoder b 3 b 3 b 2 b 2 b 1 b 1 Uses matrix decoder as aalog MUX Implemets biary to decimal coversio with pass trasistor aalog logic Very structured layout Itercoectio poits are switches (combiatio of -chael ad p-chael) -Strig Challeges Tree Decoder Still may sigals to route Large capacitace o (over 2 +1 diff caps) Multiple previous code depedecies cause output trasitio time to be quite upredictable Cosiderable trasiets itroduced o -strig
13 -Strig DAC V EF Decoder b 3 b 3 b 2 b 2 b 1 b 1 -Strig Tree Decoder Parasitic Capacitaces i Tree Decoder
14 -Strig DAC V EF Decoder Example: < > b 3 b 3 b 2 b 2 b 1 b 1 -Strig V 3 Tree Decoder Previous-Code Depedet Settlig Assume all C s iitially with 0V ed deotes V, black deotes 0V, Purple some other voltage
15 Previous-Code Depedet Settlig Assume all C s iitially with 0V ed deotes V, gree deotes V, black deotes 0V, Purple some other vo V EF -Strig DAC Trasitio from <010> to <101> Example: < > Decoder b 3 b 3 b 2 b 2 b 1 b 1 V 6 -Strig V 3 Tree Decoder
16 Trasitio from <010> to <101> V EF -Strig DAC Decoder b 3 b 3 b 2 b 2 b 1 b 1 White boxes show capacitors depede upo previous code <010> Example: < > V 6 -Strig V 3 Tree Decoder Previous-Code Depedet Settlig Assume all C s iitially with 0V ed deotes V 3, gree deotes V 6, black deotes 0V, Purple some other voltage
17 -Strig DAC V EF Decoder b 3 b 3 b 2 b 2 b 1 b 1 Uses tree decoder as aalog MUX Implemets biary to decimal coversio with pass trasistor aalog logic Very structured layout Itercoectio poits are switches (combiatio of -chael ad p-chael) Dramatically reduces capacitace o output ad switchig capacitaces -Strig Challeges Still may sigals to route Multiple previous code depedecies cause output trasitio time to be quite upredictable Tree Decoder
18 -Strig DAC V DD Decoder b 3 b 3 b 2 b 2 b 1 b 1 Tree Decoder Tree-Decoder i Digital Domai Sigle trasistor used at each marked itersectio to for PTL AND gates Do the resistors that form part of PTL dissipate ay substatial power? No because oly oe will be coductig for ay DAC output
19 -Strig DAC Strig DAC with ow-colum Decoder V EF F F F F F Colum Decoder F F F F F F F 2 = 1:2 1 Dramatic reductio i decoder complexity Dramatic reductio of capacitive loadig o output Chages decoder from a oedimesioal to a two-dimesioal solutio (ca be thought of as foldig) Logic gates could be placed at each ode to elimiate aalog row decoder F F F F F F F F F F F F F F F F F F F F ow Decoder Challeges (most were preset i earlier structures too) Some previous code depedece INL large Difficult to cacel gradiet effects i layout Switchig sequecig ca help a lot Switch impedaces code depedet Settlig times code depedet
20 -Strig DAC V EF F F F F F Colum Decoder F F F F F F F 2 = 1:2 1 Ca this cocept be exteded further? Dramatic reductio i decoder complexity Dramatic reductio of capacitive loadig o output Chages decoder from a oedimesioal to a m-dimesioal solutio (foldig) Logic gates could be placed at each ode to elimiate aalog row decoder F F F F F F F F F F F F F F F F ow Decoder F F F F
21 -Strig DAC What about this parallel -strig? V FF S 1 Added two resistors tapped at middle of origial -strig 1 S 2 1 S N-2 S N-1 S N
22 -Strig DAC What about this parallel -strig? V FF Added six resistors tapped at middle of origial -strig 1 S 1 2 S S N-2 S N-1 1 S N
23 -Strig DAC V EF MSB ow Decoder 2 1 LSB Aalog MUX 2 2
24 -Strig DAC V EF = 1:2 1 2 F F F F C F F F F F F F F C F F F F F F F F C F F F F F F F F Colum Decoder ow Decoder C F F F F Note Dual Ladder is used!
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