EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances

Size: px
Start display at page:

Download "EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances"

Transcription

1 EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances

2 Parasitic Capacitors in MOSFET (will initially consider two)

3 Parasitic Capacitors in MOSFET C GCH

4 Parasitic Capacitors in MOSFET Recall that pn junctions have a depletion region!

5 Parasitic Capacitors in pn junction capacitance MOSFET C Depletion Region For V FB <φ B /2 C JO A C φ B V FB C = CA J0 V 1- φ FB B m

6 Parasitic Capacitors in pn junction capacitance MOSFET The bottom and the sidewall:

7 Parasitic Capacitors in pn junction capacitance MOSFET C Depletion Region For a pn junction capacitor C = BOT C A BOT V 1- φ C =C A+C P J BOT SW FB B m C = SW C P SW V 1- φ FB B m

8 Question Are the parasitic capacitors relevant?

9 Observation Parasitic Capacitors are Small Consider a minimum-sized transistor 2l 3l 4l

10 Process Parameters from AMI 0.5u Process PROCESS PARAMETERS Sheet Resistance Contact Resistance Gate Oxide Thickness N+ACTV P+ACTV POLY PLY2_ 1120 HR POLY MTL MTL UNITS ohms/sq ohms angstrom PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL N\PLY 822 N WELL 812 ohms/sq ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS Area (substrate) Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active) l=.35 microns N+ACTV P+ACTV POLY POLY2 969 M M M N_WELL 39 UNITS af/um^2 af/um^2 af/um^2 af/um^2 af/um^2 af/um^2 af/um^2 af/um af/um af/um af/um af/um af/um

11 Size of Capacitances Gate-Channel Capacitance = 6l 2 x 2.47fF/m 2 = 1.82fF Source Diffusion-Substrate Capacitance = 12l 2 x.424ff/m l x.315ff/m =.624fF fF =2.16fF Note Sidewall Capacitance larger than Bottom Capacitance Are these negligible?

12 Are these negligible? These small capacitors play the dominant role in the speed limitations of most digital circuits These small capacitors play a major role in the performance of many linear circuits It is essential that these capacitors (parasitic capacitors) be considered and managed when designing most integrated circuits today!

13 Types of Capacitors 1. Fixed Capacitors a. Fixed Geometry b. Junction 2. Operating Region Dependent a. Fixed Geometry b. Junction

14 Parasitic Capacitors in MOSFET Fixed Capacitors

15 Parasitic Capacitors in MOSFET Fixed Capacitors C GSO C GDO Overlap Capacitors: C GDO, C GSO

16 Parasitic Capacitance Summary D C GD G B C GS Cutoff Ohmic Saturation C GS CoxWL D CoxWL D CoxWL D C GD CoxWL D CoxWL D CoxWL D L D is a model parameter S

17 Parasitic Capacitors in MOSFET Fixed Capacitors C BS1 C BD1 Junction Capacitors: C BS1, C BD1

18 Parasitic Capacitors in MOSFET Fixed Capacitors C GSO C GDO C BS1 C BD1 Overlap Capacitors: C GDO, C GSO Junction Capacitors: C BS1, C BD1

19 Fixed Parasitic Capacitance Summary C GD D C BD G C GS C BS B C BOT and C SW are model parameters Cutoff Ohmic Saturation C GS CoxWL D CoxWL D CoxWL D C GD CoxWL D CoxWL D CoxWL D C BG C BS C BS1 = C BOT A S +C SW P S C BS1 = C BOT A S +C SW P S C BS1 = C BOT A S +C SW P S C BD C BD1 = C BOT A D +C SW P D C BD1 = C BOT A D +C SW P D C BD1 = C BOT A D +C SW P D S

20 Parasitic Capacitors in MOSFET Operation Region Dependent

21 Parasitic Capacitors in MOSFET Operation Region Dependent -- Cutoff C GBCO Cutoff Capacitor: C GBCO

22 Parasitic Capacitors in MOSFET Operation Region Dependent -- Cutoff C GBCO Note: A depletion region will form under the gate if a positive Gate voltage is applied thus decreasing the capacitance density Cutoff Capacitor: C GBCO

23 Parasitic Capacitors in MOSFET Operation Region Dependent and Fixed -- Cutoff C GSO C GDO C BS1 C GBCO C BD1 Overlap Capacitors: C GDO, C GSO Junction Capacitors: C BS1, C BD1 Cutoff Capacitor: C GBCO

24 Parasitic Capacitance Summary C GD D C BD G B C GS C BS S C BG Cutoff Ohmic Saturation C GS CoxWL D CoxWL D CoxWL D C GD CoxWL D CoxWL D CoxWL D C BG CoxWL (or less) C BS C BOT A S +C SW P S C BS1 = C BOT A S +C SW P S C BS1 = C BOT A S +C SW P S C BD C BOT A D +C SW P D C BD1 = C BOT A D +C SW P D C BD1 = C BOT A D +C SW P D

25 Parasitic Capacitors in MOSFET Operation Region Dependent -- Ohmic C GCH C BCH Note: The Channel is not a node in the lumped device model so can not directly include this distributed capacitance in existing models Note: The distributed channel capacitance is usually lumped and split evenly between the source and drain nodes Ohmic Capacitor: C GCH, C BCH

26 Parasitic Capacitors in MOSFET Operation Region Dependent and Fixed -- Ohmic C GSO C GCH C GDO C BCH C BS1 C BD1 Overlap Capacitors: C GDO, C GSO Junction Capacitors: C BS1, C BD1 Ohmic Capacitor: C GCH, C BCH

27 Parasitic Capacitance Summary C GD D C BD G B C GS C BS S C BG Cutoff Ohmic Saturation C GS CoxWL D CoxWL D CoxWL D C GD CoxWL D CoxWL D CoxWL D C BG CoxWL (or less) C BS C BOT A S +C SW P S C BS1 = C BOT A S +C SW P S C BS1 = C BOT A S +C SW P S C BD C BOT A D +C SW P D C BD1 = C BOT A D +C SW P D C BD1 = C BOT A D +C SW P D

28 Parasitic Capacitors in MOSFET Operation Region Dependent -- Saturation C GCH C BCH Note: Since the channel is an extension of the source when in saturation, the distributed capacitors to the channel are generally lumped to the source node Saturation Capacitors: C GCH, C BCH

29 Parasitic Capacitors in MOSFET Operation Region Dependent and Fixed --Saturation C GSO C BS1 C GCH C BCH C GDO C BD1 Overlap Capacitors: C GDO, C GSO Junction Capacitors: C BS1, C BD1 Saturation Capacitors: C GCH, C BCH

30 Parasitic Capacitance C GD Summary D C BD G B C GS C BS S C BG Cutoff Ohmic Saturation C GS CoxWL D CoxWL D + 0.5C OX WL CoxWL D +(2/3)C OX WL C GD CoxWL D CoxWL D + 0.5C OX WL CoxWL D C BG CoxWL (or less) 0 0 C BS C BOT A S +C SW P S C BOT A S +C SW P S +0.5WLC BOTCH C BOT A S +C SW P S +(2/3)WLC BOTCH C BD C BOT A D +C SW P D C BOT A D +C SW P D +0.5WLC BOTCH C BOT A D +C SW P D

31 Parasitic Capacitance Summary C GD D C BD G B C GS C BS S C BG Cutoff Ohmic Saturation C GS CoxWL D CoxWL D + 0.5C OX WL CoxWL D +(2/3)C OX WL C GD CoxWL D CoxWL D + 0.5C OX WL CoxWL D C BG CoxWL (or less) 0 0 C BS C BOT A S +C SW P S C BOT A S +C SW P S +0.5WLC BOTCH C BOT A S +C SW P S +(2/3)WLC BOTCH C BD C BOT A D +C SW P D C BOT A D +C SW P D +0.5WLC BOTCH C BOT A D +C SW P D

32 R-String DAC V REF X IN n Decoder b 3 b 3 b 2 b 2 b 1 b 1 R-String V OUT Tree Decoder Parasitic Capacitances in Tree Decoder

33 R-String DAC V REF X IN n Decoder Example: < > b 3 b 3 b 2 b 2 b 1 b 1 R-String V OUT V 3 Tree Decoder Previous-Code Dependent Settling Assume all C s initially with 0V Red denotes V, black denotes 0V, Purple some other voltage

34 Previous-Code Dependent Settling Assume all C s initially with 0V Red denotes V, green denotes V, black denotes 0V, Purple some other vo V REF R-String DAC Transition from <010> to <101> X IN n Example: < > Decoder b 3 b 3 b 2 b 2 b 1 b 1 V 6 R-String V OUT V 3 Tree Decoder

35 Transition from <010> to <101> V REF R-String DAC X IN n Decoder b 3 b 3 b 2 b 2 b 1 b 1 White boxes show capacitors dependen upon previous code <010> Example: < > V 6 R-String V OUT V 3 Tree Decoder Previous-Code Dependent Settling Assume all C s initially with 0V Red denotes V 3, green denotes V 6, black denotes 0V, Purple some other voltage

36 R-String DAC V OUT V DD Decoder b 3 b 3 b 2 b 2 b 1 b 1 Tree Decoder Tree-Decoder in Digital Domain Single transistor used at each marked intersection to for PTL AND gates Do the resistors that form part of PTL dissipate any substantial power? No because only one will be conducting for any DAC output

37 R-String DAC V REF X IN n Decoder b 1 b 1 b 2 b 2 b 3 b 3 R-String V OUT Tree Decoder

38 End of Lecture 37

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

More information

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer? EE 330 Exam 1 Spring 2017 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.

More information

2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor?

2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor? EE 330 Exam 1 Spring 2018 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.

More information

Exam 2 Fall How does the total propagation delay (T HL +T LH ) for an inverter sized for equal

Exam 2 Fall How does the total propagation delay (T HL +T LH ) for an inverter sized for equal EE 434 Exam 2 Fall 2006 Name Instructions. Students may bring 2 pages of notes to this exam. There are 10 questions and 5 problems. The questions are worth 2 points each and the problems are all worth

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

EE382M-14 CMOS Analog Integrated Circuit Design

EE382M-14 CMOS Analog Integrated Circuit Design EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

Digital Microelectronic Circuits ( )

Digital Microelectronic Circuits ( ) Digital Microelectronic ircuits (361-1-3021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

LAYOUT TECHNIQUES. Dr. Ivan Grech

LAYOUT TECHNIQUES. Dr. Ivan Grech LAYOUT TECHNIQUES OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout Layout Techniques Main Layers in a typical Double-Poly, Double-Metal

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered

More information

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model

More information

EE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes

EE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes EE 434 Lecture 12 Process Flow (wrap up) Device Modeling in Semiconductor Processes Quiz 6 How have process engineers configured a process to assure that the thickness of the gate oxide for the p-channel

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Practice 7: CMOS Capacitance

Practice 7: CMOS Capacitance Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

The K-Input Floating-Gate MOS (FGMOS) Transistor

The K-Input Floating-Gate MOS (FGMOS) Transistor The K-Input Floating-Gate MOS (FGMOS) Transistor C 1 V D C 2 V D I V D I V S Q C 1 C 2 V S V K Q V K C K Layout V B V K C K Circuit Symbols V S Control Gate Floating Gate Interpoly Oxide Field Oxide Gate

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

The Gradual Channel Approximation for the MOSFET:

The Gradual Channel Approximation for the MOSFET: 6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis.

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis. June 26, 2004 oal of this chapter Chapter 2 MO Transistor Theory oonchuay upmonchai Integrated esign Application Research (IAR) Laboratory June 16th, 2004; Revised June 16th, 2005 q Present intuitive understanding

More information

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law

More information

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

More information

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

More information

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers 6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

More information

ECE321 Electronics I

ECE321 Electronics I EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling? LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

More information

Figure 1: MOSFET symbols.

Figure 1: MOSFET symbols. c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

The Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

The Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS

More information

Page 1 of (2 pts) What is the purpose of the keeper transistor in a dynamic logic gate?

Page 1 of (2 pts) What is the purpose of the keeper transistor in a dynamic logic gate? Page 1 of 6 EE 434 Exam 2 Fall 2004 Name Instructions: nswer the following questions and solve the following problems. In problems relating to timing or delay calculations, assume you are working in a

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two - 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

More information

EE 330 Homework 5 Spring 2017 (This assignment will not be collected or graded)

EE 330 Homework 5 Spring 2017 (This assignment will not be collected or graded) EE 330 Homework 5 Spring 2017 (This assignment will not be collected or graded) Assume the CMOS process is characterized by model parameters V TH =1V and µc OX =100µA/V 2. If any other model parameters

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

MOS Capacitors ECE 2204

MOS Capacitors ECE 2204 MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

More information

EE 330 Lecture 14. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs

EE 330 Lecture 14. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs EE 330 Lecture 14 Devices in Semiconuctor Processes Dioes Capacitors MOSFETs Reminer: Exam 1 Friay Feb 16 Stuents may bring one page of notes (front an back) but no electronic ata storage or remote access

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

Design of Analog Integrated Circuits

Design of Analog Integrated Circuits Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

Lecture 11: J-FET and MOSFET

Lecture 11: J-FET and MOSFET ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information