LAYOUT TECHNIQUES. Dr. Ivan Grech

Transcription

1 LAYOUT TECHNIQUES

2 OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout

3 Layout Techniques Main Layers in a typical Double-Poly, Double-Metal Process: Polysilicon - 1 Polysilicon - 2 Metal - 1 Metal - 2 N-Diffusion P-Diffusion Contacts (Vias) Metal-1 / Metal -2 Metal-1 / N-Diffusion Metal-1 / P-Diffusion Metal-1 / Polysilicon-1 Metal-1 / Polysilicon-2 Substrate is usually p-type (need n-well/tub for PMOS)

4 Basic layout of an MOS transistor

5 MOS Transistor Layout I Accurate aspect ratio (rectangular structures only) Minimise parasitic resistance in series with source and drain contacts (use multiple contacts) Reduce gate series resistance by minimising PolySi length (affects frequency response) Split transistors with large W/L ratio into smaller transistors in parallel: reduction in gate resistance reduction source/drain resistance reduction of substrate parasitic capacitance

6 Layout of an MOS transistor

7 Poor/Correct Layout of an MOS transistor

8 Wide transistor split into n parallel parts

9 Layout of a split transistor (n = 4)

10 Layout of a differential pair (a) Normal (b) Interdigitated (c) Common Centroid

11 Charge injection cancellation

12 MOS Transistor Layout II For matched transistors: Same orientation Same boundary conditions (use dummy devices) Physically close Interdigitized structures (e.g. differential pairs) Common centroid method Avoid minimum size structures

13 Resistor Layout I Resistor types Polysilicon 1 / 2 Diffusion (P + / N + ) Well - used for high value resistors Resistance determine by layer sheet resistance: R=R L/W For linear resistors: Polysilicon is used (other types of resistors are voltage dependent) There is also a problem of maximum signal swing for diffusion & well resistors - require that parasitic p-n junction remains reverse biased For well resistors, substrate diffusions need to be placed in order to achieve insulation between adjacent strips

14 Resistor layouts

15 Resistor Layout II Usually large L-values are required to achieve adequate resistance - use of serpentine structures Main problems: Corners (difficult to estimate actual value - estimated as /2) Undercut causes width reduction - use large width to limit random component undercut variations Undercut is a function of boundary conditions - use dummy strips suitable terminations have to be used (ohmic contacts only ) - depend on resistive layer used resistance variation with position - use common centriod & interdigitized structures temperature effects can be reduced by placing resistors on the same isotherm shielding has to be used in mixed mode ICs

16 Layout of a resistor made by well diffusion

17 Layout of 2 matched interdigitated resistors

18 Matched devices on the same isotherm

19 Capacitor Layout I Layers used for capacitors plates: metal, poly, diffusions Layers used as dielectric silicon oxide or polysilicon oxide Most common linear capacitor (used in SC / SI blocks) Poly1 - Poly2 capacitor Capacitance given by: C = ε 0 ε R A/t (1-10pF typical C) Capacitance value is determined by the smaller plate area For good matching capacitor values should be an integer multiple of some unit capacitor value (usually pf)

20 Polysilicon-diffusion capacitor

21 Layout of two matched capacitors Common Centroid Symmetry

22 Polysilicon-polysilicon capacitor with shielding well

23 Capacitor Layout II Problems associated with integrated capacitors: Undercut effect A* = WL(1-αP/A) i.e actual area affected by Perimeter/Area (P/A) ratio Parasitic capacitance (especially to substrate - can be non-linear) Field fringing effects (often neglected in calculation) In order to achieve good capacitor matching: Use common centroid arrangement Dummy boundary devices Use same P/A ratio in the layout of capacitors whose values are not integer multiples of a unit value Use a protective (shielding) well surrounded by a guard ring (substrate contacts) Use matched metal lines and terminations

24 Layout of a non-integer multiple of a unit capacitor

25 Layout-Oriented Design Determine components to be matched Accuracy should rely on component ratios rather than absolute values Each component should be sized to be an integral number of a unit size Components to be matched should be physically placed near to each other Avoid minimum dimensions on components to be accurately matched Design performance (at least to a first order approximation) should be independent of : temperature V T absolute component values intrinsic transconductance