Microelectronic Devices and Circuits Lecture 13  Linear Equivalent Circuits  Outline Announcements Exam Two 


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1 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large signal models, w. charge stores pn diode, BJT, MOSFET (subthreshold and strong inversion) Small signal models; linear equivalent circuits General two, three, and four terminal devices pn diodes: Linearizing the exponential diode Adding linearized charge stores BJTs: Linearizing the F.A.R. βmodel Adding linearized charge stores MOSFETs: Linearized strong inversion model Linearized subthreshold model Adding linearized charge stores Clif Fonstad, 10/27/09 Lecture 13 Slide 1
2 Subthreshold Operation of MOSFETs, cont. t ox 0 x D t n The barrier at the n p junction is lowered near the oxidesi interface for any v GS > V FB. The barrier is lowered by φ(x) φ p for 0 < x < x D. (This is the effective v BE on the lateral BJT between x and x dx.) V FB < v GS < V φ(0,y) T G v S DS > 0 D φ n v DS x Injection n n p v BS = 0 The barrier lowering (effective forward bias) (1) is controlled by v GS, and (2) decreases quickly with x. v BE,eff (x) B 0 L y = [φ(x) φ p ] v GS φp Clif Fonstad, 10/27/09 Injection occurs over this range, Lecture 13 Slide 2 but is largest near x = 0. φ p φ(x) φ p φ n φ p φ(x) 0 φ(x)φ p L φ(0) Plot vs y at fixed x, 0 < x < x D. Plot vs x at fixed y, 0 < y < L. φ m t ox x d x y
3 Subthreshold Operation of MOSFETs, cont. To calculate i D, we first find the current in each dx thick slab: S V FB < v GS < V T G v DS > 0 D t ox 0 x xdx n n p x D v BS = 0 x n' x,0 0 L ( ) $ n i e q"(x,v GS )/ kt n' x,l ( ) = n i e q"(x,v GS )/ kt #1 n'(x,0) " n'(x,l) di D (x) = qd e L Clif Fonstad, 10/27/09 y ( ) " n' x,0 ( )e #qv DS / kt W dx # W L D e qn i 1" e "qv DS ( / kt ) )e q$(x,v GS )/ kt dx Lecture 13 Slide 3
4 Subthreshold Operation of MOSFETs, cont. Integrating this from x = 0 to x = x D using the approximate value for the integral derived in Lecture 9, and approximating the relationship between Δφ(0) and Δv GS as linear, i.e. Δφ(0) Δv GS /n, we arrived at: i D, s"t (v GS,v DS,0) # W L µ $ * kt ' e C ox & ) % q ( where & ( n " ' 1 1 * )( C ox # Si qn A [ ] 2 $2% p 2 [ n "1] e q { v GS "V T } nkt 1" e "qv DS / kt ( ) * (,( = Variations on this form: It is common to see i D,st written using the factors K and γ we defined earlier, and with kt/q replaced by V t, the thermal voltage, and [n 1] replaced in the prefactor. Written this way, we have: ( ) 2 $ i D,s"t (v GS,v DS,0) # K V t 2 ["2% p ] e { vgs "VT } nv t 1" e "v DS /V t with " # 2$ qn Si A, K # W (, * L µ * " * ec * ox, n(v BS ) % ) 1 [ ] C ox * 2 &2' p & v BS. * Clif Fonstad, 10/27/09 Lecture 13 Slide 4
5 Subthreshold Output Characteristic We plot a family of i D vs v DS curves with (v GS V T ) as the family variable, after first defining the subthreshold diode saturation current, I S,st : 2 $ I S,s"t # K V t [ ] 2 "2% p = KV 2 t [ n "1] 10 1 I S,st 10 2 I S,st 10 3 I S,st 10 4 I S,st log i D,st (v GS V T ) = 0.06xn Volts (v GS V T ) = 0.12xn Volts (v GS V T ) = 0.18xn Volts (v GS V T ) = 0.24xn Volts v DS { i D,s"t (v GS,v DS,0) # I S,s"t e v GS "V T } nv t 1" e "v DS /V t ( ) Clif Fonstad, 10/27/09 Lecture 13 Slide 5
6 Large Signal Model for MOSFET Operating Subthreshold The large signal model for a MOSFET operating in the weak inversion or subthreshold region looks the same model as that for a device operating in strong inversion (v GS > V T ) EXCEPT there is a different equation relating i D to v GS, v DS, and v BS : We will limit our model to v GS " V T, v DS > 3V t and v BS = 0. D i D G i G (= 0) i D (v GS, v DS ) i G,s"t (v GS,v DS,v BS ) = 0 S,B { i D,s"t (v GS,v DS,0) # I S,s"t ( 1" $v DS )e v GS "V To } nv t 1" e "v DS /V t ( ) 1 for v DS > 3 V t Early effect Clif Fonstad, 10/27/09 Lecture 13 Slide 6
7 Large signal models with charge stores: A pn diode: BJT: npn (in F.A.R.) B IBS qbc ib IBS B C qab!fib q AB : Excess carriers on pside plus excess carriers on nside plus junction depletion charge. q BE : Excess carriers in base plus EB junction depletion charge q BC : CB junction depletion charge MOSFET: nchannel G qg qbe D E qdb id B q G : Gate charge; a function of v GS, v DS, and v BS. q DB : DB junction depletion charge q SB : SB junction depletion charge Clif Fonstad, 10/27/09 S qsb Lecture 13 Slide 7
8 Signal notation: A transistor circuit, whether digital or analog, is typically connected to several DC power supplies that establish the desired DC "bias" currents and voltages throughout it. It also typically has one or more time varying input signals that result in time varying currents and voltages (one of which is the desired output of the circuit) being added to the DC bias currents and voltages. Each voltage and current in such a circuit thus has a DC bias portion and a signal portion, which add to make the total. We use the following notation to identify these components and the total: i A (t) = I A i a (t) v AB (t) = V AB v ab (t) Total: lowercase letter and uppercase subscript. Bias: uppercase letter and subscript. Signal: lowercase letter and subscript. Clif Fonstad, 10/27/09 Lecture 13 Slide 8
9 DC Bias Values: To construct linear amplifiers and other linear signal processing circuits from nonlinear electronic devices we must use regions in the nonlinear characteristics that are locally linear over useful current and voltage ranges, and operate there. To accomplish this we must design the circuit so that the DC voltages and currents throughout it "bias" all the devices in the circuit into their desired regions, e.g. yield the proper bias currents and voltages: I A, I B, I C, I D, etc. and V AG, V BG, V CG,V DG, etc. This design is done with the signal inputs set to zero and using the large signal static device models we have developed for the nonlinear devices we studied: diodes, BJTs, MOSFETs. Working with these models to get the bias values, though not onerous, can be tedious. It is not something we want to have to do to find voltages and currents when the signal inputs are applied. Instead we use linear equivalent circuits. Clif Fonstad, 10/27/09 Lecture 13 Slide 9
10 Linear equivalent circuits: After biasing each nonlinear devices at the proper point the signal currents and voltages throughout the circuit will be linearly related for small enough input signals. To calculate how they are related, we make use of the linear equivalent circuit (LEC) of our circuit. The LEC of any circuit is a combination of linear circuit elements (resistors, capacitors, inductors, and dependent sources) that correctly models and predicts the firstorder changes in the currents and voltages throughout the circuit when the input signals change. A circuit model that represents the proper first order linear relationships between the signal currents and voltages in a nonlinear device is call an LEC for that device. Our next objective is to develop LECs for each of the nonlinear devices we have studied: diodes, BJTs biased in their forward active region (FAR), and MOSFETs biased in their subthreshold and strong inversion FARs. Clif Fonstad, 10/27/09 Lecture 13 Slide 10
11 Creating a linear equivalent circuit, LEC: Consider a device with three terminals, X, Y, and Z: q X (v XZ, v XY ) q Y (v YZ, v YX ) X i X (v XZ, v YZ ) i Y (v XZ, v YZ ) Y Z Suppose, as is our situation with the large signal device models we have developed in 6.012, that we have expressions for the currents into terminals X and Y in terms of the voltages v XZ and v YZ : i X (v XZ,v YZ ) and i Y (v XZ,v YZ ) and that we similarly have expressions for the charge stores associated with terminals X and Y: q X (v XZ,v YZ ) and q Y (v XZ,v YZ ) Clif Fonstad, 10/27/09 Lecture 13 Slide 11
12 Creating an LEC, cont.: We begin with our static model expressions for the terminal characteristics, and write a Taylor's series expansion of them about a bias point, Q, defined as a specific set of v XZ and v YZ that we write, using our notation, as V XZ and V YZ For example, for the current into terminal X we have: i X (v XZ,v YZ ) = i X (V XZ,V YZ ) "i X (v XZ #V XZ ) "i X YZ #V YZ ) "v XZ "v Q YZ Q(v 1 2 " 2 i X 2 "v XZ Q (v XZ #V XZ ) 2 1 " 2 i X 2 2 "v YZ YZ #V YZ ) Q(v 2 1 " 2 i X (v XZ #V XZ )(v YZ #V YZ ) even higher order terms 2 "v XZ "v YZ Q For sufficiently small* (v XZ V XZ ) and (v YZ V YZ ), the second and higher order terms are negligible, and we have: i X (v XZ,v YZ ) " i X (V XZ,V YZ ) #i X (v XZ $V XZ ) #i X (v YZ $V YZ ) #v XZ #v Q YZ Q i X (V XZ,V YZ ) = I X (V XZ,V YZ ) [ v XZ "V XZ ] # v xz [ v YZ "V YZ ] # v yz Clif Fonstad, 10/27/09 Lecture 13 Slide 12 * What is "sufficiently small" is determined by the magnitude of the higher order derivatives.
13 Creating an LEC, cont.: So far we have: Next we define: i X (v XZ,v YZ ) " I X (V XZ,V YZ ) # $i X v xz $i X v yz $v XZ $v Q YZ Q [ i X " I X ] # i x "i X "v XZ Q # g i "i X "v YZ Q Replacing the partial derivatives with the conductances we have defined, gives us our working form of the linear equation relating the incremental variables: i x " g i v xz g r v yz Doing the same for i Y, we arrive at i y " g f v xz g o v yz g f # $i Y where $v XZ Q A circuit matching these relationships is seen below: x v xz z i x g i g r v yz g f v xz g o # $i Y $v YZ Q Clif Fonstad, 10/27/09 Lecture 13 Slide 13 g o i y y v yz z # g r
14 Creating an LEC, cont.: This linear equivalent circuit is only good at low frequencies: i x x y v g xz g r v yz g f v g v i o yz xz z z To handle high frequency signals, we linearize the charge stores' dependencies on voltage also. q X (v XZ, v XY ) q Y (v YZ, v YX ) i y Z Their LECs are linear capacitors: "q X "v XZ Q X i X (v XZ, v YZ ) i Y (v XZ, v YZ ) # C xz "q Y "v YZ Q # C yz "q X "v XY Q Y $ # C xy = "q Y & % "v YX Q Clif Fonstad, 10/27/09 Lecture 13 Slide 14 ' ) (
15 Creating an LEC, cont.: Adding these to the model yields: i x C x xy y v C xz xz g i g o v g g f v r v yz C yz yz xz z z Two important points: #1 All of the elements in this LEC depend on the bias point, Q: g i = "i X, g r = "i X, g f = "i Y, g o = "i Y, C xz = "q X, C xy = "q X, C yz = "q Y "v XZ "v Q YZ "v Q XZ "v Q YZ "v Q XZ "v Q XY "v Q YZ Q #2 The devicespecific nature of an LEC is manifested in the dependences of the element values on the bias currents and voltages, rather than in the topology of the LEC. Thus, different devices may have LECs that look the same. (For example, the BJ and FET LECs may look similar, but some of the elements depend much differently on the bias point values.) Clif Fonstad, 10/27/09 Lecture 13 Slide 15 i y
16 Linear equivalent circuit (LEC) for pn diodes (low f): We begin with the static model for the terminal characteristics: i D (v AB ) = I S e qv AB kt "1 [ ] Linearizing i D about V AB, which we will denote by Q (for quiescent bias point): i D (v AB ) " i D (V AB ) #i D #v AB Q [ v AB $V AB ] IBS I S A id We define the equivalent incremental conductance of the diode, g d, g d " #i D #v AB Q = q kt I S eqv AB / kt $ and we use our notation to write: I D = i D (V AB ), ending up with qi D kt i d = [ i D " I D ], v ab = [ v AB "V AB ] i d = g d v ab The corresponding LEC is shown at right: id a g d b B vab vab g d " q I D kt Clif Fonstad, 10/27/09 Lecture 13 Slide 16
17 LEC for pn diodes (high f): At high frequencies we must include the charge store, q AB, and linearize its two components*: A q DP (v AB ) = "AqN Ap x p q AB = q DP q QNR,p"side Depletion layer charge store, q DP, and its linear equivalent capacitance, C dp : ( v AB ) # "A 2q$ Si N Ap % b " v AB ( ) IBS B qab C dp (V AB ) & 'q DP 'v AB Q = A q$ Si N Ap ( ) 2 % b "V AB a Diffusion charge store, q QNR,pside, and its linear equivalent capacitance, C df : q QNR,p"side (v AB ) = i D[ w p " x p ] 2 2D e C df (V AB ) " #q QNR,p$side #v AB Q = q I D kt [ w p $ x p ] 2 g d b C d [ ] 2 = g d % d with % d " w p $ x p 2D e 2D e Clif Fonstad, 10/27/09 Lecture 13 Slide 17 * This discusion assumes an n p diode)
18 Linear equivalent circuit for BJTs in FAR (low f): In the forward active region, our static model says: [ ] i B (v BE,v CE ) = I BS e qv BE kt "1 i C (v BE,v CE ) = # o [ 1 $v CE ]i B (v BE,v CE ) = # o I BS e qv BE kt "1 [ ] 1 $v CE [ ] We begin by linearizing ic about Q: i c (v be,v ce ) = "i C v be "i C v ce = g m v be g o v ce "v BE "v Q CE Q We introduced the transconductance, g m, and the output conductance, g o, defined as: g m " #i C #v BE Q g o " #i C #v CE Q Evaluating these partial derivatives using our expression for i C, we find: g m = q kt " I o BS eqv kt BE [ 1 #V CE ] $ qi C kt [ ] # $ # I C or $ I C ' g o = " o I BS e qv BE kt 1 Clif Fonstad, 10/27/09 Lecture 13 Slide 18 % & V A ( * )
19 LEC for BJTs (low f), cont.: Turning next to i B, we note it only depends on v BE so we have: i b (v be ) = "i B v be = g # v be "v BE Q The input conductance, g π, is defined as: g " # $i B $v BE Q (Notice that we do not define g π as qi B /kt) To evaluate g π we do not use our expression for i B, but instead use i B = i C /β o : g " # $i B = 1 $i C = g m = q I C $v BE % Q o $v BE % Q o kt % o Representing this as a circuit we have: i b b c v be g! v! g m v! g o e e Clif Fonstad, 10/27/09 (Notice that v be is also called v π ) Lecture 13 Slide 19 i c v ce
20 LEC for BJTs (high f): To extend the model to high frequency we linearize the charge stores associated with the junctions and add them. The basecollector junction is reverse biased so the charge associated with it, q BC, is the depletion region charge. The corresponding capacitance is labeled C µ. B qbc qbe ib IBS C E!FiB q BC (v BC ) " #A 2q$ Si [% b,bc # v BC ]N DC C µ (V BC ) " #q BC #v BC Q = A q$ Si N DC [ ] 2 % b &V BC The baseemitter junction is forward biased and its dominant charge store is the excess charge injected into the base; the baseemitter depletion charge store less important. 2 D q BE (v BE ) " Aqn e i e qv BE / [ kt #1] " w 2 B, eff i C (v BE ) N AB w B, eff 2D e The linear equivalent capacitance is labeled C π. Clif Fonstad, 10/27/09 Lecture 13 Slide 20
21 LEC for BJTs (high f), cont: C π can be written in terms of g m and τ b : C " (V BE ) # $q BE $v BE Q % w 2 B,eff 2D e qi C kt = g m& b " b # w B,eff 2 D e Adding C π and C µ to our BJT low frequency LEC we get the full BJT LEC: i b C µ i c b c v be g! v! g m v! g o C! e e 2 v ce Clif Fonstad, 10/27/09 g m = q I C kt g " = g m # F ( ) g o = $ I C = I C V A C µ C % = A = g m & b q" Si N DC [ ] 2 # b $V BC Lecture 13 Slide 21
22 LEC for MOSFETs in saturation (low f): In saturation, our static model is: (Recall that α 1) i G (v GS,v DS,v BS ) = 0 i B (v GS,v DS,v BS ) " 0 i D (v GS,v DS,v BS ) = K 2# v $V v GS T ( BS) [ ] 2 [ 1 %( v DS $V DS,sat )] with K & W L µ * ec ox and V T = V To '( 2( p$si $ v BS $ 2( ) p$si Note that because i G and i B are zero they are already linear, and we can focus on i D. Linearizing i D about Q we have: i d (v gs,v ds,v bs ) = "i D "v GS Q v gs "i D v ds "i D v bs "v DS "v Q BS Q = g m v gs g o v ds g mb v bs We have introduced the transconductance, g m, output conductance, g o, and substrate transconductance, g mb : g m " #i D #v GS Q g o " #i D #v DS Q g mb " #i D #v BS Q Clif Fonstad, 10/27/09 Lecture 13 Slide 22
23 LEC for MOSFETs in saturation (low f), cont.: A circuit containing all these elements, i.e. the actual LEC, is: i g g d v gs v g m v gs g mb v bs g ds o s s v bs i b b Evaluating the conductances in saturation we find: i d g m " #i D #v GS Q g o " #i D #v DS Q = K [ $ V %V (V ) GS T BS ][ 1 &V DS ] ' 2K I D $ = K [ 2$ V %V (V ) GS T BS ] 2 & ' & I D g mb " #i D #v BS Q = % K [ $ V GS %V T (V BS )][ 1 &V DS ] #V T #v BS Q = ( g m Clif Fonstad, 10/27/09 Lecture 13 Slide 23
24 LEC for MOSFETs in saturation (high f): For the high frequency model we qdb linearize and add the charge qg stores associated with each pair id of terminals. G Two, q SB and q DB, are depletion region charge stores associated qsb with the n regions of the source S and drain. They are relatively straightforward compared to q G., as we will see below. q SB and q DB contribute two capacitors, C sb and C db, to our LEC. The gate charge, q G, depends in general on v GS, v DS, and v GB (= v GS v BS ), but in saturation, q G only depends on v GS and v GB (i.e. v GS and v BS ) in our model, adding C gs and C gb. When v GS V T the drain is ideally decoupled from the gate, but in any real device there is fringing capacitance between the gate electrode and the drain diffusion that we must include as C gd, a parasitic element. Clif Fonstad, 10/27/09 Lecture 13 Slide 24 D B
25 LEC for MOSFETs in saturation (high f), cont.: Adding all these capacitors to our LEC yields: g i g C gd i d d v gs s C gs g m v gs g mb v bs g o s We find the following results: C gs " #q G #v GS Q v bs C sb C db v ds b i b = 2 3 W LC * ox C gb C sb,c gb,c db : depletion capacitances C gd = W C * * gd, where C gd is the GD fringing and overlap capacitance per unit gate length (parasitic) g m " 2K I D # g o " $ I D g mb = % g m, where % = & 2 2' p (V BS Clif Fonstad, 10/27/09 Lecture 13 Slide 25
26 LEC for MOSFETs in saturation when v bs = 0: A very common situation in many circuits is that there is no signal applied between on the base, i.e. v bs = 0 (even though it may be biased relative to the source, V BS 0). In this case the MOSFET LEC simplifies significantly: The elements that remain retain their original dependences: C gs " #q G #v GS Q i g = 2 3 W LC * ox C db : depletion capacitance C gd g d v gs v C gs g m v ds gs g o C db s,b s,b g m " 2K I D # g o " $ I D C gd = W C * * gd, where C gd is the GD fringing and overlap capacitance per unit gate length (parasitic) Clif Fonstad, 10/27/09 Lecture 13 Slide 26 i d
27 LEC for Subthreshold MOSFETs, v BS = 0: Our large signal model for MOSFETs operated in the subthreshold FAR (v DS >> kt/q) and v BS = 0, is: D i D G i G (= 0) S,B i D (v GS, v DS ) i G,s"t (v GS,v DS,v BS ) = 0 { i D,s"t (v GS,v DS ) # I S,s"t ( 1" $v DS )e v GS "V To } nv t Like a MOSFET in saturation with v bs = 0, the LEC has only two elements, g m and g o, but now g m is quite different: g m " #i D q = #v GS nkt I S,s$t ( 1$ %V DS )e q ( V GS $V to ) nkt = qi D nkt Q g o " #i D #v DS Q = % I S,s$t e q ( V GS $V to) nkt & % I D ' or & I * D ), ( V A Clif Fonstad, 10/27/09 Lecture 13 Slide 27
28 LEC for Subthreshold MOSFETs, v BS = 0, cont.: The LEC for MOSFETs in subthreshold FAR (v DS >> kt/q) and v BS = 0, is: i g g d v gs v g m v gs g ds o s,b s,b g m = q I D nkt The charge store q DB is the same as q DB in a MOSFETs operated in strong inversion, but g G is not. g G is the gate capacitance in depletion (V FB < v GB < V T ), so it is smaller in subthreshold. g o " # I D Clif Fonstad, 10/27/09 Lecture 13 Slide 28 G qg i d D S,B id qdb
29 LEC for Subthreshold MOSFETs, v BS = 0, cont.: Adding the linear capacitors corresponding to the charge stores we have: C gs " #q G #v GS Q i g C gd g d v gs v C g m v ds gs gs g o C db s,b s,b $ = W L C ox C gd = W C * * gd, where C gd 1 2C $ 2 ox ( V GS %V FB ) & Si qn A is the GD fringing and overlap i d * See Lecture 9, Slides 7 and 8, for q G and the derivation of C gs. C db : depletion capacitance g m = q I D nkt g o " # I D Notice that as before, C gd is zero in our ideal model. It a parasitic that cannot be avoided and must be included because it limits device and circuit performance. Clif Fonstad, 10/27/09 Lecture 13 Slide 29
30 Comparing the low frequency LECs: All of our circuit design will be done for operation at "low" frequencies, that is where the charge store capacitances play a negligible role. Thus it is interesting to compare our three transistor LECs when this is true. They all have the same topology, but differ importantly in g i and g m : i in in out v in g i g m v in g o v out common common Bias dependences: i out BJT ST MOS SI MOS g i : q I C " F kt 0 0 g m : q I C kt qi D n kt 2KI D # g o : $ I C $ I D $ I D ST = subthreshold SI = strong inversion * We will say more about the significance of these Clif Fonstad, 10/27/09 differences when we study amplifier design. Lecture 13 Slide 30
31 The importance of the bias current: A very important observation is that all of the elements in the three LECs we compared depend on the bias level of the output current, I C, in the case of a BJT, or I D, in the case of a MOSFET: Bias dependences: BJT ST MOS SI MOS g i : q I C " F kt 0 0 g m : q I C kt q I D n kt 2KI D # g o : $ I C $ I D $ I D ST = subthreshold SI = strong inversion The bias circuitry is a key part of any linear amplifier. The designer must establish a stable bias point for all the transistors in the amplifier to insure that the gain remains constant and stable. We will study amplifier design and practice beginning with Lecture 17. Clif Fonstad, 10/27/09 Lecture 13 Slide 31
32 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Summary Reminder Exam Two In ~ 1 wk., Thursday, Nov. 5, 7:309:30 p.m. SubThreshold Refs Lecture 12 slides; Subthreshold writeup Notation Total = Bias Signal i A (t) = I A v AB (t) = V AB i a (t) v ab (t) Large signal model Design and analysis of bias conditions Linear equivalent circuits Signal portion design/analysis Small signal models; linear equivalent circuits Everything depends on the bias point The value of each element in an LEC depends on the bias point (often the bias current). Concentrate for now on low frequency LECs Full spectrum LECs with capacitors will only be used to find the upper bound on the low frequency range of operation. We won't see them again until Lecture 23. Clif Fonstad, 10/27/09 Lecture 13 Slide 32
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