CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well

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1 Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Outline Announcements PS #9 - Will be due next week Friday; no recitation tomorrow. Postings - CMOS scaling (multiple items) Exam Two - Tonight, Nov. 5, 7:30-9:30 pm Review - CMOS gate delay and power Lecture 15 results: Gate Delay = 1 n / µ n ( - V T ) P max C L /GD = K n ( - V T ) /4 Velocity Saturation CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well The Road Map; the Future Size and performance evolution with time How long can it go on? Clif Fonstad, 11/5/09 Lecture 16 - Slide 1

2 CMOS: transfer characteristic Complete characteristic w.o. Early effect: V OUT + + K n v IN K p V Tp V Tn v OUT ( /-V Tp ) / ( /-V Tn ) -V Tp V Tn / ( + V Tp ) V IN NOTE: We design CMOS inverters to have K n = K p and V Tn = -V Tp to obtain the optimum symmetrical characteristic. Clif Fonstad, 11/5/09 Lecture 16 - Slide

3 CMOS: transfer characteristic calculation, cont. v OUT We found from an LEC analysis that the slope in Region III is not infinite, but is instead: A v " v out v in = #v OUT #v IN Q = /, / ( ) [ ] [ ] = $ K n [% n + % p ] I Dn = $ g + g mn mp g on + g op / -V Tp v OUT V Tn A v / ( - V Tp ) v IN Quick apprimation: An easy way to sketch the transfer characteristic of a CMOS gate is to simply draw the three straight line portions in Regions I, III, and V: / A v Clif Fonstad, 11/5/09 / v IN Lecture 16 - Slide 3

4 CMOS: switching speed; minimum cycle time The load capacitance: C L Assume to be linear Is proportional to MOSFET gate area In channel: µ e = µ h so to have K n = K p we must have W p /L p = W n /L n Typically L n = L p = and W n = W min, so we also have W p = W min C L " n[ W n L n + W p L p ]C * = n[ W min + W min ]C * * = 3nW min C Charging cycle: v IN : HI to LO; Q n off, Q p on; v OUT : LO to HI Assume charged by constant i D,sat [ ] = K n i Ch arg e = "i Dp # K p " V Tp q Ch arg e = C L [ ] "V Tn Q p $ Ch arg e = q Ch arg e i Ch arg e = = C L [ ] K n "V Tn 6nW min C * W min * µ e C = 6n [ ] µ e [ "V Tn ] "V Tn + + v IN Q n v OUT Clif Fonstad, 11/5/09 Lecture 16 - Slide 4 C L

5 CMOS: switching speed; minimum cycle time, cont. Discharging cycle: v IN : LO to HI; Q n on, Q p off; v OUT : HI to LO Assume discharged by constant i D,sat i Disch arg e = i Dn " K n V # Tn q Disch arg e = C L $ Disch arg e = q Disch arg e i Disch arg e = = [ ] C L K n #V Tn 6nW min C * W min * µ e C [ ] = 6n [ ] µ e [ #V Tn ] #V Tn Q p + + v IN Q n v OUT C L Minimum cycle time: v IN : LO to HI to LO; v OUT : HI to LO to HI " Min.Cycle = " Ch arg e + " Disch arg e = 1n µ e #V Tn [ ] Clif Fonstad, 11/5/09 Lecture 16 - Slide 5

6 CMOS: switching speed; minimum cycle time, cont. Discharging and Charging times: What do the expressions tell us? We have This can be written as: " Min Cycle = 1nL min µ e [ #V Tn ] " Min Cycle = 1n #V Tn ( ) $ µ e ( #V Tn ) The last term is the channel transit time: ( ) = µ e "V Tn µ e # Ch = s e,ch = $ Ch Transit Thus the gate delay is a multiple of the channel transit time: " Min Cycle = 1n ( #V Tn ) " Channel Transit = n' " Channel Transit Clif Fonstad, 11/5/09 Lecture 16 - Slide 6

7 CMOS: power dissipation - total and per unit area Average power dissipation Only dynamic for now P dyn,ave = E Dissipated per cycle f = C L = 3nW min C * f Power at maximum data rate Maximum f will be 1/τ Gate Delay Min. P fmax = 3nW L C * min min = 3nW min C * " Min.Cycle = 1 W min µ e C * [ $V Tn ] 4 [ ] # µ V $V e DD Tn 1n Power density at maximum data rate Assume that the area per inverter is proportional to W min PD fmax = P dyn@fmax InverterArea " P dyn@f max = µ ec * #V Tn W min [ ] Clif Fonstad, 11/5/09 Lecture 16 - Slide 7

8 CMOS: design for high speed Maximum data rate Proportional to 1/τ Min Cycle " Min.Cycle = " Ch arg e + " Disch arg e = 1n µ e #V Tn [ ] Implies we should reduce and increase. Note: As we reduce we must also reduce t, but t doesn't enter directly in f max so it doesn't impact us here Power density at maximum data rate Assume that the area per inverter is proportional to W min PD fmax [ ] " P dyn@f max = µ e# $V Tn W min t Shows us that PD increases very quickly as we reduce unless we also reduce (which will also reduce f max ). Note: Now t does appear in the expression, so the rate of increase with decreasing is even greater because t must be reduced along with L to stay in the gradual channel regime. How do we make f max larger without melting the silicon? Clif Fonstad, 11/5/09 By following CMOS scaling rules, the topic of today's lecture. Lecture 16 - Slide 8

9 CMOS: velocity saturation Sanity check before looking at device scaling CMOS gate lengths are now under 0.1 µm (100 nm). The electric field in the channel can be very high: E y 10 4 V/cm when v DS 0.1 V. Model A Electrons: Holes: Clearly the velocity of the electrons and holes in the channel will be saturated at even low values of v DS! What does this mean for the device and inverter characteristics? Clif Fonstad, 11/5/09 Lecture 16 - Slide 10

10 MOS: Output family with velocity saturation i D E crit L % 0 for v GS < V T, 0 < v ' DS * i D (v GS,v DS,v BS ) " & W s sat C [ v GS #V T (v BS )] for V T < v GS, $ crit L < v DS ' W L µ * e C [ v GS #V T (v BS )]v DS for V T < v GS, 0 < v DS < $ crit L ( ' This simple model for the output characteristics of a very short channel MOSFET (plotted above) provides us an easy way to understand the impact of velocity saturation on MOSFET and CMOS inverter performance. v DS Cutoff Saturation Linear Clif Fonstad, 11/5/09 Lecture 16 - Slide 11

11 CMOS: Gate delay and f max with velocity saturation Charge/discharge cycle and gate delay: The charge and discharge currents, charges, and times are now: * i Disch arg e = i Ch arg e = W min s sat C ( ) "V Tn q Disch arg e = q Ch arg e = C L = 3W min C * # Disch arg e = # Ch arg e = q Disch arg e i Disch arg e = 3W min C * * W min s sat C "V Tn ( ) = 3n ( ) s sat "V Tn CMOS minimum cycle time and power density at f max : " Min.Cycle = " Ch arg e + " Disch arg e = 6n s sat #V Tn [ ] Note: " ChanTransit = L s sat " Min.Cycle # [ ] = n'" ChanTransit s sat $V Tn Lessons: We still benefit from reducing L, but not as quickly. Channel transit time, /s sat, is still critical. Clif Fonstad, 11/5/09 Lecture 16 - Slide 1

12 CMOS: Power and power density with velocity saturation Average power dissipation All dynamic P ave = E Dissipated per cycle f = C L = 3nW min C * f Power at maximum data rate Maximum f will be 1/τ Gate Delay Min. P fmax = 3nW L C * min min = 3nW min C * " Min.Cycle = 1 W mins sat C * [ $V Tn ] # s sat[ $V Tn ] 6n Power density at maximum data rate Assume that the area per inverter is proportional to W min PD fmax = [ ] P dyn@fmax InverterArea " P dyn@f max = s sat C * #V Tn W min Lesson: Again benefit from reducing L, but again not as quickly. Clif Fonstad, 11/5/09 Lecture 16 - Slide 13

13 CMOS: Collected results Maximum data rate: No velocity saturation: With velocity saturation: " Min.Cycle # " Min.Cycle # [ ] µ e $V Tn [ ] s sat $V Tn Power density at maximum data rate: No velocity saturation: PD fmax With velocity saturation: PD fmax [ ] = µ e " #V Tn t = s sat " [ #V Tn ] t Smaller is faster Smaller also dissipates more power per unit area Clif Fonstad, 11/5/09 Lecture 16 - Slide 14

14 Scaling Rules - making CMOS faster without melting Si General idea: Reduce dimensions by factor 1/s: s > 1 Evaluate impact on speed, power, power density Assume no velocity saturation for now Scaling dimensions alone: " s W " W s t " t s N A " sn A This yields and thus PD fmax C * = " : t " # C * * # sc [ ] : " % " s µ e $V Tn P dyn = 3nW min C * [ ] f : K = W L µ ec * : K # sk P dyn % sp dyn = µ e & $V Tn : PD fmax % s 3 PD fmax t Clif Fonstad, 11/5/09 Scaling dimensions alone can yield melted silicon!! Lecture 16 - Slide 15

15 Scaling Rules, cont. - constant E-field scaling Observation: Reducing dimensions alone won't work. Reduce voltage in concert (constant E-field scaling) Scaling dimensions and voltages by 1/s: " s W " W s t " t s N A " sn A We still have but now we find PD fmax " s V BS " V BS s V T " V T s C * * " sc " # µ e $V Tn P dyn = 3nW min C * K " sk [ ] : " % " s [ ] f : P dyn % P dyn s = µ e & $V Tn : PD fmax % PD fmax t When we scale dimension and voltage we get higher speed and lower power, while holding the power density unchanged. Clif Fonstad, 11/5/09 Lecture 16 - Slide 16

16 Scaling Rules, cont. - constant E-field scaling Threshold voltage: We've said V T scales, but this merits some discussion*: Thus: [ ] V T (v BS ) " V FB + # p$si + t % % Si qn A # p$si + v BS Small because with n + -poly Si Dominated by v BS if gate, φ m - φ p and V FB - φ p v BS >> φ p V T (v BS ) " t # # Si qn A v BS $ t s # # Si qsn A v BS s $ V T s Subthreshold leakage and static power: Including V BS, I Doff is: It works. I D,off " W L µ e V t # Si qn A $% p + V BS [ ] { e $V T } nv t " W L µ # e V Si qn A { t e $V T } nv t V BS Scaling all the factors, we find that I Doff and P static scale poorly! * $ + &,% I D,off " si D,off e 1# 1' ) V T s( -. / nv t * $ + &,% P Static = I D,off " P Static e 1# 1' ) V T s( -. / nv t Clif Fonstad, 11/5/09 * We're talking n-channel here, but similar results Lecture 16 - Slide 17 are found for the p-channel MOSFETs.

17 Scaling Rules, cont. - static power scales badly, but... Static power density's scaling is even worse: PD static = I V D,off DD " si e ( s#1 )V T sn V t D,off s " s ( e s#1 )V T sn V t PD W min W min s static A typical V T /nv t is ~10. If s =, the exponential factor is ~ e 3, or about 0! in a chip Bottom Line: Static power can no longer be neglected. Figure source: Intel Web Site Clif Fonstad, 11/5/09 Lecture 16 - Slide 18 Reprinted with permission of Intel Corporation.

18 Scaling Rules, cont. - What about velocity saturation? Do the same constant E-field scaling by 1/s: " s W " W s t " t s N A " sn A " s V BS " V BS s V T " V T s so C * * " sc K " sk Examining our expressions when velocity saturation is important we find: PD fmax " # [ ] : " % " s s sat $V Tn P dyn = 3nW min C * f : P dyn % P dyn s = s sat & [ $V Tn ] : PD fmax % PD fmax t Amazingly, there is no difference in the scaling behavior of the gate delay, average power, or power density in this case! Clif Fonstad, 11/5/09 Note: Velocity saturation is not a factor in I D,off. Lecture 16 - Slide 19

19 An historical scaling example - Inside Intel Parameter Pentium Scaling factor, s 1 3 (µm) W n (µm) t (nm) (V) V T (V) Fan out K (µa/v ) GD (ps) f max (MHz) P ave /gate (mw) Density 0W/cm max.) 0 880,000 Clif Fonstad, 11/5/09 Lecture 16 - Slide 0 Sources: Prof. Jesus del Alamo and Intel

20 An second look inside Intel - a slightly different perspective Parameter 486 Pentium generations Scaling factor, s (µm) SRAM cell area (µm ) Die size (mm ) f mzx (MHz) t (nm) Metal layers Planarization SOG CMP CMP CMP Poly type n n,p n,p n,p Transistors CMOS BiCMOS BiCMOS BiCMOS Source: Dr. Leon D. Yau, Intel, 10/8/96 Clif Fonstad, 11/5/09 Lecture 16 - Slide 1

21 Moore's Law - Everything* doubles every years. Figure source: Intel Web Site * Density, speed, performance, transistors per chip, transistors shipped, transistors per cent, revenues, etc. First stated in Clif Fonstad, 11/5/ as every year; revised to every years in Lecture 16 - Slide Reprinted with permission of Intel Corporation.

22 Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Summary CMOS gate delay and power Three key performance metrics: (We want to make them all smaller) Gate Delay = 1 n ( - V T ) / µ e P max C L /GD = (W n / ) µ e C * ( - V T ) /4 PD dyn,max P max /W n = µ e ε ( - V T ) /4 t CMOS scaling rules Summary of rules: Constant E-field - scale all dimensions and all voltages by 1/s Scaling as: /s Results in: K s K w w/s C * s C * t t /s τ τ/s N A sn A P dyn P dyn /s V T,V BS, V T /s,v BS /s, /s PD dyn PD dyn The Roadmap; what's next? Stay tuned: 3-D; new semiconductors; performance over size Clif Fonstad, 11/5/09 Lecture 16 - Slide 4

23 MIT OpenCourseWare Microelectronic Devices and Circuits Fall 009 For information about citing these materials or our Terms of Use, visit:

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