Electronic Devices and Circuits Lecture 14 - Linear Equivalent Circuits - Outline Announcements

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1 6.012 Electronic Devices and Circuits Lecture 14 Linear Equivalent Circuits Outline Announcements Handout Lecture Outline and Summary Review Adding refinements to large signal models Charge stores: depletion regions, excess carriers, gate charge Activelength modulation: the Early effect Extrinsic parasitics: Lead resistances, capacitances, and inductances Small signal models What are they good for? Linear equivalent circuits pn diodes: JTs: MOSFETs: linearizing the exponential diode incorporating the charge stores linearizing the EersMoll model incorporating the charge stores adding the Early effect and possile parasitics linearizing the GradualChannel model incorporating the charge stores adding the Early effect and possile parasitics Clif Fonstad, 10/03 Lecture 14 Slide 1

2 Circuit symols: C C E JT: MOSFET: D E E C npn pnp pnp as frequently oriented in circuits D S S G G G G S Linear schematics nchannel S Digital schematics D Linear schematics D Digital schematics pchannel (usual circuit orientation Clif Fonstad, 10/03 Lecture 14 Slide 2

3 Output Characteristics JT: npn ic Saturation Forward Active Region ic F i i C F (1 lv CE i 0.2 V Cutoff vce MOSFET: nchannel id Linear or Triode Saturation (FAR i D K [v GS V T (v S ]2/2a i D K[v GS V T (v S v DS /2]v DS i D K[v GS V T (v S ] 2 [1 lv DS ]/2 Cutoff vds Clif Fonstad, 10/03 Lecture 14 Slide 3

4 Creating a linear equivalent circuit, LEC: Suppose we have a device with three terminals, X, Y, and Z, and that we have expressions for the currents into terminals X and Y in terms of the voltages v XZ and v YZ : i X,v YZ and i Y,v YZ Suppose we also have expressions for the charge stores associated with terminals X and Y: q X,v YZ and q Y,v YZ We egin with the static model for the terminal characteristics, and linearize them aout an ias point, Q, defined as a specific set of v XZ and v YZ that we write, usinur notation, as V XZ and V YZ For example, for the current into terminal X we have: i X,v YZ = i X (V XZ,V YZ i X V XZ i X (v YZ V YZ higher order terms v XZ v Q YZ Q For sufficiently small V XZ and (v YZ V YZ, we have: i X,v YZ ª i X (V XZ,V YZ i X v XZ Q Clif Fonstad, 10/03 continued on the next page Lecture 14 Slide 4 X q X, v XY q Y (v YZ, v YX i X, v YZ i Y, v YZ V XZ i X v YZ Q Z (v YZ V YZ Y

5 Creating a linear equivalent circuit, LEC, cont.: Usinur notation, we recognize that: I X i X (V XZ,V YZ, i x [ i X I X ], v xz [ v XZ V XZ ], v yz v YZ V YZ We identify the partial derivatives as conductances, and name them as: i X i g X i g r Applying these to our earlier result we have, first: and finally: v XZ Q v YZ Q i X,v YZ ª I X i X v xz i X v yz v XZ v Q YZ Q i x (v xz,v yz ª g i v xz g r v yz Doing the same for i Y, we arrive at i y (v xz,v yz ª g f v xz v yz [ ] where: g f i Y v XZ Q i Y v YZ Q continued on the next page Clif Fonstad, 10/03 Lecture 14 Slide 5

6 Creating a linear equivalent circuit, LEC, cont.: A circuit showing relating the incremental currents and voltages is shown elow: x v xz z g i g r v yz g f v xz z Next, to handle high frequency signals, we linearize the charge stores' dependencies on voltage. Their LECs, which are linear capacitors: q X q C Y q Ê xz C X yz C xy = q ˆ Y v XZ v Q YZ v Á Q XY v Q Ë YX Q Adding these to the model gives us: x v xz z g i C xz Clif Fonstad, 10/03 Lecture 14 Slide 6 C xy y v yz v g r v yz C yz yz g f v xz z y

7 Linear equivalent circuit (LEC for the pn junction diode: We egin with the static model for the terminal characteristics: i D (v A = I S e qv A kt 1 L inearizing i D aout V A, which we will denote y Q (for quiescent ias point: and we use our notation to write: I D = i D (V A, i d = [ i D I D ], v a = v A V A ending up with i D (v A ª i D (V A i D [ ] v A Q [ v A V A ] We define the equivalent incremental conductance of the diode,g d, as: g d i D = q v A kt I S eqv A / kt ª Q i d = g d v a [ ] The corresponding LEC is shown at right: Clif Fonstad, 10/03 Lecture 14 Slide 7 q I D kt g d ª q I D kt IS A id id a g d va va

8 LEC for the pn junction diode, cont.: At high frequencies we must include the charge store, q A, and linearize its two components: A q A = q DP q QNR,pside C d = C dp C df Depletion layer charge store, q DP, and its linear equivalent capacitance, C dp : q DP (v A = AqN Ap x p ( v A ª A 2qe Si N Ap ( f v A IS qa C dp (V A q DP v A Q = A qe Si N Ap ( 2 f V A a Diffusion charge store, q QNR,pside, and its linear equivalent capacitance, C df : q QNR,pside (v A = i D[ w p x p ] 2 2D e C df (V A q QNR,pside v A Q = q I D kt [ w p x p ] 2 Clif Fonstad, 10/03 (Note: All of this is for an n p diode Lecture 14 Slide 8 g d C d [ ] 2 = g d t d with t d w x p p 2D e 2D e

9 Linear equivalent circuit for the JT (static: In the forward active region, our static model says: [ ] i (v E,v CE = I S e qv E kt 1 i C (v E,v CE = o [ 1 lv CE ]i (v E,v CE = o I S e qv E kt 1 We egin y l inearizing i C aout Q: [ ] 1 lv CE [ ] i c (v e,v ce = i C v e i C v ce = g m v e v ce v E v Q CE Q We introduced the transconductance, g m, and the output conductance,, defined as: g m i C v E Q i C v CE Q Evaluating these partial derivatives usinur expression for i C, we find: g m = q kt oi S e qv kt E [ 1 lv CE ] ª q I C kt [ ] l ª l I C or ª I C Á = o I S e qv E kt 1 Clif Fonstad, 10/03 Lecture 14 Slide 9 (Continued on next foil. Ê Ë V A ˆ

10 LEC for the JT (static, cont.: Turning next to i, we note it only depens on v E so we have: i (v e = i v E Q v e = g p v e The input conductance, g p, is defined as: g p i v E Q To evaluate g p we do not use our expression for i, ut instead use i = i C / o : (Notice that we do not define g p as qi /kt Representing this as a circuit we have: (Notice that v e has een renamed v p e g p i v E Q g p v p = 1 o i v E Q = g m o = qi C o kt g m v p Clif Fonstad, 10/03 Lecture 14 Slide 10 c e

11 Linear equivalent circuit for the JT (dynamic: To complete the model we next linearize and add the charge stores associated with the two junctions. qc The asecollector junction is reverse iased so the charge associated with it, q C, is the depletion region charge. The correspond ing capacitance is laeled C m. The aseemitter junction is forward iased IS as has the excess charge injected into the ase as well as the aseemitter depletion qe E charge store associated with it. The linear equivalent capacitance is laeled C p. The part of C p due to the excess charge turns out to e q I C w 2 /2D e kt, which can also e written g m t with t = w 2 /2D e Summarizing: C p = g m t E depletion cap., C m : C depletion cap. Adding these C's to our model: e g p v p Clif Fonstad, 10/03 Lecture 14 Slide 11 C p C m i g m v p C Fi c e

12 Linear equivalent circuit for the MOSFET (static: In saturation, our static model is: (We've said a = 1 i G (v GS,v DS,v S = 0 i (v GS,v DS,v S ª 0 i D (v GS,v DS,v S = K 2 v GS V T with K W L m * ec ox [ ( v S ] 2 [ 1 lv DS ] { [ ]} 1/ 2 and V T (v S V F 2f psi 1 2e * Si qn A 2f psi v S C ox Note that ecause i G and i are zero they are already linear, and we can focus on i D. L inearizing i D aout Q we have: i d (v gs,v ds,v s = i D v GS Q v gs i D v DS Q v ds i D v S Q v s = g m v gs v ds g m v s We have introduced the transconductance, g m, output conductance,, and sustrate transconductance, g m : g m i D v GS Q i D v DS Q g m i D v S Q (Continued on next foil. Clif Fonstad, 10/03 Lecture 14 Slide 12

13 LEC for the MOSFET (static, cont.: Evaluating the conductances usinur expression for i D, we find: g m i D v GS Q = K[ V GS V T (V S ][ 1 lv DS ] ª 2K I D i D v DS Q = K 2 V GS V T (V S [ ] 2 l ª l I D or ª I D Ê Á Ë V A ˆ g m i D v S Q Representing this as a circuit we have: = K[ V GS V T (V S ][ 1 lv DS ] V T v S Q g v gs s with h V T v S Q g m v gs = 1 * C ox = h g m = h 2K I D e Si qn A qf p V S d g m v s s v s Clif Fonstad, 10/03 Lecture 14 Slide 13

14 Linear equivalent circuit for the MOSFET (dynamic: To complete the model we next linearize and add the charge stores associated with each pair of terminals. In saturation q G is a function only of v GS and v G, so our model only accounts for C gs and C g. C gd is a parasitic element. We have: C gs = (2/3 WL C * ox C gd : sum of GD fringing and overlap capacitances (all parasitics C s, C g, C d : depletion capacitances Adding these C's to our model: g v gs s C gs G C gd qg g m v gs D S id qd qs d g m v s s Clif Fonstad, 10/03 v s C s C d C g Lecture 14 Slide 14

15 6.012 Electronic Devices and Circuits Lecture 14 Linear Equivalent Circuits Summary Analog circuit design; small signal models Linear amplification and processinf signals Digital circuits are ultimately analog Linear equivalent circuits: it all depends on the ias point pn diodes: g d a C d g d = q I D /kt C d = g d t d C dp (V A Clif Fonstad 10/03 JTs: (in FAR e g m = q I C /kt g p = g m / F = I C /V A [or l I C ] C p = g m t C dp,e (V E C m = C dp,c (V C MOSFETs: C (in saturation g m = K(V GS V T = (2K I D 1/2 g gd d g m = hg m [h = {e Si qn A /2( 2f p V S } 1/2 /C ox* ] v gs C = I D /V A [or l I D ] gs g m v gs g m v s C gs = (2/3 WL C * s ox s C gd : GD fringing and overlap v s C d capacitance, all parasitic C s C g C s, C g, C d : depletion capacitances g p v p Cp C m g m v p c e Lecture 14 Slide 15

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