2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor?
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1 EE 330 Exam 1 Spring 2018 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited. There are 10 questions and 5 problems. The points allocated to each question and each problem are as indicated. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If parameters of semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; n C OX =100 A/v 2 p C OX = n C OX /3,V TNO =0.5V, V TPO = - 0.5V, C OX =2fF/ 2, = 0; if reference to a diode is made, assume the process parameter; J S =10-17 A/ 2. The ratio of Boltzmann s constant to the charge of an electron is k/q= 8.61E-5 V/K. If any other process parameters for MOS devices are needed, use the process parameters associated with the process described on the attachment to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. 1. (2pts) There were two major challenges that needed to be overcome for the industry to replace aluminum interconnects with copper interconnects? Give one of these two challenges. 2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor? 3. (2pts) In the late 1940 s, the bipolar transistor was invented and it replaced an electronic device that had been used for many years. What electronic device did the bipolar transistor replace? 4. (2pts) SiO 2 is often thermally grown to form a gate oxide. But if SiO 2 is placed on top of metal, a different process is used to form the SiO 2 layer. What process is typically used to form SiO 2 on top of metal? 5. (2pts) How many valence band electrons does Silicon have? Page 1 of 8
2 6. (2pts) Static CMOS gates that have pull-up networks comprised of only p- channel devices, pull-down networks comprised of only n-channel devices, and a circuit structure that results in one and only one of these two networks conducting for any Boolean input have 3 very attractive properties. Give two of these three attractive properties. 7. (2pts) What is the distinction between a contact and a via in a semiconductor process? 8. (2pts) The capacitance between the anode and cathode of a reverse-biased pn junction is quite voltage dependent. Describe what happens in this junction that makes this capacitance voltage dependent. 9. (2pts) The parameter I S in the standard diode equation is challenging to measure accurately in our laboratory. What is the reason that it is challenging to measure this term accurately in our laboratory 10. (2pts) Why is the capacitance density of Metal 3 to substrate considerably lower than the capacitance density of Metal 1 to substrate in a semiconductor process? Page 2 of 8
3 Problem 1 (16 pts) Assume a circuit was designed in a 180nm process with a die area of 5mm 2. The circuit was fabricated on 8 wafers. The cost of the wafers coming out of the foundry (after processing) was $2500. Though the foundry usually gives the defect density to customers, for some reason the designer was unable to get the defect density from the foundry because the foundry representative argued that the defect density was proprietary. For this reason, the designer was unable to predict the yield or the cost per good die. The circuit was manufactured anyway and after fabrication, 200,000 chips were tested of which 1050 were defective and all defective die failed because of hard faults. a) What was the defect density in the process? b) What is the cost per good die for this design? Page 3 of 8
4 Problem 2 (16 pts) Consider a Boolean system with three inputs, A, B, and C, and output F defined by the function F = A + B C a) Design a CMOS circuit, at the transistor level, that implements the Boolean system described using only NAND and NOR logic gates. Assume the inputs that are available are A, B, and C. b) Repeat part a) but use compound logic gates instead of NAND and NOR logic. Page 4 of 8
5 Problem 3 (16 pts) Consider the following two circuits. a) For the circuit on the left, determine V OUT b) For the circuit on the right, assume V IN =100sin1000t. Obtain an expression for and plot V OUT for one period of the excitation A D =100µ 2 2K V OUT 1K V OUT 12V 2K D 1 A D1 =100µ 2 D 2 A D2 =200µ 2 2K V IN 1K 25V Page 5 of 8
6 Problem 4 (16 pts) Consider the following circuit. Determine the width W of transistor M 1 so that V OUT =2.5V. 5V 200µA V OUT M 1 W=? L=10µm Page 6 of 8
7 Problem 5 (16 pts) Assume a resistor R 1 has a resistance of 2KΩ at T=250K and a resistor R 2 has a resistance of 1K at T=250K. Assume the TCR of R 1 is constant of value 1000 ppm/ C and the TCR of R 2 is constant of value -500 ppm/ o C. a) What will be the resistance of R 1 at 300K b) If R 1 and R 2 are placed in series to form a 3K resistor, what will be the percent change in resistance if the temperature is increased from 250K to 300K? Page 7 of 8
8 TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth volts SHORT 20.0/0.6 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.6 Ids0 < 2.5 < 2.5 pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa Gamma V^0.5 K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: XL_AMI_C5F FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >15.0 <-15.0 volts PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY2_HR POLY2 MTL1 MTL2 UNITS Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness 144 angstrom PROCESS PARAMETERS MTL3 N\PLY N_WELL UNITS Sheet Resistance ohms/sq Contact Resistance 0.78 ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY2 M1 M2 M3 N_WELL UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 2308 af/um^2 Area (poly) af/um^2 Area (poly2) 53 af/um^2 Area (metal1) af/um^2 Area (metal2) 32 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) 48 af/um Overlap (N+active) 206 af/um Overlap (P+active) 278 af/um Page 8 of 8
2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?
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