2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?
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1 EE 330 Exam 1 Spring 2017 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited. There are 10 questions and 5 problems. The points allocated to each question and each problem are as indicated. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If parameters of semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; µ n C OX =100µA/v 2,µ p C OX =µ n C OX /3,V TNO =0.5V, V TPO = - 0.5V, C OX =2fF/µ 2, λ = 0; if reference to a diode is made, assume the process parameter; J S =10-17 A/µ 2 ; and if reference to a bipolar process is made assume process parameters; J S =10-15 A/µ 2, β=100 and V AF =. The ratio of Boltzmann s constant to the charge of an electron is k/q= 8.61E-5 V/K. If any other process parameters for MOS devices are needed, use the process parameters associated with the process described on the attachment to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. 1. (2pts) What is the difference between n-active and p-active? 2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer? 3. (2pts) Why is a barrier metal included under all copper interconnects? 4. (2pts) Why is the ON voltage of a silicon diode often modeled as a 0.6V voltage source? 5. (2 pts) What is the major reason CMOS replaced NMOS as the technology of choice for building most large digital circuits? Page 1 of 6
2 6. (2pts) What is the major benefit of using shallow trench isolation rather than thermally grown oxide when laterally separating transistors from each other? 7. (2pts) Why is CVD rather than thermal growth used to place SiO 2 on top of a metal layer? 8. (2pts) How many valence-band electrons are there in a Silicon atom? 9. (2pts) What is the major reason the capacitance density of Metal 2 to substrate is considerably less than the capacitance density of Metal 1 to substrate in most semiconductor processes? 10. (2pts) Why are contacts from Metal 1 to Poly usually not allowed on the top of thin gate oxide? Page 2 of 6
3 Problem 1 (16 pts) Consider a Boolean system with three inputs, A, B, and C, and output F defined by the function F = AB + AC. a) Design a CMOS circuit, at the transistor level, that implements the Boolean system described using only NAND logic. Assume the inputs that are available are A, B, and C. b) Repeat part a) but use compound logic gates instead of NAND logic. Page 3 of 6
4 Problem 2 (16 pts) Assume a CMOS inverter designed in the ON 0.5µm CMOS process drives a 1pF load and the supply voltage is 3.5V. If a step change on the input from 0 to 3.5V occurs at time t=0, what is the HL output transition time? Assume V DD =3.5V. Problem 3 (16 pts) A stick diagram along with a layer map are shown below. Draw the equivalent circuit corresponding to this stick diagram. V DD A B Y Poly n-active p-active Metal 1 Layer Map Contact V SS Page 4 of 6
5 Problem 4 (16 pts) An interconnect region is shown where the length of Metal 1, Metal 2, and Poly are all approximately 400µm. The width of Metal 2 and Poly are both 2µm and the width of Metal 1, which lies under Metal 2, is 6µm. On the right side Metal 2 is connected to Poly and on the left an input voltage source drives Metal 1. a) Draw an equivalent electrical circuit of this layout (including values for all components) that includes all relevant parasitic capacitances associated with Metal 1 and Metal 2 and the relevant resistance of Poly. Neglect any resistance associated with the metal layers and any capacitance associated with the Poly. b) If the input is a 2V step applied at time t=0, what should the output voltage be if there are no parasitic resistors or capacitors? c) Give an analytical expression for the actual output voltage if a 2V step is applied at the input. Metal 1 400µ Metal 2 V IN V OUT Poly Problem 5 (16 pts) If the voltage of a forward-biased pn junction is varied between 0.55V and 0.6V, what is the range in the diode current. Assume the junction area of the diode is 200μ 2 and JS=10-15 A/μ 2. Page 5 of 6
6 TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth volts SHORT 20.0/0.6 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.6 Ids0 < 2.5 < 2.5 pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa Gamma V^0.5 K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: XL_AMI_C5F FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >15.0 <-15.0 volts PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY2_HR POLY2 MTL1 MTL2 UNITS Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness 144 angstrom PROCESS PARAMETERS MTL3 N\PLY N_WELL UNITS Sheet Resistance ohms/sq Contact Resistance 0.78 ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY2 M1 M2 M3 N_WELL UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 2308 af/um^2 Area (poly) af/um^2 Area (poly2) 53 af/um^2 Area (metal1) af/um^2 Area (metal2) 32 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) 48 af/um Overlap (N+active) 206 af/um Overlap (P+active) 278 af/um Page 6 of 6
2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor?
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