EE 435. Lecture 38. DAC Design Current Steering DACs Charge Redistribution DACs ADC Design
|
|
- Robyn Brown
- 5 years ago
- Views:
Transcription
1 EE 435 Lecture 38 DAC Design Current Steering DACs Charge edistribution DACs ADC Design
2 eview from last lecture Current Steering DACs X N Binary to Thermometer ndecoder (all ON) S S N- S N V EF F nherently nsensitive to Nonlinearities in Switches and esistors Smaller ON resistance and less phase-shift from clock edges Termed bottom plate switching Thermometer coded
3 eview from last lecture Current Steering DACs T-gate Binary to Thermometer ndecoder (all ON) S S S N N V EF F CELL k β = = CELL CELL + CELL+kF F k Transistor mplementation of Switches f VOUTFS VEF CELL = NF 0.5 < β
4 eview from last lecture Current Steering DACs V EF X N n S S S 3 3 n- S n n F Binary-Weighted esistor Arrays Need for decoder eliminated! DNL may be a major problem NL performance about same as thermometer coded if same unit resistors used Sizing and layout of switches is critical Observe thermometer coding and binary weighted both offer some major advantages and some major limitations
5 eview from last lecture Current Steering DACs V EF n X N S S 3 S 3 4 S 4 5 S 5 6 S 6 7 N S 7 F Binary-Weighted esistor Arrays Actual layout of resistors is very important
6 eview from last lecture Another - DAC b 4 b 4 b 3 b3 b b b b V EF
7 Another - DAC F b 4 b 3 b b V SS
8 Another - DAC F b 4 b 3 b b b 4 b 3 b b V SS
9 Current Steering DAC n Binary to Thermometer Decoder (all ON) d k ON d d N- F OUT =k OUT Switch impedance of little concern
10 Current Steering DAC n- F X N n b n b n- b OUT =k OUT
11 Current Steering DAC X MSB n Binary to Thermometer Thermometer Coded Array X LSB n Binary Coded Array F OUT
12 Current Steering DAC n Binary to Thermometer Decoder (all ON) # k d d d N- F OUT =k OUT V DD
13 Current Steering DAC V DD n Binary to Thermometer Decoder (all ON) # k d d d N- F OUT =k OUT V DD C P
14 Current Steering DAC n Binary to Thermometer Decoder (all ON) # k d d d N- F OUT =k OUT V DD M Cascode Current Source (Mirror) V YY M Differential Amplifier (Analog) M 3 M 4
15 Current Steering DAC V DD V YY M M n Binary to Thermometer Decoder (all ON) # k d d d N- F M 3 M 4 OUT =k OUT V DD V YY M M C P M 3 M 4 C P
16 V DD Current Steering DAC V YY M M C P n Binary to Thermometer Decoder (all ON) # k d d OUT =k d N- OUT F M 3 M 4 C P D T D D D V M M V T T V d V EB V EB
17 Current Steering DAC with Supply ndependent Biasing V DD V EF X X X d0 d0 d d dn dn A N= n B f transistors on top row are all matched, X =V EF / Thermometer coded structure (requires binary to thermometer decoder) A V EF N i0 Provides Differential Output Currents d i
18 Current Steering DAC with Supply ndependent Biasing V DD V EF X X X X d0 d0 d d dn dn V A A N= n B V B X f transistors on top row are all matched, X =V EF / V V d N A A EF i i0 Provides Differential Output Voltages
19 Current Current Steering DAC with Supply ndependent Biasing V DD V EF W W W n- W X X n- X d0 d0 d d dn dn A X B f transistors on top row are binary weighted A V d n EF i ni i0 Provides Differential Output Currents
20 Matching is Critical in all DAC Considered V DD V DD b k b k V EF V EF S cn S cn S S S ck S ck Obtaining adequate matching remains one of the major challenges facing the designer!
21 Dynamic Current Source Matching k EF k C C C C Ck Ck C C C Correct charge is stored on C to make all currents equal to EF Does not require matching of transistors or capacitors equires refreshing to keep charge on C Form of self-calibration Calibrates current sources one at a time Current source unavailable for use while calibrating Can be directly used in DACs (thermometer of binary coded) Often termed Current Copier or Current eplication circuit
22 Dynamic Current Source Matching EXT k EXT k k EF CEXT CEXT C C C C Ck Ck C C C C Extra current source can be added to facilitate background calibration
23 End of Lecture 38
Nyquist-Rate D/A Converters. D/A Converter Basics.
Nyquist-Rate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1
More informationEE 330 Lecture 31. Current Source Biasing Current Sources and Mirrors
EE 330 Lecture 31 urrent Source Biasing urrent Sources and Mirrors eview from Last Lecture Basic mplifier Gain Table DD DD DD DD in B E out in B E out E B BB in E out in B E E out in 2 D Q EE SS E/S /D
More informationEE 505 Lecture 11. Statistical Circuit Modeling. R-string Example Offset Voltages
EE 505 Lecture 11 Statistical Circuit Modeling -string Example Offset oltages eview from previous lecture: Current Steering DAC Statistical Characterization Binary Weighted IL b= 1 1 IGk 1 1 I
More informationPARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
More informationEE 505 Lecture 10. Statistical Circuit Modeling
EE 505 Lecture 10 Statistical Circuit Modeling Amplifier Gain Accuracy eview from previous lecture: - + String DAC Statistical Performance eview from previous lecture: esistors are uncorrelated but identically
More informationEE 435. Lecture 36. Quantization Noise ENOB Absolute and Relative Accuracy DAC Design. The String DAC
EE 435 Lecture 36 Quantization Noise ENOB Absolute and elative Accuracy DAC Design The String DAC . eview from last lecture. Quantization Noise in ADC ecall: If the random variable f is uniformly distributed
More informationEE 505 Lecture 8. Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 8 Clock Jitter Statistical Circuit Modeling Spectral Characterization of Data Converters Distortion Analysis Time Quantization Effects of DACs of ADCs Amplitude Quantization Effects of DACs
More informationEdited By : Engr. Muhammad Muizz bin Mohd Nawawi
Edited By : Engr. Muhammad Muizz bin Mohd Nawawi In an electronic circuit, a combination of high voltage (+5V) and low voltage (0V) is usually used to represent a binary number. For example, a binary number
More informationLecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1
Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationLecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
More informationEXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.3-1 10.3 - EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS TECHNIQUE: Divide the total resolution N into k smaller sub-dacs each with a resolution of N k. Result:
More informationEE100Su08 Lecture #9 (July 16 th 2008)
EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart
More informationEE 435 Lecture 44. Switched-Capacitor Amplifiers Other Integrated Filters
EE 435 Lecture 44 Switched-Capacitor Amplifiers Other Integrated Filters Switched-Capacitor Amplifiers Noninverting Amplifier Inverting Amplifier C A V = C C A V = - C Accurate control of gain is possible
More informationA novel Capacitor Array based Digital to Analog Converter
Chapter 4 A novel Capacitor Array based Digital to Analog Converter We present a novel capacitor array digital to analog converter(dac architecture. This DAC architecture replaces the large MSB (Most Significant
More informationD/A Converters. D/A Examples
D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction
More informationir. Georgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 Eindhoven University of Technology Xilinx
Calibration of Current Steering D/A Converters ir. eorgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 1 Eindhoven University of Technology 2 Xilinx Current-steering
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. References
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution
More informationNyquist-Rate A/D Converters
IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling
More informationEE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 7 Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling . Review from last lecture. MatLab comparison: 512 Samples
More informationAs light level increases, resistance decreases. As temperature increases, resistance decreases. Voltage across capacitor increases with time LDR
LDR As light level increases, resistance decreases thermistor As temperature increases, resistance decreases capacitor Voltage across capacitor increases with time Potential divider basics: R 1 1. Both
More informationChapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory
SRAM Design Chapter Overview Classification Architectures The Core Periphery Reliability Semiconductor Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationEE 505. Lecture 13. String DACs
EE 505 Lecture 13 Strig DACs -Strig DAC V FF S 1 S 2 Simple structure Iheretly mootoe Very low DNL Challeges: S N-2 S N-1 S N S k d k Maagig INL Large umber of devices for large outig thermometer/bubble
More informationEE 330 Lecture 31. Basic Amplifier Analysis High-Gain Amplifiers Current Source Biasing (just introduction)
330 Lecture 31 asic Amplifier Analysis High-Gain Amplifiers urrent Source iasing (just introduction) eview from Last Time ommon mitter onfiguration ommon mitter onsider the following application (this
More informationEE 330. Lecture 35. Parasitic Capacitances in MOS Devices
EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationDigital to Analog Converters I
Advanced Analog Building Blocks 2 Digital to Analog Converters I Albert Comerma (PI) (comerma@physi.uni-heidelberg.de) Course web WiSe 2017 DAC parameters DACs parameters DACs non ideal effects DACs performance
More informationCMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices
EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture
More information8-bit 50ksps ULV SAR ADC
8-bit 50ksps ULV SAR ADC Fredrik Hilding Rosenberg Master of Science in Electronics Submission date: June 2015 Supervisor: Trond Ytterdal, IET Norwegian University of Science and Technology Department
More informationEE 330 Lecture 33. Cascaded Amplifiers High-Gain Amplifiers Current Source Biasing
EE 330 Lecture 33 Cascaded Amplifiers High-Gain Amplifiers Current Source Biasing Review from Last Time Can use these equations only when small signal circuit is EXACTLY like that shown!! Review from Last
More informationEE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor
More informationAnalog and Telecommunication Electronics
Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D2 - DAC taxonomy and errors» Static and dynamic parameters» DAC taxonomy» DAC circuits» Error sources AY 2015-16
More informationEE 505. Lecture 27. ADC Design Pipeline
EE 505 Lecture 7 AD Design Pipeline Review Sampling Noise V n5 R S5 dv REF V n4 R S4 V ns V ns β= + If the ON impedance of the switches is small and it is assumed that = =, it can be shown that Vˆ IN-RMS
More informationCapacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009
Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationEE 505 Lecture 10. Statistical Circuit Modeling
EE 505 Lecture 10 Statistical Circuit Modeling mplifier Gain ccuracy eview from previous lecture: - + eview from previous lecture: String DC Statistical Performance 1 1 k k k ILk j 1 j 1 k 1 OM j1 1 1
More informationEE 505 Lecture 9. Statistical Circuit Modeling
EE 505 Lecture 9 Statistical Circuit Modelig eview from previous lecture: Statistical Aalysis Strategy Will first focus o statistical characterizatio of resistors, the exted to capacitors ad trasistors
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationDigital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II
Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II Administration: o Prayer Electricity and Electronics, Section 20.1, Digital Fundamentals: o Fundamentals:
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationEE141-Fall 2011 Digital Integrated Circuits
EE4-Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 Lecture 3 Spring 2016 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More information! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8 - Khanna
More informationE40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1
E40M Binary Numbers M. Horowitz, J. Plummer, R. Howe 1 Reading Chapter 5 in the reader A&L 5.6 M. Horowitz, J. Plummer, R. Howe 2 Useless Box Lab Project #2 Adding a computer to the Useless Box alows us
More informationSuccessive Approximation ADCs
Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1- Successive Approximation ADC Vishal Saxena -2- Data Converter Architectures Resolution [Bits]
More information[1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. Fig. 1.1
1 (a) Define capacitance..... [1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. S 1 S 2 6.3 V 4.5 μf Fig. 1.1 Switch S 1 is closed and switch S 2 is left
More informationBipolar Junction Transistor (BJT) - Introduction
Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationVI. Transistor amplifiers: Biasing and Small Signal Model
VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly.
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationDAC10* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017
* PRODUCT PAGE QUICK LINKS Last Content Update: 0/3/07 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Data Sheet : 0-Bit Current-Out DAC Data Sheet REFERENCE MATERIALS Solutions
More informationPass-Transistor Logic
-all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
More informationBehavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design
Behavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design PC.SHILPA 1, M.H PRADEEP 2 P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur Asst Professor, Dept. of
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
More informationBEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC FOR USE IN SAR ADC DESIGN
BEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC FOR USE IN SAR ADC DESIGN 1 P C.SHILPA, 2 M.H PRADEEP 1 P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur 2 Asst Professor, Dept.
More informationSemiconductor memories
Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor
More informationECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION
ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationExtremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors
Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors Zhiheng Wei 1a), Keita Yasutomi ) and Shoji Kawahito b) 1 Graduate School of Science and Technology,
More informationSOME USEFUL NETWORK THEOREMS
APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem
More informationMidterm 1 Announcements
Midterm Announcements eiew session: 5-8pm TONIGHT 77 Cory Midterm : :30-pm on Tuesday, July Dwelle 45. Material coered HW-3 Attend only your second lab slot this wee EE40 Summer 005: Lecture 9 Instructor:
More informationChapter 2 Switched-Capacitor Circuits
Chapter 2 Switched-Capacitor Circuits Abstract his chapter introduces SC circuits. A brief description is given for the main building blocks of a SC filter (operational amplifiers, switches, capacitors,
More informationLECTURE 28. Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State
Today LECTURE 28 Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State Time permitting, RC circuits (where we intentionally put in resistance
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationEE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods
EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1
More informationThe influence of parasitic capacitors on SAR ADC characteristics
The influence of parasitic capacitors on SAR ADC characteristics DMITRY NORMANOV, DMITRY OSIPOV National Research Nuclear University MEPHI ASIC Lab 59, Moscow, Kashirskoe shosse, 3 RUSSIA simplere@ya.ru
More informationAP Physics C. Electric Circuits III.C
AP Physics C Electric Circuits III.C III.C.1 Current, Resistance and Power The direction of conventional current Suppose the cross-sectional area of the conductor changes. If a conductor has no current,
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More information4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP)
emp. Indep. Biasing (7/14/00) Page 1 4.5 (A4.3) - EMPERAURE INDEPENDEN BIASING (BANDGAP) INRODUCION Objective he objective of this presentation is: 1.) Introduce the concept of a bandgap reference 2.)
More informationSummary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold T/H circuits T/H combined
More informationIn this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents
In this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents around an electrical circuit. This is a short lecture,
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationSPS Presents: A Cosmic Lunch!
SPS Presents: A Cosmic Lunch! Who: Dr. Brown will be speaking about Evolution of the Elements: from Periodic table to Standard Model and Beyond! When: October 7 th at am Where: CP 79 (by the front office)
More informationEE C245 ME C218 Introduction to MEMS Design
EE C45 ME C8 Introduction to MEMS Design Fall 007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 5: Output t
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationAnalog and Telecommunication Electronics
Politecnico di Torino - ICT School Analog and Telecommunication Electronics D3 - A/D converters» Error taxonomy» ADC parameters» Structures and taxonomy» Mixed converters» Origin of errors 12/05/2011-1
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationCircuits Practice Websheet 18.1
Circuits Practice Websheet 18.1 Multiple Choice Identify the choice that best completes the statement or answers the question. 1. How much power is being dissipated by one of the 10-Ω resistors? a. 24
More informationMicroelectronic Circuit Design 4th Edition Errata - Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationEE 435. Lecture 22. Offset Voltages
EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output
More informationResearch Article Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
Hindawi Publishing Corporation LSI Design olume 1, Article ID 76548, 8 pages doi:1.1155/1/76548 Research Article Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs Yan Zhu, 1
More informationMark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions
Lecture Slides Intro Number Systems Logic Functions EE 0 in Context EE 0 EE 20L Logic Design Fundamentals Logic Design, CAD Tools, Lab tools, Project EE 357 EE 457 Computer Architecture Using the logic
More informationDesigning Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM.
EECS 16 Designing Information Devices and Systems II Fall 017 Miki Lustig and Michel Maharbiz Homework 1 This homework is due September 5, 017, at 11:59M. 1. Fundamental Theorem of Solutions to Differential
More informationCMOS Inverter. Performance Scaling
Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2011
EE C245 ME C218 Introduction to MEMS Design Fall 2011 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture EE C245:
More informationEE 435. Lecture 26. Data Converters. Differential Nonlinearity Spectral Performance
EE 435 Lecture 26 Data Converters Differential Nonlinearity Spectral Performance . Review from last lecture. Integral Nonlinearity (DAC) Nonideal DAC INL often expressed in LSB INL = X k INL= max OUT OF
More informationSample-and-Holds David Johns and Ken Martin University of Toronto
Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters
More informationELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
More informationM. C. Escher: Waterfall. 18/9/2015 [tsl425 1/29]
M. C. Escher: Waterfall 18/9/2015 [tsl425 1/29] Direct Current Circuit Consider a wire with resistance R = ρl/a connected to a battery. Resistor rule: In the direction of I across a resistor with resistance
More informationEE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps
EE 435 ecture 2: Basic Op Amp Design - Single Stage ow Gain Op Amps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op Amp Amplifier Amplifier used in open-loop
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More information