Data Converters. Nyquist-rate D/A Converters. Overview. Introduction I. DAC applications

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1 Data Coverters Overview Nyquist-rate D/ Coverters Pietro dreai Dept. of Electrical ad Iformatio Techology ud Uiversity, Swede Itroductio Type of coverters rchitectures based o resistors rchitectures based o capacitors rchitectures based o curret sources Other architectures Data Coverters Nyquist-rate D/ Coverters DC applicatios Itroductio I Video: HDTV moitors display more tha 1000 lies per frame, i additio to a higher cotrast ratio ad a more detailed color rage To maximize the viewig quality o a state-of-the-art display, a 1-bit 150MSPS coversio rate is ofte ecessary The iput of a DC is a multi-bit digital sigal, while the output is a voltage or a curret capable of drivig a exteral load Wired: DCs for DS ad DS+ must hadle badwidths of 1.1MHz or.mhz with 1-bit resolutio Wireless: GSM/EDGE, WCDM, TE require high coversio rates ad high resolutios whe multiple carriers are used Coversio rates of MSpS ad 1-16 bits of resolutio may be ecessary udio: typically, 16-4 bits to headphoes/speakers, with a coversio rate of 44kSpS Ofte a curret is used to drive a off-chip coaxial cable to yield a voltage across the termiatio Data Coverters Nyquist-rate D/ Coverters 3 Data Coverters Nyquist-rate D/ Coverters 4

2 Itroductio II May DCs use itegrated resistaces or capacitaces to atteuate (or, more seldom, to amplify) the referece careful layout desig (commo-cetroid, dummy compoets, temperature-isesitive, etc) leads to matchig accuracies i the order of % resolutios up to 60-70dB are possible without trimmig of aalog passive compoets, ad without usig digital correctio or digital calibratio Use of aalog CMOS switches low o-resistace, high speed of switchig, miimum side effects Natural i CMOS processes (MOS device is a better switch tha trasistor!) Complemetary MOS or bootstrapped MOS (gate voltage is a shifted-up replica of the sigal to be switched) Cotrol of clock feed-through eeded (MOS chael charge flowig to D/S whe the gate cotrol goes off) Voltage ad curret refereces Voltage ad curret refereces ca be either geerated o-chip, or provided via a exteral pi y error affectig the refereces limits the overall system performace should be costat idepedetly of PVT variatios, load, ad time Static errors are usually irrelevat; dyamic errors are much more importat speed ad liearity are affected The oise spectral desity v v Ref, must be well below the quatizatio floor: v I 6 6f FS FS Ref, ;; or i N Ref, ;; N fs s Data Coverters Nyquist-rate D/ Coverters 5 Data Coverters Nyquist-rate D/ Coverters 6 Referece oise a example Types of coverters The demad o the oise floor of the referece becomes very challegig for resolutios above 14 bits: if I FS =0m, the oise spectrum of the curret referece must be below 0.79/sqrt(Hz), which, across 50Ω, results i a oise voltage desity of 39.5V/sqrt(Hz) (fairly low) s a compariso, the spectral desity of the iput-referred oise of a MOS trasistor is ad eve a sigle trasistor with voltage desity as large as v Χ f < 4kTφ g gm m < 0. mv / v < 7.4V Hz gives rise to a oise The basic compoets used i a DC architecture ormally classify the DC. We distiguish betwee: rchitectures based o resistors rchitectures based o capacitors rchitectures based o curret sources Data Coverters Nyquist-rate D/ Coverters 7 Data Coverters Nyquist-rate D/ Coverters 8

3 Resistor based Resistive divider I Strips of resistive layers with a give specific resistace,. The effective umber of squares, (/W) eff, ad the cotact resistace, R cot, give the total resistace value ( rages from a few Ω/ to kω/ ) θ ς θ ς Resistive (Kelvi) divider, iveted by ord Kelvi i the 18 th cetury W R < θ ς eff R cot :1 matchig (o dummies, resistace of metal layer is eglected) bsolute resistace value oly importat for power ad area cosumptio; relative value (matchig) is what really couts Data Coverters Nyquist-rate D/ Coverters 9 Data Coverters Nyquist-rate D/ Coverters 10 Resistive divider II lterative approach uary selectio 3 equal resistor, R U, geerate 8 discrete aalog voltages: i Vi < Vref i < Oly oe switch o the divider-to-buffer path, but may cotrol lies The resistive divider i (b) shifts the voltages by ½SB (V ref / +1 ) by movig ½ uit resistace from the top to the bottom of the divider. The selectio of a voltage is doe by a tree of switches whose state is cotrolled by a digital iput switches betwee ladder ad buffer RC delay The buffer provides a very high iput impedace, performig a voltage measuremet, ad a very low output impedace for adequate drivig of the DC load The decodig method used to select the divider voltage depeds o a trade-off betwee speed, complexity, ad power cosumptio Data Coverters Nyquist-rate D/ Coverters 11 Data Coverters Nyquist-rate D/ Coverters 1

4 Digital potetiometer Trade-off matrix selectio other embodimet of the resistive ladder topology Same fuctioality as the covetioal potetiometer, except that the wiper termial is cotrolled by a digital sigal, so oly discrete steps are allowed Selectio of the wiper positio cotrolled via a -bit register value Commuicatio ad cotrol of the device ca be supported by a parallel or serial iterface Volatile or o-volatile logic to retai the wiper settig. For volatile logic, the wiper is ormally set at mid-rage at power-up limit to the ladder DC is set by the umber of switches/cotrol lies ( ) required. The matrix approach reduces the complexity to / (<< ); however, two switches i series i the sigal path I this example, =8, the DC is partitioed i 4 MSBs (rows) ad 4 SBs colums) Data Coverters Nyquist-rate D/ Coverters 13 Data Coverters Nyquist-rate D/ Coverters 14 Settlig of the output voltage X-Y selectio with shut resistaces ssume the speed of the buffer is very high the voltage at the iput ad output of the buffer depeds oly o the divider, approximated by a RC time costat (with C cocetrated at the buffer iput). If the output k is selected, the N U N, 1( U, 1( N k, 1 R, k 1 RU k, 1, k 1 R < N R < R N R N k R k R eq o o U o o U R s R s R S i parallel to k R U uits: higher speed, but also higher power cosumptio; for each lie, the equivalet resistace is C < C N C N C i i, B o p, o off p, off where C i is the total capacitace at the buffer iput. C i,b is the iput capacitace of the buffer; N o ad N off are o ad off switches coected to the buffer iput (their umber is costat; i our example, N o =N off =3); ad C p,o C p,off are the associated parasitic capacitaces C i is almost costat, while R eq depeds o the selected tap (R eq is parabolic, maximum at mid-poit) sigal-depedet time costat possible distortio! uit resistor should be small eough Data Coverters Nyquist-rate D/ Coverters 15 R s R s krurs Req ( t < kru RS < kr R Data Coverters Nyquist-rate D/ Coverters 16 U S

5 Settlig of the output voltage I If slew-rate ad badwidth of the buffer matter (ad disregardig RC from divider) assume a iput step 0 ΧV is the maximum step with a liear respose σ ΧV i Settlig of the output voltage II No-liear combiatio of liear ramp ad expoetial ramp Recostructio filter yields the time average of the output waveform average of o-liear error causes distortio If the settlig time is log eough, the itegrated error durig the slewig period (area i figure) is Cotiuity of first t=t slew,( (,( V t < V 0 SR t for t ; t out i slew, t, tslew ( σ out < i 0 Χ i 0,Χ for = slew V t V V V e t t 0( ΧVi Χ V σ < SR σ < 1 οα ft ( tslew <, σ SR α = feedback factor (we assume: buffer = opamp + feedback) ; f T = uit gai frequecy of op-amp 1 ΧVi 1 ΧVi V tslew V tslew SR σ,χ SR Χ <, SR while durig the settlig period it is If the error is a costat If the error is liear i ΧV i ΧV σ costat offset, o major issue gai error, o major issue ΧV i If the error depeds o higher powers of (as here) distortio Quatitative estimate of distortio trasistor-level simulatio required Data Coverters Nyquist-rate D/ Coverters 17 Data Coverters Nyquist-rate D/ Coverters 18 Remarks o liearity If liearity is a importat issue, remember: code-depedet settlig of the output typically causes distortio (however, the output is liear if the error is liearly proportioal to the iput code, which is e.g. the case whe Χ V i the previous example i ;ΧV i this case, the error would be σ ΧV i ) high SFDR demads that the variatio of the settlig time be much smaller tha the hold period a low resistace is eeded at every ode Segmeted resistive DC priciple The use of shutig resistors has geerated a auxiliary /-bit DC evolutio: segmetatio realizes a high-resolutio DC by combiig the operatio of two or more DCs (3+3 bits i DC below: cascade of 3-bit MSB DC + eight 3-bit SB DCs) Data Coverters Nyquist-rate D/ Coverters 19 Data Coverters Nyquist-rate D/ Coverters 0

6 Segmeted DC Oly oe SB DC is eeded, if good buffers are available buffers must have the same offsets, high iput impedace ad low output impedace, ad a iput commo-mode rage of V ref It is also possible to replace buffers with curret sources: there is o curret flowig from SB DC to MSB DC if the equatio o the right is satisfied I ΧVSB < SB R Vref, Vref < MSB SB R, The i th resistace is Effect of mismatch 1 ( 1, ( R < R δ δ i u a ri where δ a is the absolute error, ad δ r,i is the relative error, i.e. mismatch. The voltage at tap k is k 0 Ri Vout k < Vref k < 0..., 1, 1 R ad is of course idepedet of δ a : 0 The error depeds o the accumulatio of mismatches, ad is obviously zero at the two edigs of the strig i k k δ 0 ri, Vout k( < Vref k < 0..., 1, 1, 1 δ 0 ri, Data Coverters Nyquist-rate D/ Coverters 1 Data Coverters Nyquist-rate D/ Coverters Mismatch with liear gradiet straight strig with uity elemets spaced by ΧX ad gradiet i their relative values gives ( Rk < R0 1 k Χ X k < 0..., 1 IN with liear gradiet: straight ad folded lie Recall that IN k < Vout k, Vout k. Curves (a) ad (b) show the IN, 4 for Χ x < 10, ad result i a maximum IN of ±0.8SB If the divider layout is folded aroud the mid-poit, the the mid-poit voltage is correct; for the same value of the gradiet, the maximum IN becomes ±0.SB, curve (c). Careful layouts are geerally required ad the output at the tap k becomes V k < V k ΧX k k 1 out ref, 1 ΧX, 1 parabolic with iitial value 0 ad fial value V ref Data Coverters Nyquist-rate D/ Coverters 3 Data Coverters Nyquist-rate D/ Coverters 4

7 Example Harmoic distortio caused by a liear gradiet:, 5 Cosider a gradiet <.5 10 λ i the resistivity of a straight strig of resistors spaced by ΧX=4λ. The DC is a resistive-strig divider coected betwee 0V ad 1V. The FFT of a iput sequece made of 1 poits gives a oise floor for a 8-bit DC at 1 <, 1.76, 6.0 8, 10log <, 83dBc Q which is eough for detectig spurs higher tha e.g. -65dBc (18dB above the oise floor) with some cofidece V 50dB Simulatios/calculatios k k ΧX k k 1 V ad Vout k( < Vref, 1 ΧX, 1 i ref V k( Χ ( Χ, 1 ΧX, 1( ( V 1 X V X V i i ref out 1 1 ( ( V, Χ X, V ΧX V i i ref d fud ref ( i ΧX 4V If < < V d fud i i i,max ref, (, the i i si ϖt( < 1, cos ϖt( ( < < <,49.9dB Data Coverters Nyquist-rate D/ Coverters 5 Data Coverters Nyquist-rate D/ Coverters 6 Effect of radom mismatch o resistors If the resistor variatios are as high as 10%, but they are ot correlated oise floor is icreased, but small distortio (DN high, but IN low) s we will see later, the fact that the mismatches are ucorrelated does ot mea, i geeral, that there caot be ay IN! Trimmig ad calibratio Mismatch effects are ofte ivestigated with Mote Carlo simulatios Trimmig corrects the mismatches caused by iaccuracies i the fabricatio process Thi-film techologies that realize resistors o top of the passivatio layer of the IC are particularly suitable; resistors are trimmed very accurately with a laser? 67dB Use of fuses or ati-fuses for respectively opeig or closig the itercoectios of a etwork of resistive elemets Coectio with fuses or ati-fuses is doe durig testig (either before or after packagig) ad is permaet Data Coverters Nyquist-rate D/ Coverters 7 Data Coverters Nyquist-rate D/ Coverters 8

8 Calibratio Switches tured o or off at power-o (off-lie or foregroud calibratio) or durig the ormal operatio of the coverter (ideally, without iterferig with it: o-lie or backgroud calibratio) These kids of calibratio are ot permaet ca compesate for slow drift, like agig, or, for backgroud calibratio, eve temperature effects (which is particularly importat) If too may elemets trade-off, correctio at the group level voltage mode R-R resistor ladder DC Reduces the total umber of resistors from to (+1) = 3 The resistace to the left of every ode is R! IN improvemet with 3-poit calibratio of 8-bit DC curret mode virtual groud Data Coverters Nyquist-rate D/ Coverters 9 Data Coverters Nyquist-rate D/ Coverters 30 R-R resistor ladder with buffer Voltage mode It ca be verified (e.g. with Thevei s theorem) that coectig the k th switch to V ref leads to a cotributio voltage mode V out < V ref k The output of the R-R ladder i the voltage mode is the superpositio of terms that are the successive divisios-by- of V ref curret mode V V V V V < b b... b b 4 ref ref ref ref out, 1,, which is the DC coversio of the digital biary iput Data Coverters Nyquist-rate D/ Coverters 31 Data Coverters Nyquist-rate D/ Coverters 3

9 Curret mode imits of R-R resistor ladder The curret-mode circuit performs a successive divisio-by- of the referece curret I ref, provided that the voltage at the output ode is (virtual) groud The superpositio of the currets selected by the switches yields the output curret I I I I I < b b... b b 4 ref ref ref ref out, 1,, The parasitic capacitace of the switched ode remais at the same voltage (aalog groud or virtual groud) idepedetly of the code (desirable: faster switchig, liear) bout the output resistace of the referece source: the load see by the voltage ref. source is code-depedet this may cause harmoic distortio use referece geerators whose output impedace is much lower tha the miimum load bout the R-R algorithm: the iput-output characteristics of the R-R ladder (either voltage or curret mode) is NOT itrisically mootoic (as it was for the resistive ladder) This is because i the R-R ladder a icremet by oe SB switches the coectio i all those arms where the cotrol bits chage value because of radom mismatches, it may happe that a icrease by oe SB switches off a cotributio whose value is higher tha the amout that is switched o worst case is at midpoit Glitches (because of large switched currets) may affect the dyamic respose of the curret-mode R-R (udesirable, of course) Data Coverters Nyquist-rate D/ Coverters 33 Data Coverters Nyquist-rate D/ Coverters 34 Curret mismatches Replacig resistors with MOS Cosider the switchig at mid scale: 1, δ, the mid- If, because of mismatches, the MSB curret is scale trasitio becomes I ref 1, 1 I, ( ref, ( I 1 1 I 1 δ ref Iref ref For medium accuracy, area ca be saved by replacig passive resistors with MOS devices, as i the curret-mode ladder below. Observe that two equal parallel MOS etworks divide the iput curret ito two equal parts regardless of the o-liear respose of the sigle elemet, as log as the two etworks operate at the same (o-liear) poit. The step amplitude is ref 1 ( ΧI I, δ 1 If 1, δ = the step amplitude is egative, ad the trasfer fuctio becomes o-mootoic Data Coverters Nyquist-rate D/ Coverters 35 Data Coverters Nyquist-rate D/ Coverters 36

10 Deglitchig Capacitive divider DC track-ad-hold (T&H) after the DC ca highly improve the DC performace by removig the glitches. However, the liearity of the T&H must be at least 10dB higher tha the DC s, which may be difficult to obtai < C V V 1 out ref C 1 C V < V k out ref Data Coverters Nyquist-rate D/ Coverters 37 Data Coverters Nyquist-rate D/ Coverters 38 Itegrated capacitors Parasitic limitatios Capacitors may be implemeted with parallel plates (poly-oxide-poly, metal-isulator-metal (MIM)), or with vertical plates (see right), which yields deser capacitors i moder fie-lie processes with up to 10 differet metal levels The parasitic capacitaces coected to V ref or groud receive the required charge by low-impedace odes (good) The parasitic capacitaces coected to the output ode chage the output voltage (bad) If, however, the parasitic capacitaces are idepedet of the output voltage, oly a gai error is itroduced (ok) V 1 i i out < Vref 0 i 0 No-liear parasitic capacitaces that chage with the output voltage cause harmoic distortio (bad) C bc C pi, Data Coverters Nyquist-rate D/ Coverters 39 Data Coverters Nyquist-rate D/ Coverters 40

11 N-bit capacitor-divider DC tteuatio capacitor ideally, ifiite impedace atteuator reduces capacitace spread The atteuatio capacitor C reduces the capacitor cout The largest elemet i the two arrays is, 1 C U istead of C The total capacitace drops from CU to, 1( C C C The value of C is foud by cosiderig that C i series with the leftside array must yield C U : yieldig C <, 1 C U C C CU CU < C U, 1 U U U Ufortuately, the value of C is a fractio of C U : obtaiig the desired accuracy requires a great deal of care i the layout; furthermore, C is floatig, ad its bottom-plate parasitic capacitace is i parallel to the left-side array Data Coverters Nyquist-rate D/ Coverters 41 Data Coverters Nyquist-rate D/ Coverters 4 Multiplyig DC (MDC) MDC avoids the demads o large iput dyamic rage for the opamp (ad performs offset cacellatio as well) Offset cacellatio i MDC I Durig the reset phase Ε R, the op-amp is coected as a feedback uity buffer, ad the offset voltage is loaded oto the feedback capacitace ad all other capacitaces V out, 1 i b 0 i C <, C U U Data Coverters Nyquist-rate D/ Coverters 43 Data Coverters Nyquist-rate D/ Coverters 44

12 Offset cacellatio i MDC II Durig the active phase Ε DC, the offset is cacelled from the output However, the feedback factor aroud the opamp is ½ durig the active phase ad 1 durig reset, complicatig the frequecy compesatio of the opamp Flip-aroud MDC 1 The previous MDC has as may as, 1C U. The flip-aroud MDC has oly half as may, by chargig k capacitors to V ref -V off (all others to -V off ) durig Ε R, ad the coectig them i parallel to the other, k capacitors durig Ε DC all caps are tied together ad coected to the output, performig charge sharig. Top-plate parasitics are first discharged (to -V off ) ad the kept to virtual groud, while bottom-plate parasitic caps are drive by voltage sources. basic idea V < V out ref kcu C U GND V ref ε R ε DC Data Coverters Nyquist-rate D/ Coverters 45 Data Coverters Nyquist-rate D/ Coverters 46 remider y capacitor-based DC architecture requires a reset phase to make sure that the capacitor array is iitially discharged The output is ot valid durig reset a T&H is required to sustai the output durig reset Hybrid capacitive-resistive DC Better tha the segmeted resistive DC, sice the capacitors are replacig the troublesome buffers resistace ladder implemets the MSB coversio (3 bits here) while the capacitive flip-aroud DC performs the SB coversio ( bits here) V < V Χ k out MSB MSB SB V MSB VMSB 1 Data Coverters Nyquist-rate D/ Coverters 47 Data Coverters Nyquist-rate D/ Coverters 48

13 Curret-based DC Simplified model of sigle curret cell k currets out of as usual, 1 are steered toward the output ode, obtaiig, ,, 1( I < I b b b b out u Norto Ru I < I ; R < R R R R N u N u o u o kcells biary weighted uary weighted R R k k R Vout < kin < INR ; < R R k 1 k R N N N V out depeds o-liearly o k, i.e. o the sigal distortio! Data Coverters Nyquist-rate D/ Coverters 49 Data Coverters Nyquist-rate D/ Coverters 50 I R ( Distortio, 1 Vout,max < IN R ; Vout,max, om < IN R, 1 1, 1 The edpoit-fit IN measured i SBs is the Vout,max, om V k(, V k( V k 1, 1( ( < <, ; < 0..., 1 Χ < 1 k out out, om out,max IN k k k N Its maximum is at mid-scale, ad is approximately IN max <, To summarize The output resistace of the uity curret source causes secod-order harmoic distortio The use of differetial architectures elimiates (ideally) all eve-order distortio, relaxig the requiremets o the uit curret source load resistace (coaxial cable) is oly eeded for very high speed applicatios; for lower speeds, op-amps ca be used to preset a virtual groud to the DC, agai much relaxig the requiremets o the output impedace of the curret sources IN; SB R = R R < ς < R = Mς 1, u ; if 5, 1 u If we have a full-scale siusoidal iput with amplitude, k p <, the fudametal output harmoic has amplitude INRk p, while the d harmoic has amplitude INR kp 4, resultig i a SDR of R R 4. With the above values, SDR=-7dB u Data Coverters Nyquist-rate D/ Coverters 51 Data Coverters Nyquist-rate D/ Coverters 5

14 Uity curret geerator (BJT ad MOS) Radom mismatch i curret mirrors α W ID < Vgs, Vth ; α < λcox ssume mismatches o β ad V th : Χα ΧV th I1 < I 1 α Vgs V, th I Χα ΧVth < I 1,, α Vgs, V ssume Χβ ad ΧV th are ucorrelated the total error becomes th R r g r out ds m4 ds 4 Χ I Χα 4 Vth < I α V V Χ gs, th ( with Χα α α Vth < ; Χ V th < W W Usig curret sources with high output resistace secures liearity at low frequecies at high frequecies, parasitic (o-liear) capacitaces domiate I geeral, complex schemes reduce the speed of operatio α V th ad are process costats; to halve the error, the device area must icrease 4 times Data Coverters Nyquist-rate D/ Coverters 53 Data Coverters Nyquist-rate D/ Coverters 54 Example scalig of trasistor size et the required ΧI/I (for a give yield) for a 1-bit curret-steerig DC be 0.3%. λc ox is 39λ/V, the uit curret I U is 4.88λ, Vth is mv λ ad β is 3e-3 λ. Plot ΧI/I as a fuctio of the MOS area. Estimate the MOS size for a gate overdrive of 0.4V. W( mi < α W=1.11λ, 4 V th ΧI Vgs, Vth ( β=i U /V ov=61.0λ/v, W/=β/λC ox =1.56 W=4.35λm =.78 λm I Data Coverters Nyquist-rate D/ Coverters 55 Radom mismatch with uary selectio The edpoit-fit error for k selected uit curret sources is where Χ ad ΧI are average errors cacellig the possible gai error I r k k Χ r, j, ΧIr Χ, ΧI k < I k I, kχi out s i radom systematic Explicitly, ad cosiderig oly the radom errors, the gai g at the edpoit is give, with uary curret I u, by Iu Χ <, ΧI 1 r, i I 1 r, i Iu g Iu g Iu The gai-ormalized curret error becomes: k k, ΧI 1 ri, kiu Χ I 1 ri,, k ΧI 1 ri, out, r u, Χ I k <, ki < g i 1 I Data Coverters Nyquist-rate D/ Coverters 56 s j s u 1 ΧI ri,

15 Radom mismatch with uary selectio II The variace is calculated as k, outr, 1 ri, 1 ri, ΧI k Χ I, k ΧI,,, Χ I, k < kχi k Χ I, k kχ I < k, k ΧI out r r r r r Maximum at mid-rage: m k < Χ I k < ΧI, 1, out, r,max r Radom mismatch with uary selectio III The radom mismatch x<χir Iu is of course varyig from cell to cell; with a ormal distributio p x( of x, the probability of havig a error equal to x is (with ρ the variace of x, ad ρ its stadard deviatio): x, 1 p x( < e ρ ρ ο IN 0 eve though the ΧI ri, are ucorrelated! It is usually required that the maximum IN error must be lower tha ½ SB, which results i the followig requiremet o : ΧI r 1 ΧI IN < Χ I < Χ I ; I ;,, 1 r, r r u Iu Data Coverters Nyquist-rate D/ Coverters 57 Data Coverters Nyquist-rate D/ Coverters 58 Radom mismatch with uary selectio IV Matchig i 65m CMOS MOS curret I The ormal distributio results i a yield of 0.99 at.57ρ (i.e., for.57ρ), ad a yield of at 3.3ρ. I order to comply with these yields, we must the have: I I (.57ρ ; ρ Χ ; 0.39,, r u x ; I U =10λ, V od =110mV W=0.135λm, =60m 10 I U =10λ, V od =70mV W=1.35λm, =0.6λm ad I I ( 3.3ρ ; ρ Χ ; 0.30,, r u However, it must be cosidered that this aalysis does ot accout for the effect of systematic mismatch, which ca be eve worse tha the radom mismatch Data Coverters Nyquist-rate D/ Coverters 59 Data Coverters Nyquist-rate D/ Coverters 60

16 Matchig i 65m CMOS MOS curret II Matchig i 65m CMOS MOS curret III I U =10λ, V od =70mV W=1.35λm, =0.6λm 10 I U =10λ, V od = 100mV W=13.5λm, =6λm I U =10λ, V od =110mV W=0.135λm, =60m I U =1λ, V od = -10mV W=0.135λm, =60m Data Coverters Nyquist-rate D/ Coverters 61 Data Coverters Nyquist-rate D/ Coverters 6 Selectio of curret sources Uit curret sources are usually arraged i a two-dimesioal array. The simplest selectio mode is a sequetial uary thermometric selectio by lies ad colums, startig i oe corer of the array. Below we see a 8-bit DC where 70 cells are selected (code ) Gradiet error et us assume that the error is liearly depedet o the cell positio: φ x ad φ y beig the gradiets, ( < 1 φ Χ ( 1 φ Χ ( I i j I i i u u x x y y Maximum error is approx. φ Χ ad m φ yχy, ad periodic x x The above error causes IN Moreover, it is worth poitig out that uary selectio esured mootoicity ad eables flexibility, but requires oe cotrol sigal for each elemet This makes the uary selectio approach upractical for 8-bit or more Data Coverters Nyquist-rate D/ Coverters 63 Data Coverters Nyquist-rate D/ Coverters 64

17 Selectio of curret sources The goal is to radomize the mismatches, keepig the accumulated error low No-radom vs. radom selectio Example: 3-level triagular wave with mismatch betwee compoets 3 No-radom Radom 1 Repetitive error distortio! Radom error white oise! a) ie ad colum shufflig (i commo-cetroid fashio); b) multiple local refereces, each close to the respective sector lower threshold mismatch; c) multiple refereces + radom walk selectio of sectors ad uit cells turs correlated error ito pseudo-radom oise Data Coverters Nyquist-rate D/ Coverters 65 Data Coverters Nyquist-rate D/ Coverters 66 Curret switchig methods Biary-weighted DC, combiig k-1 uit curret sources i parallel (with sigle cotrol sigal for etire parallel coectio) Virtually o decodig logic is required; however, possible omootoicity With a radom error, the maximum DN (at mid-poit, without edpoit-fit) is DNmax < I I 1 I I Χ Χ, Χ Χ ΧI ΧI, 1, 1, 1 r u r u r u Uary-cotrol DC (thermometer, shuffled, radom) Itrisic mootoicity, miimum glitch power, good DN/IN; however, each curret source eeds a idividual cotrol sigal; The maximum DN is, for ay code trasitio DNmax < ΧIr ΧIu Segmetatio with curret switchig Coceptual schematic of a 3-step segmeted curret-steerig DC thermometric thermometric biary Data Coverters Nyquist-rate D/ Coverters 67 Data Coverters Nyquist-rate D/ Coverters 68

18 rea of segmeted DC rea of segmeted DC II The area of a segmeted architecture depeds o the area of the uit curret sources ad the area of the circuitry ecessary to geerate ad distribute the cotrol sigals The maximum allowed DN determies the value of the gate area W of the MOS trasistor used to geerate I U i the biary-weighted SB DC (see previous eq. o max. DN i biary-coded DCs): 4 W = DN Vgs, Vth ( 1 Vth α max Thus, the area of the sigle SB cell is proportioal to be writte as < U u, ad ca with the area of the uit curret cell with uary selectio ( < 0) u The area of the logic circuitry ecessary to geerate ad distribute a sigle thermometric code icreases (roughly) liearly with the umber of MSBs: For a segmetatio <, we obtai i total < < M M DC U U, MSB, extra u d M U, MSB, extra < d M, < u d DC U If < 8 ad <1, the DC area is miimum for < 3 d u M Data Coverters Nyquist-rate D/ Coverters 69 Data Coverters Nyquist-rate D/ Coverters 70 rea of segmeted DC III real-life example Q. Huag et al., 00MS/s 14b 97mW DC i 0.18μm CMOS, ISSCC 004 (ETH Zurich, DTU Demark) O the left, plots of ormalized DC area for 1-bit, 11-bit, ad 10-bit segmeted DCs, versus With a 3-step segmeted curret-steerig DC, the area becomes: d DC < U I M u I M Data Coverters Nyquist-rate D/ Coverters 71 Data Coverters Nyquist-rate D/ Coverters 7

19 Switchig of curret sources Switchig phase geerator Remember: whe geeratig the cotrol phases, ever leave the coectio of a uit curret geerator ope, sice the trasistor would be pushed ito the triode regio, with a log recoverig time both off: problem! ever both off: ok! Data Coverters Nyquist-rate D/ Coverters 73 Data Coverters Nyquist-rate D/ Coverters 74