EE 505. Lecture 28. ADC Design SAR

Size: px

Start display at page:

Download "EE 505. Lecture 28. ADC Design SAR"

Frederick Walton
6 years ago
Views:

1 EE 505 Lecture 28 ADC Desig SAR

2 Review from Last Lecture Elimiatio of Iput S/H C LK X IN S/H Stage 1 r 1 Stage 2 r 2 Stage k r k Stage m r m 1 2 k m Pipelied Assembler (Shift Register Array) X OUT C LK X IN Stage 1 r 1 Stage 2 r 2 Stage k r k Stage m r m 1 2 k m Pipelied Assembler (Shift Register Array) X OUT Advace samplig clock a little so that sample is take at quiet time but ot too much to loose over-rage protectio 2

3 Review from Last Lecture Pipelied Data Coverter Desig Issue 1. ADC offsets, Amp Offsets, Fiite Op Amp Gai, errors, Fiite Gai Errors all cause amplifiers to saturate 2. Correct iterpretatio of α k s is critical Guidelies Strategy 1. Out-rage protectio circuitry will remove this problem ad ca make pipelie robust to these effects if α k s correctly iterpreted a) Use Extra Comparators b) Use sub-radix structures 2. a) Accurately set α k values b) Use aalog or digital calibratio 3. Op Amp Gai causes fiite gai errors ad itroduces oiearity 4. Op amp settlig must ca cause errors 5. Power dissipatio strogly depedet upo GB of Op Amps 6. Choice of FB Amplifier Architecture seriously impacts performace 3. a) Select op amp architecture that has acceptable sigal swig b) Select gai large eough at boudary of rage to miimize oliearity ad gai errors 4. Select GB to meet settlig requiremets (degrade modestly to accout for slewig) 5. Miimize C L, use eergy efficiet op amps, share or shut dow op amp whe ot used,scale power i latter stages, elimiate iput S/H if possible, iterleave at high frequecies 6. Bottom plate samplig, bootatrappig, clock advace to reduce aperature ucertaity,critical GB, parasitic isesitivity eeded, β depedet upo architecture ad phase, compesatio for worst-case β, TG if eeded 3

4 Pipelied Data Coverter Desig Guidelies Issue 7. Samplig operatio iheretly itroduces a sampled-oise due to oise i resistors Strategy 7. Select the capacitor sizes to meet oise requiremets. Cotiuous-time oise ca also be preset but is ofte domiated by sampled oise. Size switches to meet settlig ad oise requiremets. Excessive GB will cause oise degradatio i some applicatios, iclude oise from all stages (ot just first stage). 8. Sigal-depedet trackig errors at iput itroduce liearity degradatio 8. Bootstrapped switches almost always used at iput stage. Must avoid stressig oxide o bootstrapped switches 9. Aperature ucertaity ca cause serious errors 10. Iput S/H major cotributor to oliearity ad power dissipatio 9. Sice latecy usually of little cocer, be sure that a clea clock is used to cotrol all samplig. 10. Elimiate S/H but provide adequate over-rage protectio for this removal. Reduces power dissipatio ad improves liearity! 4

5 Review from Last Lecture Cyclic (Algorithmic) ADCs C LK X IN S/H Stage 1 r 1,r 2,.r m-1 1, 1,... 1 Pipelied Assembler (Shift Register Array) C LK C LK X IN S/H Stage 1 1 r X IN Stage 1 r 1 Pipelied Assembler (Shift Register Array) Pipelied Assembler (Shift Register Array) 5

6 Sample Hold SAR ADC C LK Cotroller Cotroller stores estimates of iput i Successive Approximatio Register (SAR) At ed of successive approximatio process, ADC output is i SAR Elimiates the power-cosumig amplifiers of the pipelied ADC Much slower tha pipelied ADC S/H at the iput is essetial Ca have excellet power performace Widely used structure with reewed attetio i recet years 6

7 Sample Hold C LK Cotroller Ay structure ca be used I basic structure, sigle comparator ca be used Performace etirely determied by S/H,, ad comparator Very simple structure ad relatively fast desig procedure If offset voltage of comparator is fixed, comparator offset will ot itroduce ay oliearity 7

8 Sample Hold C LK Cotroller Ay structure ca be used I basic structure, sigle comparator ca be used Performace etirely determied by S/H,, ad comparator Very simple structure ad relatively fast desig procedure If offset voltage of comparator is fixed, comparator offset will ot itroduce ay oliearity 8

9 C LK Typical Operatio (show for 5 bits) Sample Hold Cotroller T CLK t Requires +1 clock cycles Ca be exteded to large umber of bits (16 or more) Comparator requires large CM rage Speed limited by S/H S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H SOC EOC 9

10 C LK Typical Operatio (show for 5 bits) Sample Hold Cotroller t T CLK S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H SOC EOC Two or more bit periods ca be added to S/H Slows overall operatio proportioally but overhead small for large 10

11 Sample Hold CLK Does ot recover from errors Particularly problematic whe errors occur o earlier bits Over-rage protectio ca be added but at expese of additioal clock periods Cotroller Output t Error o First Coversio Output t T CLK T CLK S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H SOC EOC SOC EOC 11

12 Sample Hold C LK Cotroller Charge Redistributio could be used i SAR ADCs V OUT C 1 C 2 C 3 C C R ST S 1 S 2 S 3 S V RFF Capacitors usually biary weighted With this, typical commo-mode iput required for comparator Stadard S/H also required 12

13 Sample Hold C LK Alterate Charge Redistributio Cotroller V C C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S g 1 g 2 g 3 g -1 d 1 d 2 d 3 d -1 g d φ X Cotroller g = d i i Durig samplig phase, iput is sampled o all capacitors Durig successive approximatio process, capacitors are alterately coected to groud or Voltage o commo ode will coverge to 0 Comparator is always comparig to groud thus reducig commo-mode oliearity errors Note iput sample is ot held idepedetly throughout the etire coversio process Bootstrapped switch is critical durig samplig phase Parasitic capacitaces o V C ode do ot affect fial output (Bottom plate) Major source of power dissipatio is i the charge redistributio process 13

14 Sample Hold C LK Alterate Charge Redistributio Cotroller V C C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S g 1 g 2 g 3 g -1 d 1 d 2 d 3 d -1 g d φ X Cotroller C 2 i i C 1 i Q SAMP 2 CV IN i 1 Q C d V V CV i i REF C C i i i Q C2 divref VC CVC CVREF di 2 CVC 2 1 i 1 i 1 i 1 i REF i C i 1 Q CV d 2 CV 2 14

15 Alterate Charge Redistributio V C SAR ADC C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S g 1 g 2 g 3 g -1 d 1 d 2 d 3 d -1 g d φ X Cotroller i REF i 2 C 2 2 IN i 1 CV d CV CV i 2 V V d V IN REF i C i 1 2 i IN REF i 2 C i 1 V V d V If the SAR output is adjusted so that VREF VREF VC 2 2 It follows that i VREF i V VREF di 2 VIN VREF di i1 i1 REF 15

16 Alterate Charge Redistributio V C SAR ADC C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S g 1 g 2 g 3 g -1 d 1 d 2 d 3 d -1 g d φ X Cotroller Biary Search Process Descriptio 1. After samplig with φ S, evisio closig all g switches ad φ X V C will be Close d 1 It follows that 1 C V V CV CV CV CV REF C i C C i VIN IN i2 i1 C V V CV CV 1 REF C i C C i2 i1 1 solvig obtai VC 2 VREF VIN 1 2 CVREF VC 2 C VIN 2 C thus VC 0 d CVREF VIN 2 C VC 2 C 3. Sice d 1 =0, close g 1 ad ow close d 2. It follows that 1 2 CVREF VINC VCC 2 VC 2 VREF VIN 1 VC 2 VREF VIN thus VC 0 d2 1 V 0 d 0 C V 2 V V 2 C REF IN 1 16

17 Alterate Charge Redistributio V C SAR ADC C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S g 1 g 2 g 3 g -1 d 1 d 2 d 3 d -1 g d φ X Cotroller Biary Search Process Descriptio 4. Sice d 2 =1, leave d 2 closed ad ow close d 3. It follows that V 2 V 2 V V 3 2 C REF REF IN thus VC 0 d Sice d 3 =0, ope d 3 ad ow close d 4. It follows that 4 2 V 2 V 2 V V C REF REF IN thus VC 0 d Sice d 4 =1, keep d 4 closed ad ow close d 5. It follows that V 2 V 2 V 2 V V thus VC 0 d C REF REF REF IN 17

18 Output Alterate Charge Redistributio VC C1 C2 C3 C-1 C 2-1 C 2-2 C 2-3 C 2C C C φs φs φs φs φs φs φs g1 g2 g3 g-1 φx d1 d2 d3 d-1 g d Cotroller VREF VIN t - T CLK S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H SOC EOC 18

19 C-2C Array for Charge Redistributio V C C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S g 1 g 2 g 3 g -1 d 1 d 2 d 3 d -1 g d φ X Cotroller Ca a C-2C array be used for the charge-redistributio? Yes but iteral odes would all eed to settle! Ca a couter be used rather tha a biary search to obtai the SAR code? Yes but coversio time would be log with worst-case requirig 2 periods

20 Iput Rage Iput Rage Iput Rage SAR ADC Cocepts are ofte expressed i sigle-eded structures Fully differetial structures widely used Distictio betwee referece voltages ofte ot clearly stated 1 2 V CM V CM VIN VREF V CM V 2 REF Sigle Eded V V V REF1 IN REF1 VCM 0 Sigle Eded Symmetric 2V V 2V REF 2 IND REF 2 Fully Differetial Is Commo-Mode iput 0 or /2? Is maximum iput, 2 or 4 : Sigle-eded Sigle-eded Differetial Iput +, - Differetial Iput

21 Example of Fully Differetial Implemetatio 23

22 Aother example of Fully Differetial Implemetatio with differet switchig sequece ad differet refereces. 24

Charge Redistributio ADC with reduced charge redistributio eergy Goal: Reduce uecessary switchig iheret i the origial process by first switchig all capacitors to ad the returig to groud if test fails.

23 Charge Redistributio ADC with reduced charge redistributio eergy Goal: Reduce uecessary switchig iheret i the origial process by first switchig all capacitors to ad the returig to groud if test fails. Goal: Oly switch if eeded! Stadard Switchig Samples iput o array coected betwee ad Oly chage state if output must be decreased For 10-bit ADC, reported switchig eergy ad total capacitace reduced by about 81% ad 50%, respectively Reduced Switchig Does ot cosider kt/c oise sice resolutio is small

24 Charge Redistributio ADC with reduced charge redistributio eergy Goal: Oly switch if eeded!

26 Charge Sharig ADC with reduced charge redistributio eergy Goal: Have oly passive switchig

27 Charge Sharig ADC with reduced charge redistributio eergy Goal: Have oly passive switchig

28 Lots of ogoig activity i SAR ADCs

29 Lots of ogoig activity i SAR ADCs

30 Lots of ogoig activity i SAR ADCs

31 Ed of Lecture 28

EE 505. Lecture 29. ADC Design. Oversampled

EE 505. Lecture 29. ADC Design. Oversampled EE 505 Lecture 29 ADC Desig Oversampled Review from Last Lecture SAR ADC V IN Sample Hold C LK V REF DAC DAC Cotroller DAC Cotroller stores estimates of iput i Successive Approximatio Register (SAR) At