NOISE IN SC CIRCUITS. NLCOTD: Gain Booster CMFB. Highlights (i.e. What you will learn today) Review. Course Goals. ECE1371 Advanced Analog Circuits

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1 EE37 Advaced Aalog ircuits Lecture 0 NIE IRUIT Richard chreier richard.schreier@aalog.com Trevor aldwell trevor.caldwell@utoroto.ca ourse Goals Deepe Uderstadig o M aalog circuit desig through a top-dow study o a moder aalog system The lectures will ocus o Delta-igma ADs, but you may do your project o aother aalog system. Develop circuit isight through brie peeks at some ity little circuits The circuit world is illed with may little gems that every competet desiger ought to recogize. EE37 0- Date Lecture Re Homework R Itroductio: MD & MD &T -3, A Matlab MD R Example Desig: Part &T 9., J&M 0 witch-level sim R 3 Example Desig: Part J&M 4, &T B Q-level sim T 4 Pipelie ad AR ADs J&M,3 Pipelie DNL I No Lecture R 5 Advaced &T 4, 6.6, 9.4, B TMD; Proj Readig Week No Lecture R 6 omparator ad Flash AD J&M T 7 ircuits Raz, J&M T 8 Ampliier Desig T 9 Ampliier Desig T 0 Noise i ircuits &T R witchig Regulator Project Presetatios T Matchig & MM-hapig Project Report EE NLTD: Gai Booster MFB Need MFB or Gai Booster e optio is to use stadard T MFB (Lecture 9) Is there a easier way with less circuitry? EFF B4 B3 M3 M M M B M M4 M5 EE M9 M7 M3 B4 B3 B B M0 M8 M6 M4 B Highlights (i.e. What you will lear today). How to aalyze oise i switched-capacitor circuits. igiicace o switch oise vs. TA oise Power eiciet solutio Impact o TA architecture Review Previous aalysis o kt/ oise (igorig TA/opamp oise) Phase : kt/ oise (o each side) Phase : kt/ added to previous oise (o each side) Total Noise (iput reerred): kt/ Dieretially: 4kT/ 3. Desig example or modulator EE EE37 0-6

2 Review Thermal Noise i TAs NR Total oise power: 4kT/ igal power: / NR: /8kT igle-eded Example Noise curret rom each trasistor is Assume /3 I 4kT g m NR (sigle-eded) Total oise power: kt/ (samplig capacitor ) igal power: / (sigal rom - to ) NR: /4kT EE EE Thermal Noise i TAs igle-eded Example Thermal oise i sigle-eded TA Assumig paths match, tail curret source M 5 does ot cotribute oise to output 8kT PD o oise voltage i M (ad M ): 3g m 8kTgm 3 PD o oise voltage i M 3 (ad M 4 ): 3gm Total iput reerred oise rom M -M 4 6kT g m3 6kT eq, 3gm gm 3gm Noise actor depeds o architecture TA with capacitive eedback Aalyze output oise i sigle-stage TA Use capacitive eedback i the ampliicatio / itegratio phase o a switched-capacitor circuit,eq EE EE TA with capacitive eedback Traser uctio o closed loop TA G Hs ( ) s/ eq, where the D Gai ad st -pole requecy are G / Load capacitace depeds o the type o TA or a sigle-stage, it is L + /( + ), while or a two-stage, it is the compesatio capacitor o g o m TA with capacitive eedback Itegrate total oise at output () H( j ) d 0, eq 6kT o G 3gm 4 4kT 3 Miimum output oise or = is Not a uctio o g m sice badwidth is proportioal to g m while PD is iversely proportioal to g m 4kT 3 EE37 0- EE37 0-

3 TA with capacitive eedback Graphically ampled Thermal Noise What happes to oise oce it gets sampled? Total oise power is the same Noise is aliased olded back rom higher requecies to lower requecies PD o the oise icreases sigiicatly Noise is eectively iltered by the equivalet brick wall respose with a cut-o requecy o o / Total oise at is the itegral o the oise withi the brick wall ilter (area is simply o / x / ),eq L, EE EE ampled Thermal Noise o,s out ame total area, but PD is larger rom 0 to / Geq, 4kT out () 4 / / 3 / Low requecy PD s Aliased Noise is icreased by 3dB G eq, EE o ampled Thermal Noise / 3dB is the settlig time o the system, while / is the settlig period or a two-phase clock / ( N ) e 3 db ( N )l PD is icreased by at least ( N )l I N = 0 bits, PD is icreased by 7.6, or 8.8dB This is a iheret disadvatage o sampleddata compared to cotiuous-time systems But oise is reduced by oversamplig ratio ater digital ilterig EE Noise i a Itegrator Usig the parasitic-isesitive itegrator Noise i a Itegrator Phase : amplig Ro Ro Ro Two phases to cosider ) amplig Phase Icludes oise rom both switches ) Itegratig Phase Icludes oise rom both switches ad TA EE Noise PD rom two switches: Ro() 8kTR Time costat o R- ilter: R PD o oise voltage across 8kTR () ( ) EE37 0-8

4 Noise i a Itegrator Phase : amplig Itegrated across etire spectrum, total oise power i is 8kTR kt, sw 4 Idepedet o R (PD is proportioal to R, badwidth is iversely proportioal to R ) Ater samplig, charge is trapped i EE Noise i a Itegrator Phase : Itegratig Two oise sources - switches ad TA Noise PD rom two switches: Ro() 8kTR 6kT Noise PD rom TA: v, eq () 3gm Noise voltage across charges to Ro,eq EE Noise i a Itegrator What is the time-costat? Ro m L Aalysis shows that Z For large R L, assume that / s R g R Resultig time costat (R / g ) EE37 0- Z m L g m L m Noise i a Itegrator Total oise power with both switches ad TA o itegratig phase v, eq () Ro(), op, sw 4 4 6kT 8kTR 3gm 4(R / gm) 4(R / gm) 4kT kt x 3 ( x) ( x) Itroduced extra parameter EE37 0- x R g m Noise i a Itegrator Total oise power o rom both phases, op, sw, sw 4kT kt x kt 3 ( x) ( x) kt 4 /3 x x Lowest possible oise achieved i x kt I this case, What was assumed to be the total oise was actually the least possible oise! EE Noise otributios Percetage oise cotributio rom switches ad TA (assume =.5) Noise Fractio (%) witch TA x=r g m EE37 0-4

5 Noise otributios Whe g m >> /R (x >> ) witch domiates both badwidth ad oise Total oise power is miimized Whe g m << /R (x << ) TA domiates both badwidth ad oise Power-eiciet solutio Miimize g m (ad power) or a give settlig time ad oise kt 4 gm x 3 Miimized or x=0 EE Maximum Noise How much larger ca the oise get? Depeds o (table excludes cascode oise) Architecture Telescopic/ Di.Pair Telescopic/ Di.Pair Folded ascode Folded ascode Relative EFF s EFF, = EFF, / EFF, = EFF, EFF, = EFF, / EFF, = EFF, Maximum Noise (x=0) 3. kt/ kt/ kt/ kt/ EE db eparate Iput apacitors Usig separate iput caps icreases oise Each additioal iput capacitor adds to the total oise eparate caps help reduce sigal depedet disturbaces i the DA reerece voltages I Dieretial vs. igle-eded All previous calculatios assumed sigle-eded operatio For same settlig time, g m, is the same, resultig i the same total power [0dB] Dieretial iput sigal is twice as large [gai 6dB] Dieretial operatio has twice as may caps ad thereore twice as much capacitor oise (assume same size per side ad ) [lose ~.db or =.5, x=0 less or larger ] DA a kt 4 /3 x... a x Net Improvemet: ~4.8dB EE EE Dieretial vs. igle-eded igle-eded Noise kt 4 /3 x, se x Dieretial Noise, di, op, sw, sw 4kT kt x kt 3 ( x) ( x) kt 4 /3 4x x Relative Noise (or =.5, x=0), di 4 /3 4x 4 4 /3 x 3, se EE Noise i a Itegrator What is the total output-reerred oise i a itegrator? Assume a itegrator traser uctio kz Hz ( ) ( k) ( ) z where k ad A I EE

6 Noise i a Itegrator Noise i a Modulator Total output-reerred oise PD How do we id the total iput-reerred oise i a modulator? T() () H() z () ) Fid all thermal oise sources 4kT where ) Fid PDs o the thermal oise sources 3 3) Fid traser uctios rom each oise source to the output kt 4 /3 x ad x 4) Usig the traser uctios, itegrate all PDs rom D to the sigal bad edge /. R ice all oise sources are sampled, white PDs 5) um the oise powers to determie the total output thermal oise x x / 6) Iput oise = output oise (assumig TF is ~ i the sigal bad) To id output-reerred oise or a give R EE /( R) () EE37 T T d Noise i a Modulator Example: = 00MHz, T = 0s, R = 3 NR = 80dB (3-bit resolutio) Iput igal Power = 0.5 (-6dB rom ) Noise Budget: 75% thermal oise Total iput reerred thermal oise: ( 6 NR)/ * 0 (43.4 ) TH EE Noise i a Modulator ) Fid all thermal oise sources i o kt 4 A /3 x A A xa 4kT 3 A A A o 4kT EE i kt 4 B /3 x B B xb B B kt kt ( ) B Noise i a Modulator Noise i a Modulator ) Fid PDs o the thermal oise sources For each o the mea square voltage sources, x x / Hz ( ) Hz ( ) 3) Fid traser uctios rom each oise source z z Hz ( ) Hz ( ) to the output Assume ideal itegrators From output o H A (z) to output z HA( z) HB( z) NTFo ( z) H( z) NTF( z) z Hz ( ) TF( z) ( z )( z ) Hz ( ) Hz ( ) NTF( z) ( z ) Hz ( ) Hz ( ) EE EE ) Fid traser uctios rom each oise source to the output From iput o H A (z) to output NTF z H z H z NTF z i( ) ( ) ( ) ( )

7 Noise i a Modulator 3) Fid traser uctios rom each oise source to the output From iput o H B (z) to output NTFi ( z) H( z) NTF( z) Hz ( ) z ( z ) Hz ( ) Hz ( ) From output o H B (z) to output (equal to traser uctio at iput o summer to output) NTF ( ) ( ) ( ) o z NTF z z EE Noise i a Modulator 3) Fid traser uctios rom each oise source to the output Most sigiicat is NTF i Magitude (db) igal Bad NTF i -40 NTF o NTF i NTF o Normalized Frequecy EE Noise i a Modulator 4) Usig the traser uctios, itegrate all PDs rom D to the sigal bad edge /. R Use MATLAB/Maple to solve the itegrals /( R) i i i / 0 i / N NTF () d 5 si R R /( R) o o o() / 0 o 7 9 / N NTF d si cos si R R R R EE Noise i a Modulator 4) Usig the traser uctios, itegrate all PDs rom D to the sigal bad edge /. R i Ni si / R R N 3 si cos R R R 4 si R o 3 o / (ome simpliicatios ca be made or large R) EE Noise i a Modulator 5) um the oise powers to determie the total output thermal oise Assume x A = x B = 0. ad A = B =.5 TH.9kT kt.9kt 3 3 A R AA 3R B 3R 4 4 kt 8kT 5R 5R 5 5 B B With a R o 3, irst term is most sigiicat (assume A = B = /3) kt kt kt TH A A B EE Noise i a Modulator 6) Iput oise = output oise (assumig TF is ~ i the sigal bad) kt 9. 0 (43.4 ) A => A = 00F TH Assumig other capacitors are smaller tha A, the subsequet terms are isigiicat ad the approximatio is valid I lower oversamplig ratios are used, other terms may become more sigiicat i the calculatio EE37 0-4

8 Noise i a Pipelie AD imilar procedure to modulator, except traser uctios are much easier to compute Diereces Iput reer all oise sources Gai rom each stage to the iput is a scalar Noise rom later stages will be more sigiicat sice typical stage gais are as low as ample-ad-hold adds extra oise which is iput reerred with a gai o Etire oise power is added sice the sigal bad is rom 0 to / (R=) Noise i a Pipelie AD Example I each stage has a gai G, G, G N o i o i3 on Ni i G G G G G G N /H stage oise will add directly to i EE EE NLTD: Gai Booster MFB What You Leared Today. Noise aalysis or switched-capacitor circuits. otributios o both switch oise ad TA oise Fidig a power eiciet solutio igiicace o TA architecture 3. modulator desig example EE EE ome Project Guidelies Geeral: ) orers: Do ot eed to simulate ) Noise aalysis: use calculatios to size the capacitors, but use adece to id TA oise 3) lock Geerator: do t eed to desig ooverlappig clock geerator, but buer the ideal clocks ad take ito accout the buer size or power calculatios (i you have other clock phases ot just ad you should idicate how you would geerate these) 4) Biasig: Ideal voltage source or DD/ ad reerece ladder edges; Ideally oe curret source rom which all currets are derived (at least use oly oe curret source per circuit block) EE ome Project Guidelies Presetatio: 5-0 miutes lides ( title, cotet) Focus o major desig issues ad circuit blocks (what you cosider the most importat desig decisios) Report We should be able to replicate your circuit with the iormatio provided i the report Give trasistor sizes, preerably aotated o igures Try to avoid adece schematics (i you use them, make them more readable without all the uecessary aotatios) EE