EE 505. Lecture 27. ADC Design Pipeline

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1 EE 505 Lecture 7 AD Design Pipeline

2 Review Sampling Noise V n5 R S5 dv REF V n4 R S4 V ns V ns β= + If the ON impedance of the switches is small and it is assumed that = =, it can be shown that Vˆ IN-RMS kt ktr GB 4 4 Too much GB or too large of R SW can increase sampled noise voltage Too small of R SW will not derive any benefit and will increase power, area, and driving problems

3 Sampling Noise apacitors introduce no noise Noise is, however, present in switches that take samples This switch noise causes SNR problems in the amplifier if not correctly managed 3

4 Sampling Noise S S (a) (b) 4

5 Sampling Noise LK S R SW (a) (b) (c) High TRAK HOLD Low T LK 5

6 Sampling Noise LK 6

7 Sampling Noise (t) (kt) LK 7

8 Sampling Noise (t) (kt) LK 8

9 Sampling Noise V n R SW Power spectral density of any resistor, R SW, is given by SVR 4kTR SW This is thermal noise and often termed white noise since the spectral dissipation is uniform for all f 9

10 Sampling Noise V n T(s) Linear Network Theorem If V n (t) is a continuous-time zero-mean noise source with power spectral density S V, then the spectral density of is given by the expression S Ts S V OUT s j V The RMS value of a continuous-time random variable V(T) is defined to be T T V E lim V (t)dt RMS T 0 The RMS value of a random sequence <V(kT)> is defined to be N N ˆV E lim V kt RMS N k ( the operator E is the expected value operator) (these definitions apply to non-random signals as well) 0

11 Sampling Noise V n T(s) Linear Network Theorem If V n (t) is a continuous-time zero-mean noise source with power spectral density S V, then the spectral density of is given by the expression S Ts S V Theorem If V(t) is a continuous-time zero-mean noise voltage with power spectral density S V, then the RMS value of the continuous-time noise is given by RMS OUT f=0 V S df V s j V Note: There are some parts of the hypothesis of this theorem that have not been stated such as stationary of the distribution and no correlation between samples spaced T seconds apart..

12 Sampling Noise V n R SW SVOUT SVR 4kTR SW 4kTR + Rω

13 Sampling Noise SVOUT 4kTR + Rω V n R SW V n RMS Recall: f=0 S V OUT df f y0 y0 dy tan y y V n RMS f=0 S V OUT df 0 4kTR ω R kt df Key Result, ontinuous-time noise at 3

14 Sampling Noise Since noise is independent of V REF, would like to make V REF as large as possible to minimize sizing Scaling to lower supply voltage has a negative impact on capacitor sizing (scaling supply by requires increasing by factor of 4) 4

15 Sampling Noise Example: 4-bit AD =4.6pF 5

16 Sampling Noise Theorem 3 If V(t) is a continuous-time zero-mean noise voltage and <V(kT)> is a sampled version of V(t) sampled at times T, T,. then the RMS value of the continuous-time waveform is the same as that of the sampled version of the waveform. This can be expressed as V RMS Vˆ RMS Note: There are some parts of the hypothesis of this theorem that have not been stated such as stationary of the distribution and no correlation between samples spaced T seconds apart.. 6

17 Sampling Noise. Theorem 4 If V(t) is a continuous-time zero-mean noise source and <V(kT)> is a sampled version of V(t) sampled at times T, T,. then the standard deviation of the random variable V(kT), denoted as satisfies the expression V Vˆ Vˆ RMS RMS ˆV Theorem 5 The RMS value and the standard deviation of the noise voltage that occurs in the basic switched-capacitor sampler is related to the capacitor value by the expression ˆV V RMS RMS Vˆ kt 7

18 Sampling Noise V n R SW V AP V n V n RMS kt Vˆ n RMS kt Key Result, ontinuous-time noise at Key Result, Discrete-time noise at 8

19 Sampling Noise But noise is actually a bit worse than simply kt/ Φ Φ V REF dφ Φ Φ β= + β = A =+ FB dφ V n5 R S5 V n R S V n3 R S3 V ns V n R S V n4 R S4 V ns dv REF 9

20 Sampling Noise V n R S V n3 R S3 V n R S β = RMS Noise Voltage on capacitors and V n RMS kt Vˆ n RMS kt V n RMS kt Vˆ n RMS kt 0

21 Sampling Noise V n5 R S5 dv REF V n4 R S4 V ns V ns β= + + +s R +R 4 5 V =V OUT IN +s R + + +s R + R GB GB +R s GB GB + R GB Vˆ 5 d V REF +s R + + +s R + R ˆ Vˆ +R s +V +R s n 5 n 4 +s R GB +s R +R s +R s 5 n Vˆ n4 5 +s R + + +s R + R GB GB ˆ V =V V V Vˆ OUT IN REF n n d Vˆ n +R s Vˆ +R s 5 n s R + + +s R +R GB GB 4 5 4

22 Sampling Noise V n5 R S5 dv REF V n4 R S4 V ns V ns β= + ˆ V =V V V Vˆ OUT IN REF n n d Vˆ n +R s Vˆ +R s 5 n s R + + +s R +R GB GB If the ON impedance of the switches is small, it can be shown that V ktr GB 4-5RMS 4

23 Sampling Noise V n5 R S5 dv REF V n4 R S4 V ns V ns β= + If the ON impedance of the switches is small and it is assumed that = =, it can be shown that V ktr GB 4-5RMS 4 Vˆ kt ktr GB IN-RMS 4 Vˆ IN-RMS kt ktr GB 4 4 3

24 Sampling Noise V n5 R S5 V ns dv REF V n4 R S4 V ns β= + If the ON impedance of the switches is small and it is assumed that = =, it can be shown that Vˆ IN-RMS If size switches so that R SW kt ktr GB 4 4 f ln n + Vˆ IN-RMS LK kt ST 4

25 Sampling Noise V n5 R S5 V ns dv REF V n4 R S4 V ns β= + If the ON impedance of the switches is small and it is assumed that = =, it can be shown that Vˆ IN-RMS kt ktr GB 4 4 Too much GB or too large of R SW can increase sampled noise voltage Too small of R SW will not derive any benefit and will increase power, area, and driving problems 5

26 V REF dφ V REF dφ Sampling Timing Φ Φ Φ Φ Φ Φ Φ Φ dφ dφ Even numbered stages sampled with φ and odd stages sampled with φ T LK φ φ First Sample SS ST SS ST S3S S3T S4S S4T S5S S5T S6S S6T S7S S7T S8S Second Sample SS ST SS ST S3S S3T S4S S4T S5S S5T S6S Second Sample SS ST SS ST S3S S3T S4S 6

27 Sampling Timing Φ Φ Φ Φ V REF dφ T LK dφ φ φ A φ φ A First Sample AD AD AD3 AD4 AD5 AD6 AD7 AD8 Second Sample AD AD AD3 AD4 AD5 AD6 Second Sample AD AD AD3 AD4 Quiet sampling is important 7

28 Switch Sizing Φ Φ Φ Φ d V REF dφ dφ Sizing switches for constant input onsider any first-order R network Target Settling: to ½ LSB in time T LK / for worst-case transition V REF n ST R SW H V REF t 0.5T LK 8

29 Switch Sizing Target Settling: to ½ LSB in time T LK / for worst-case transition R SW H V REF V REF n ST t t R V e V V REF REF REF n ST 0.5T LK t R e n ST R n ST t ln R SW f n ln LK ST 9

30 Switch Sizing Φ To settle to ½ LSB in time T LK / R GB SW f ln n + H LK ST n + ln ST f β LK Φ Φ V REF dφ dφ Recall minimum GB requirement (which is usually what will be designed for) Eliminating f LK we obtain R SW H βgb Define excess switch sizing factor θ by R SW θ βgb H Φ 30 d

31 Sampling Noise Summary of Flip-around S gain stage β= + A =+ FB Vˆ kt + IN-RMS θ R= 4 βgb Vˆ 4-5RMS Φ Φ V REF dφ dφ Φ Φ d V 4-5RMS θ β +θ ω kt + dω π -β β 4θβ β 4 ω βθ +ω θ+ - + ω=0 -β -β -β Often θ<< even with minimum sized devices and in this case V 4-5RMS is negligible Vˆ IN-RMS kt + 3

32 Sampling Noise Two popular S gain stages Φ Φ Φ Φ d V REF dφ dφ Φ Φ Φ VOUT dφ dφ Φ V REF 3

33 Sampling Noise Basic S gain stage Φ Φ A =- FB Φ VOUT dφ dφ Φ β= + V REF V n R S V n5 R S5 V n V n4 R S4 R S V ns R S3 V n3 dv REF (a) (b) 33

34 Sampling Noise Basic S gain stage Φ Φ Φ VOUT dφ dφ Φ V REF V n R S V n5 R S5 V n V n4 R S4 R S V ns R S3 V n3 dv REF (a) (b) It can be shown that V = V +dv +V +V OUT IN REF n n4 s +R s+ + +R s 4 4 GB 34

35 Sampling Noise Basic S gain stage Φ dφ dφ Φ V REF Φ Φ VOUT V n5 R S5 V n R S V n4 R S4 V n R S R S3 V n3 V ns dv REF (a) (b) V = V +dv +V +V OUT IN REF n n4 s +R s+ + +R s 4 4 GB V θ R= βgb β= + ktθ -β π β +ω +θ -θβ +ω θβ OUTn4RMS 4 ω=0 dω Vˆ IN-RMS kt Vˆ OUT4-RMS θ<< Vˆ IN-RMS kt 35

36 Φ dφ dφ Φ V REF Φ Φ V REF dφ dφ Φ Sampling Noise Φ Two popular S gain stages Φ Φ VOUT V d 4-5RMS A =+ FB Vˆ kt + β= + IN-RMS θ β +θ ω kt +γ dω π -β β 4θβ β 4 ω βθ +ω θ+ - + ω=0 -β -β -β V θ<< A =- FB Vˆ ktθ -β ω=0 Vˆ kt IN-RMS IN-RMS Vˆ 4-5RMS β= + Vˆ OUT4-RMS π β +ω +θ -θβ +ω θβ OUTn4RMS 4 kt + dω θ<< Vˆ IN-RMS kt 36

37 Sampling Noise When is the continuous-time S noise really of concern? Recall GB kt V = n+ R= 4 βgb n + ln ST f β LK Eliminating GB and R= 4 kt n ST n ST + lnf LK 37

38 38 Sampling Noise When is the continuous-time S noise really of concern? MAX n ST ST LK R = kt n + lnf E E E E E+06.9E E E E E E E E+07.5E+08.5E E E E E+05.8E+06.8E+07.8E+08.8E+09.8E E+06.E+07.E+08.E+09.E+0.E E+06 5.E+07 5.E+08 5.E+09 5.E+0 5.E+ 0.3E+04.3E+05.3E+06.3E+07.3E+08.3E+09.3E+0.3E+.3E+ 9.0E+05.0E+06.0E+07.0E+08.0E+09.0E+0.0E+.0E+.0E E E E E E E+0 4.6E+ 4.6E+ 4.6E+3 7.E+06.E+07.E+08.E+09.E+0.E+.E+.E+3.E E E E E E+0 9.8E+ 9.8E+ 9.8E+3 9.8E E E E E+0 4.7E+ 4.7E+ 4.7E+3 4.7E+4 4.7E+5 4 G 00M 0M M 00K 0K K E E E E E+06.9E E E E E E E E+07.5E+08.5E E E E E+05.8E+06.8E+07.8E+08.8E+09.8E E+06.E+07.E+08.E+09.E+0.E E+06 5.E+07 5.E+08 5.E+09 5.E+0 5.E+ 0.3E+04.3E+05.3E+06.3E+07.3E+08.3E+09.3E+0.3E+.3E+ 9.0E+05.0E+06.0E+07.0E+08.0E+09.0E+0.0E+.0E+.0E E E E E E E+0 4.6E+ 4.6E+ 4.6E+3 7.E+06.E+07.E+08.E+09.E+0.E+.E+.E+3.E E E E E E+0 9.8E+ 9.8E+ 9.8E+3 9.8E E E E E+0 4.7E+ 4.7E+ 4.7E+3 4.7E+4 4.7E+5 4 G 00M 0M M 00K 0K K 00 0 lock Speed Resolution R MAX (flk,n)

39 Sampling Noise What about this one? Φ Φ A =? FB Φ Φ Φ Φ β=? V REF dφ dφ Series-Parallel Structure 39

40 Sampling Noise LK X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT Sampling noise from all stages must be referred back to input! V V V V... V A A A A A A INRMS IN IN IN3 INn n- n V INk V INRMS IN k- k= V i= A i See Katyal,Lin and Geiger, ISAS, for capacitor sizing for minimization of noise and power 40

41 V REF dφ V REF dφ Sampling Timing Φ Φ Φ Φ Φ Φ Φ Φ dφ dφ Even numbered stages sampled with φ and odd stages sampled with φ T LK φ φ First Sample SS ST SS ST S3S S3T S4S S4T S5S S5T S6S S6T S7S S7T S8S Second Sample SS ST SS ST S3S S3T S4S S4T S5S S5T S6S Second Sample SS ST SS ST S3S S3T S4S 4

42 Sampling Timing Φ Φ Φ Φ V REF dφ T LK dφ φ φ A φ φ A First Sample AD AD AD3 AD4 AD5 AD6 AD7 AD8 Second Sample AD AD AD3 AD4 AD5 AD6 Second Sample AD AD AD3 AD4 Quiet sampling is important 4

43 Bootstrapped Switch The ideal sampling operation Φ H Should track in the TRAK mode Should accurately sample at transition to HOLD mode 43

44 Bootstrapped Switch The ideal sampling operation Φ Φ H H Φ A Should track in the TRAK mode Should accurately sample at transition to HOLD mode 44

45 Bootstrapped Switch The ideal sampling operation R SW Φ H R S H If linear Φ A R SW V +R s OUT SW L = V + R +R +R s Attenuation Error IN S SW SW L f For high frequency inputs, an attenuation error will occur Affects absolute accuracy but not linearity But, if switches are nonlinear, will introduce a nonlinear error that can be very substantial Signal dependent R SW or switch nonlinearity will introduce nonlinear errors 45

46 Bootstrapped Switch Bootstrapping Principle φ φ V DD X φ φ φ 46

47 Bootstrapped Switch Bootstrapping Principle φ φ φ V DD X φ V DD φ φ X φ φ φ φ onceptual Realization May have difficult time turning on some switches May stress gate oxide! 47

48 Bootstrapped Switch Bootstrapping Principle φ V DD X φ φ φ From Galton, ISS 04 48

49 Bootstrapped Switch Bootstrapping Principle φ V DD X φ φ φ From Abo and Gray JS 99 49

50 Bootstrapped Switch Bootstrapping Principle φ V DD X φ φ φ From Roberts MWSAS

51 Bootstrapped Switch Bootstrapping Principle φ V DD X φ φ φ From Kaiser JS 00 5

52 Bootstrapped Switch Bootstrapping Principle φ V DD X φ φ φ From Steensgaard ISAS 999 5

53 Pipelined Data onverter Design Issue. AD offsets, Amp Offsets, Finite Op Amp Gain, DA errors, Finite Gain Errors all cause amplifiers to saturate. orrect interpretation of α k s is critical Guidelines Strategy. Out-range protection circuitry will remove this problem and can make pipeline robust to these effects if α k s correctly interpreted a) Use Extra omparators b) Use sub-radix structures. a) Accurately set α k values b) Use analog or digital calibration 3. Op Amp Gain causes finite gain errors and introduces noninearity 4. Op amp settling must can cause errors 5. Power dissipation strongly dependent upon GB of Op Amps 6. hoice of FB Amplifier Architecture seriously impacts performance 3. a) Select op amp architecture that has acceptable signal swing b) Select gain large enough at boundary of range to minimize nonlinearity and gain errors 4. Select GB to meet settling requirements (degrade modestly to account for slewing) 5. Minimize L, use energy efficient op amps, share or shut down op amp when not used,scale power in latter stages, eliminate input S/H if possible, interleave at high frequencies 6. Bottom plate sampling, bootatrapping, clock advance to reduce aperature uncertainty,critical GB, parasitic insensitivity needed, β dependent upon architecture and phase, compensation for worst-case β, TG if needed 53

54 Pipelined Data onverter Design Guidelines Issue 7. Sampling operation inherently introduces a sampled-noise due to noise in resistors Strategy 7. Select the capacitor sizes to meet noise requirements. ontinuous-time noise can also be present but is often dominated by sampled noise. Size switches to meet settling and noise requirements. Excessive GB will cause noise degradation in some applications, include noise from all stages (not just first stage). 8. Signal-dependent tracking errors at input introduce linearity degradation 8. Bootstrapped switches almost always used at input stage. Must avoid stressing oxide on bootstrapped switches 54

55 Aperture Uncertainty VREF V ( sinωt) IN T K Desired V Actual T K + T V V IN REF ωcosωt) t V V IN REF ω t MAX n+ V V / MAX REF T V ωv / IN REF t T MAX ω n 55

56 Aperture Uncertainty VREF V ( sinωt) IN T ω n Example: If f LK =00MHz, n=4 determine the aperture uncertainty T 4.86E-4. 05p sec 4 E8 Aperture uncertainty requirements can be very stringent! 56

57 Elimination of Input S/H LK X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT Why is input S/H used? 57

58 Elimination of Input S/H LK X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT Why is input S/H used? onventional Wisdom: Because want right sample at input Because gain stages mess up when input is time varying But what does an AD error do to the Boolean output? V in n α k k d k f(offset) f(residue) Absolutely nothing if over-range protection is provided! 58

59 Elimination of Input S/H LK X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT Why is input S/H used? onventional Wisdom: Because want right sample at input Because gain stages mess up when input is time varying 59

60 Elimination of Input S/H LK X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT LK X IN Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT Advance sampling clock a little so that sample is taken at quiet time but not too much to loose over-range protection 60

61 Fully Differential Architectues Second-order spectral component is often most significant contributor to SFDR and THD limitations in single-ended structures Noise from AD and other components, coupled through the substrate, often source of considerable noise in an AD All even-ordered spectral components are eliminated with fully-differential symmetric structures ommon mode noise is rejected with fully-differential symmetric structures Almost all implementations of Pipelined ADs are fully-differential Straightforward modification of the single-ended concepts discussed here Authors often present structures in single-ended mode and then just mention that differential structure was used Modest (but small) increase in area and power for fully differential structures 6

62 Pipelined Data onverter Design Issue. AD offsets, Amp Offsets, Finite Op Amp Gain, DA errors, Finite Gain Errors all cause amplifiers to saturate. orrect interpretation of α k s is critical Guidelines Strategy. Out-range protection circuitry will remove this problem and can make pipeline robust to these effects if α k s correctly interpreted a) Use Extra omparators b) Use sub-radix structures. a) Accurately set α k values b) Use analog or digital calibration 3. Op Amp Gain causes finite gain errors and introduces noninearity 4. Op amp settling must can cause errors 5. Power dissipation strongly dependent upon GB of Op Amps 6. hoice of FB Amplifier Architecture seriously impacts performance 3. a) Select op amp architecture that has acceptable signal swing b) Select gain large enough at boundary of range to minimize nonlinearity and gain errors 4. Select GB to meet settling requirements (degrade modestly to account for slewing) 5. Minimize L, use energy efficient op amps, share or shut down op amp when not used,scale power in latter stages, eliminate input S/H if possible, interleave at high frequencies 6. Bottom plate sampling, bootatrapping, clock advance to reduce aperature uncertainty,critical GB, parasitic insensitivity needed, β dependent upon architecture and phase, compensation for worst-case β, TG if needed 6

63 Pipelined Data onverter Design Guidelines Issue 7. Sampling operation inherently introduces a sampled-noise due to noise in resistors Strategy 7. Select the capacitor sizes to meet noise requirements. ontinuous-time noise can also be present but is often dominated by sampled noise. Size switches to meet settling and noise requirements. Excessive GB will cause noise degradation in some applications, include noise from all stages (not just first stage). 8. Signal-dependent tracking errors at input introduce linearity degradation 8. Bootstrapped switches almost always used at input stage. Must avoid stressing oxide on bootstrapped switches 9. Aperature uncertainty can cause serious errors 0. Input S/H major contributor to nonlinearity and power dissipation 9. Since latency usually of little concern, be sure that a clean clock is used to control all sampling. 0. Eliminate S/H but provide adequate over-range protection for this removal. Reduces power dissipation and improves linearity! 63

64 Layout Issues 64

65 Number of Bits/Stage 65

66 yclic (Algorithmic) ADs LK X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m Pipelined Assembler (Shift Register Array) n X OUT LK X IN S/H Stage r,r,.r m- n,n,... n Pipelined Assembler (Shift Register Array) n yclic (algorithmic) AD Reduces throughput but also area 66

67 yclic (Algorithmic) ADs LK X IN S/H Stage r,r,.r m- n,n,... n Pipelined Assembler (Shift Register Array) n LK LK X IN S/H Stage n r X IN Stage r n Pipelined Assembler (Shift Register Array) n Pipelined Assembler (Shift Register Array) n 67

68 End of Lecture 7

Nyquist-Rate A/D Converters

Nyquist-Rate A/D Converters IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling