Digital to Analog Converters I
|
|
|
- Mariah Craig
- 5 years ago
- Views:
Transcription
1 Advanced Analog Building Blocks 2 Digital to Analog Converters I Albert Comerma (PI) (comerma@physi.uni-heidelberg.de) Course web WiSe 2017
2 DAC parameters DACs parameters DACs non ideal effects DACs performance measurement N = number of bits V ref Full scale, V FS LSB = V FS /2 N b i = 0 or 1 V out = V FS N 1 i=0 b i = 2 N 1 LSB N 1 Note: for b i = 1, V out = V FS LSB V FS i=0 b i 2 i N c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 1 / 18
3 Ideal output DACs parameters DACs non ideal effects DACs performance measurement c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 2 / 18
4 DAC offset error DACs parameters DACs non ideal effects DACs performance measurement c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 3 / 18
5 DAC gain error DACs parameters DACs non ideal effects DACs performance measurement c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 4 / 18
6 Monotonicity DACs parameters DACs non ideal effects DACs performance measurement Ideally DACs should be monotonic c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 5 / 18
7 Saturation DACs parameters DACs non ideal effects DACs performance measurement Saturation on extreme values, usually close to power rails. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 6 / 18
8 Differential Non Linearity, DNL DACs parameters DACs non ideal effects DACs performance measurement Deviation of an output step from 1 LSB: DNL i = i stepsize LSB LSB, Extremes are taken i.e.: DNL = ±0.5LSBs c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 7 / 18
9 Integral Non Linearity, INL DACs parameters DACs non ideal effects DACs performance measurement Deviation of an output from ideal value, Cumulative sum of DNL: INL i = i j=0 DNL j c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 8 / 18
10 Idea of DAC performance DACs parameters DACs non ideal effects DACs performance measurement DNL < INL DNL > INL In reality always obtain a mix + offset + gain errors + saturation. Different methods to calculate INL: Typically after removing offset and gain errors. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 9 / 18
11 Examples: DACs parameters DACs non ideal effects DACs performance measurement 6 bit DAC 8 bit DAC c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 10 / 18
12 DACs classification Resistor string DACs Current steering DACs Segmented DACs DACs classification based on frequency domain performance. Nyquist rate DACs (Flash): Analog output samples are generated at the system sampling frequency Resistor string DAC Current steering DAC Thermometric Binary-weighted Segmented DAC Oversampling DACs: Analog output samples are generated at much higher frequencies than the system sampling frequency c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 11 / 18
13 Resistor string DACs Resistor string DACs Current steering DACs Segmented DACs All possible analog voltages are generated. Desired voltage is connected to the output. Monotonic. Good DNL/INL. Limitations: Speed limited by output RC. Large resistors needed for low power. Good matching for Rs. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 12 / 18
14 Resistor string DACs - tree Resistor string DACs Current steering DACs Segmented DACs Reduced parasitic capacitance. Decoder not needed. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 13 / 18
15 Thermometric DACs Resistor string DACs Current steering DACs Segmented DACs Thermometric code, one bit changes. Based on repetition of exact blocks (unity element). Binary to Thermometric decoder needed: Dec b 2 b 1 b 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 14 / 18
16 Current steering DAC, thermometric Resistor string DACs Current steering DACs Segmented DACs Fast and monotonic (by construction), good DNL. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 15 / 18
17 Current steering DAC, binary weighted Resistor string DACs Current steering DACs Segmented DACs Current switching, simple and fast. INL and DNL depends on matching, not inherently monotonic. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 16 / 18
18 Current steering DAC, R2R Resistor string DACs Current steering DACs Segmented DACs Reduced component spread due to the R-2R ratio. c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 17 / 18
19 Segmented DACs Resistor string DACs Current steering DACs Segmented DACs Combination of previous architectures; c comerma@physi.uni-heidelberg.de Advances Analog Building Blocks 2: DACs 18 / 18
20 Practice: simulate and compare different binary weighed DACs Use as a reference the following schematic, based on current binary weighted DAC. For a few µa bias current and 7bit resolution check DNL/INL on simulation. Perform a montecarlo simulation on DAC behaviour. Try to estimate area for an equivalent R2R version.
PARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.3-1 10.3 - EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS TECHNIQUE: Divide the total resolution N into k smaller sub-dacs each with a resolution of N k. Result:
D/A Converters. D/A Examples
D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction
Nyquist-Rate D/A Converters. D/A Converter Basics.
Nyquist-Rate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1
EE 435. Lecture 36. Quantization Noise ENOB Absolute and Relative Accuracy DAC Design. The String DAC
EE 435 Lecture 36 Quantization Noise ENOB Absolute and elative Accuracy DAC Design The String DAC . eview from last lecture. Quantization Noise in ADC ecall: If the random variable f is uniformly distributed
Data Converter Fundamentals
Data Converter Fundamentals David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 33 Introduction Two main types of converters Nyquist-Rate Converters Generate output
Analog and Telecommunication Electronics
Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D2 - DAC taxonomy and errors» Static and dynamic parameters» DAC taxonomy» DAC circuits» Error sources AY 2015-16
EE 435. Lecture 26. Data Converters. Data Converter Characterization
EE 435 Lecture 26 Data Converters Data Converter Characterization . Review from last lecture. Data Converter Architectures n DAC R-2R (4-bits) R R R R V OUT 2R 2R 2R 2R R d 3 d 2 d 1 d 0 V REF By superposition:
EE 521: Instrumentation and Measurements
Aly El-Osery Electrical Engineering Department, New Mexico Tech Socorro, New Mexico, USA September 23, 2009 1 / 18 1 Sampling 2 Quantization 3 Digital-to-Analog Converter 4 Analog-to-Digital Converter
EE 435. Lecture 26. Data Converters. Data Converter Characterization
EE 435 Lecture 26 Data Converters Data Converter Characterization . Review from last lecture. Data Converter Architectures Large number of different circuits have been proposed for building data converters
ir. Georgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 Eindhoven University of Technology Xilinx
Calibration of Current Steering D/A Converters ir. eorgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 1 Eindhoven University of Technology 2 Xilinx Current-steering
EE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
A novel Capacitor Array based Digital to Analog Converter
Chapter 4 A novel Capacitor Array based Digital to Analog Converter We present a novel capacitor array digital to analog converter(dac architecture. This DAC architecture replaces the large MSB (Most Significant
Successive Approximation ADCs
Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1- Successive Approximation ADC Vishal Saxena -2- Data Converter Architectures Resolution [Bits]
Lecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1
Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs
Lecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
Analog and Telecommunication Electronics
Politecnico di Torino - ICT School Analog and Telecommunication Electronics D3 - A/D converters» Error taxonomy» ADC parameters» Structures and taxonomy» Mixed converters» Origin of errors 12/05/2011-1
The influence of parasitic capacitors on SAR ADC characteristics
The influence of parasitic capacitors on SAR ADC characteristics DMITRY NORMANOV, DMITRY OSIPOV National Research Nuclear University MEPHI ASIC Lab 59, Moscow, Kashirskoe shosse, 3 RUSSIA simplere@ya.ru
DAC10* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017
* PRODUCT PAGE QUICK LINKS Last Content Update: 0/3/07 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Data Sheet : 0-Bit Current-Out DAC Data Sheet REFERENCE MATERIALS Solutions
Slide Set Data Converters. Digital Enhancement Techniques
0 Slide Set Data Converters Digital Enhancement Techniques Introduction Summary Error Measurement Trimming of Elements Foreground Calibration Background Calibration Dynamic Matching Decimation and Interpolation
EE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 7 Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling . Review from last lecture. MatLab comparison: 512 Samples
Behavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design
Behavioral Model of Split Capacitor Array DAC for Use in SAR ADC Design PC.SHILPA 1, M.H PRADEEP 2 P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur Asst Professor, Dept. of
Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors
Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors Zhiheng Wei 1a), Keita Yasutomi ) and Shoji Kawahito b) 1 Graduate School of Science and Technology,
A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs
204 UKSim-AMSS 6th International Conference on Computer Modelling and Simulation A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs Stefano Brenna, Andrea
BEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC FOR USE IN SAR ADC DESIGN
BEHAVIORAL MODEL OF SPLIT CAPACITOR ARRAY DAC FOR USE IN SAR ADC DESIGN 1 P C.SHILPA, 2 M.H PRADEEP 1 P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur 2 Asst Professor, Dept.
Pipelined multi step A/D converters
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 04 Nov 2006 Motivation for multi step A/D conversion Flash converters: Area and power consumption increase
EE 435. Lecture 38. DAC Design Current Steering DACs Charge Redistribution DACs ADC Design
EE 435 Lecture 38 DAC Design Current Steering DACs Charge edistribution DACs ADC Design eview from last lecture Current Steering DACs X N Binary to Thermometer ndecoder (all ON) S S N- S N V EF F nherently
Digital Electronic Meters
Digital Electronic Meters EIE 240 Electrical and Electronic Measurement May 1, 2015 1 Digital Signal Binary or two stages: 0 (Low voltage 0-3 V) 1 (High voltage 4-5 V) Binary digit is called bit. Group
Edited By : Engr. Muhammad Muizz bin Mohd Nawawi
Edited By : Engr. Muhammad Muizz bin Mohd Nawawi In an electronic circuit, a combination of high voltage (+5V) and low voltage (0V) is usually used to represent a binary number. For example, a binary number
Summary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold T/H circuits T/H combined
In this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents
In this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents around an electrical circuit. This is a short lecture,
EE 435. Lecture 26. Data Converters. Differential Nonlinearity Spectral Performance
EE 435 Lecture 26 Data Converters Differential Nonlinearity Spectral Performance . Review from last lecture. Integral Nonlinearity (DAC) Nonideal DAC INL often expressed in LSB INL = X k INL= max OUT OF
EE 435. Lecture 28. Data Converters Linearity INL/DNL Spectral Performance
EE 435 Lecture 8 Data Converters Linearity INL/DNL Spectral Performance Performance Characterization of Data Converters Static characteristics Resolution Least Significant Bit (LSB) Offset and Gain Errors
Research Article Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
Hindawi Publishing Corporation LSI Design olume 1, Article ID 76548, 8 pages doi:1.1155/1/76548 Research Article Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs Yan Zhu, 1
EE 505 Lecture 11. Statistical Circuit Modeling. R-string Example Offset Voltages
EE 505 Lecture 11 Statistical Circuit Modeling -string Example Offset oltages eview from previous lecture: Current Steering DAC Statistical Characterization Binary Weighted IL b= 1 1 IGk 1 1 I
Analog Digital Sampling & Discrete Time Discrete Values & Noise Digital-to-Analog Conversion Analog-to-Digital Conversion
Analog Digital Sampling & Discrete Time Discrete Values & Noise Digital-to-Analog Conversion Analog-to-Digital Conversion 6.082 Fall 2006 Analog Digital, Slide Plan: Mixed Signal Architecture volts bits
DATASHEET AD7520, AD7521. Features. Ordering Information. Pinouts. 10-Bit, 12-Bit, Multiplying D/A Converters. FN3104 Rev.4.
DATASHEET AD720, AD72 0Bit, 2Bit, Multiplying D/A Converters The AD720 and AD72 are monolithic, high accuracy, low cost 0bit and 2bit resolution, multiplying digitaltoanalog converters (DAC). Intersil
Oversampling Converters
Oversampling Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 56 Motivation Popular approach for medium-to-low speed A/D and D/A applications requiring
Nyquist-Rate A/D Converters
IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
8-bit 50ksps ULV SAR ADC
8-bit 50ksps ULV SAR ADC Fredrik Hilding Rosenberg Master of Science in Electronics Submission date: June 2015 Supervisor: Trond Ytterdal, IET Norwegian University of Science and Technology Department
EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances
EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances Parasitic Capacitors in MOSFET (will initially consider two) Parasitic Capacitors in MOSFET C GCH Parasitic Capacitors
EE 505 Lecture 8. Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 8 Clock Jitter Statistical Circuit Modeling Spectral Characterization of Data Converters Distortion Analysis Time Quantization Effects of DACs of ADCs Amplitude Quantization Effects of DACs
Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace
Switched Capacitor Circuits I. Prof. Paul Hasler Georgia Institute of Technology
Switched Capacitor Circuits I Prof. Paul Hasler Georgia Institute of Technology Switched Capacitor Circuits Making a resistor using a capacitor and switches; therefore resistance is set by a digital clock
Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II
Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II Administration: o Prayer Electricity and Electronics, Section 20.1, Digital Fundamentals: o Fundamentals:
Digital Signal 2 N Most Significant Bit (MSB) Least. Bit (LSB)
1 Digital Signal Binary or two stages: 0 (Low voltage 0-3 V) 1 (High voltage 4-5 V) Binary digit is called bit. Group of bits is called word. 8-bit group is called byte. For N-bit base-2 number = 2 N levels
Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
Analog to Digital Converters (ADCs)
Analog to Digital Converters (ADCs) Note: Figures are copyrighted Proakis & Manolakis, Digital Signal Processing, 4 th Edition, Pearson Publishers. Embedded System Design A Unified HW Approach, Vahid/Givargis,
EE 230 Lecture 40. Data Converters. Amplitude Quantization. Quantization Noise
EE 230 Lecture 40 Data Converters Amplitude Quantization Quantization Noise Review from Last Time: Time Quantization Typical ADC Environment Review from Last Time: Time Quantization Analog Signal Reconstruction
EE100Su08 Lecture #9 (July 16 th 2008)
EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart
Do not fill out the information below until instructed to do so! Name: Signature: Section Number:
Do not fill out the information below until instructed to do so! Name: Signature: E-mail: Section Number: No calculators are allowed in the test. Be sure to put a box around your final answers and clearly
A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation
A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation Congbing Li Haruo Kobayashi Gunma University Gunma University Kobayashi Lab Outline Research Objective & Background
8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash. ATtiny25 ATtiny25V. Appendix B. Appendix B ATtiny25/V Specification at +125 C
Appendix B ATtiny25/ Specification at +125 C This document contains information specific to devices operating at temperatures up to 125 C. Only deviations are covered in this appendix, all other information
EE 505. Lecture 13. String DACs
EE 505 Lecture 13 Strig DACs -Strig DAC V FF S 1 S 2 Simple structure Iheretly mootoe Very low DNL Challeges: S N-2 S N-1 S N S k d k Maagig INL Large umber of devices for large outig thermometer/bubble
EE 435. Lecture 29. Data Converters. Linearity Measures Spectral Performance
EE 435 Lecture 9 Data Converters Linearity Measures Spectral Performance Linearity Measurements (testing) Consider ADC V IN (t) DUT X IOUT V REF Linearity testing often based upon code density testing
EE 230 Lecture 43. Data Converters
EE 230 Lecture 43 Data Converters Review from Last Time: Amplitude Quantization Unwanted signals in the output of a system are called noise. Distortion Smooth nonlinearities Frequency attenuation Large
Introduction to digital systems. Juan P Bello
Introduction to digital systems Juan P Bello Analogue vs Digital (1) Analog information is made up of a continuum of values within a given range At its most basic, digital information can assume only one
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
Analog / Mixed-Signal Circuit Design Based on Mathematics
群馬大学 小林研究室 S23-1 Analog Circuits III 10:15-10:45 AM Oct. 28, 2016 (Fri) Analog / Mixed-Signal Circuit Design Based on Mathematics Haruo Kobayashi Haijun Lin Gunma University, Japan Xiamen University of
THE SAR ADC basic structure is shown in Fig. 1.
INTL JOURNAL OF ELETRONIS AND TELEOMMUNIATIONS, 2013, VOL. 59, NO. 2, PP. 161 167 Manuscript received March 4, 2013; revised May, 2013. DOI: 10.2478/eletel-2013-0019 The Impact of Noise and Mismatch on
Time Varying Circuit Analysis
MAS.836 Sensor Systems for Interactive Environments th Distributed: Tuesday February 16, 2010 Due: Tuesday February 23, 2010 Problem Set # 2 Time Varying Circuit Analysis The purpose of this problem set
WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
Chapter 8. Low-Power VLSI Design Methodology
VLSI Design hapter 8 Low-Power VLSI Design Methodology Jin-Fu Li hapter 8 Low-Power VLSI Design Methodology Introduction Low-Power Gate-Level Design Low-Power Architecture-Level Design Algorithmic-Level
Q. 1 Q. 25 carry one mark each.
GATE 5 SET- ELECTRONICS AND COMMUNICATION ENGINEERING - EC Q. Q. 5 carry one mark each. Q. The bilateral Laplace transform of a function is if a t b f() t = otherwise (A) a b s (B) s e ( a b) s (C) e as
NOISE-SHAPING SAR ADCS
NOISE-SHAPING SAR ADCS by Jeffrey Alan Fredenburg A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in the University of
Question 1. Question 2. Question 3
Question 1 Switch S in in the figure is closed at time t = 0, to begin charging an initially uncharged capacitor of capacitance C = 18.2 μf through a resistor of resistance R = 22.3 Ω. At what time (in
Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
Sistemas de Aquisição de Dados. Mestrado Integrado em Eng. Física Tecnológica 2016/17 Aula 4, 10th October
Sistemas de Aquisição de Dados Mestrado Integrado em Eng. Física Tecnológica 216/17 Aula 4, 1th October ADC Amplitude Quantization: ADC Digital Output Formats V REF +FS RANGE (SPAN) OR FS ANALOG INPUT
Switched Capacitor: Sampled Data Systems
Switched Capacitor: Sampled Data Systems Basic switched capacitor theory How has Anadigm utilised this. Theory-Basic SC and Anadigm-1 Resistor & Charge Relationship I + V - I Resistance is defined in terms
An 85%-Efficiency Fully Integrated 15-Ratio Recursive Switched- Capacitor DC-DC Converter with 0.1-to-2.2V Output Voltage Range
An 85%-Efficiency Fully Integrated 15-Ratio Recursive Switched- Capacitor DC-DC Converter with 0.1-to-2.2V Output Voltage Range Loai G. Salem and Patrick P. Mercier University of California, San Diego
Slide Set Data Converters. High-Order, CT Σ Converters and Σ DAC
0 lide et Data Converters High-Order, CT Σ Converters and Σ DAC 1 NR Enhancement ummary High Order Noise haping Continuos-Time Σ Modulators Band-Pass Σ Modulators Oversampling DAC 2 NR Enhancement Many
Digital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
EE247 Lecture 19. EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1. Summary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Clock boosters (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track
ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
Design Engineering MEng EXAMINATIONS 2016
IMPERIAL COLLEGE LONDON Design Engineering MEng EXAMINATIONS 2016 For Internal Students of the Imperial College of Science, Technology and Medicine This paper is also taken for the relevant examination
Modeling All-MOS Log-Domain Σ A/D Converters
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 1/22 Modeling All-MOS Log-Domain Σ A/D Converters X.Redondo 1, J.Pallarès 2 and F.Serra-Graells 1 1 Institut de Microelectrònica
PHY232 Spring 2008 Jon Pumplin (Original ppt courtesy of Remco Zegers) Direct current Circuits
PHY232 Spring 2008 Jon Pumplin http://www.pa.msu.edu/~pumplin/phy232 (Original ppt courtesy of Remco Zegers) Direct current Circuits So far, we have looked at systems with only one resistor PHY232 Spring
EE 505 Lecture 10. Statistical Circuit Modeling
EE 505 Lecture 10 Statistical Circuit Modeling Amplifier Gain Accuracy eview from previous lecture: - + String DAC Statistical Performance eview from previous lecture: esistors are uncorrelated but identically
PRODUCT OVERVIEW REF. IN 16 BIPOLAR OFFSET 17 REGISTER 74LS75 REGISTER 74LS75 BITS LSB
FEATURES -Bit resolution Integral nonlinearity error ±/LSB, max. Differential nonlinearity error ±/LSB, max. MIL-STD- high-reliability versions available Input register μs fast output settling time Guaranteed
I2 C Compatible Digital Potentiometers AD5241/AD5242
a Preliminary Technical ata FEATURES Position Potentiometer Replacement 0K, 00K, M, Ohm Internal Power ON Mid-Scale Preset +. to +.V Single-Supply; ±.V ual-supply Operation I C Compatible Interface APPLICATIONS
Electrical Circuits Lab Series RC Circuit Phasor Diagram
Electrical Circuits Lab. 0903219 Series RC Circuit Phasor Diagram - Simple steps to draw phasor diagram of a series RC circuit without memorizing: * Start with the quantity (voltage or current) that is
Successive approximation time-to-digital converter based on vernier charging method
LETTER Successive approximation time-to-digital converter based on vernier charging method Xin-Gang Wang 1, 2, Hai-Gang Yang 1a), Fei Wang 1, and Hui-He 2 1 Institute of Electronics, Chinese Academy of
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specificatio The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
NV Electronically Programmable Capacitor
Small Packages MSOP Flipchip NV Electronically Programmable Capacitor FEATURES Non-volatile EEPROM storage of programmed trim codes Power On Recall of capacitance setting High-Performance Electronically
TOP VIEW. Maxim Integrated Products 1
9-2266; Rev 2; 6/3 3ppm/ C, Low-Power, Low-Dropout General Description The high-precision, low-power, low-dropout voltage reference features a low 3ppm/ C (max) temperature coefficient and a low dropout
Unit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
SCOPE: CMOS, BUFFERED, MULTIPLYING 8-BIT D/A CONVERTER Type Generic Number Circuit Function 0 MX7528S(x)/883B DAC with ±4 LSB 02 MX7528T(x)/883B DAC with ±2 LSB 03 MX7528U(x)/883B DAC with ± LSB Case Outline(s).
Basic RL and RC Circuits R-L TRANSIENTS: STORAGE CYCLE. Engineering Collage Electrical Engineering Dep. Dr. Ibrahim Aljubouri
st Class Basic RL and RC Circuits The RL circuit with D.C (steady state) The inductor is short time at Calculate the inductor current for circuits shown below. I L E R A I L E R R 3 R R 3 I L I L R 3 R
DESCRIPTIO. LTC SMBus/I 2 C Accelerator* FEATURES APPLICATIO S TYPICAL APPLICATIO
SMBus/I 2 C Accelerator* FEATRES Improves SMBus/I 2 C TM Rise Time Transition Ensures Data Integrity with Multiple Devices on the SMBus/I 2 C Improves Low State Noise Margin Wide Supply Voltage Range:
Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
SCOPE: CMOS, BUFFERED, MULTIPLYING 8-BIT D/A CONVERTER Device Type Generic Number Circuit Function 0 MX7528S(x)/883B DAC with ±4 LSB 02 MX7528T(x)/883B DAC with ±2 LSB 03 MX7528U(x)/883B DAC with ± LSB
Homework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
Semiconductor Memory Classification
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH
EE 435. Lecture 25. Data Converters. Architectures. Characterization
EE 435 Lecture 5 Data Coverters Architectures Characterizatio . eview from last lecture. Data Coverters Types: A/D (Aalog to Digital) Coverts Aalog Iput to a Digital Output D/A (Digital to Aalog) Coverts
Measurement and Instrumentation. Sampling, Digital Devices, and Data Acquisition
2141-375 Measurement and Instrumentation Sampling, Digital Devices, and Data Acquisition Basic Data Acquisition System Analog Form Analog Form Digital Form Display Physical varialble Sensor Signal conditioning
CSCI 220: Computer Architecture-I Instructor: Pranava K. Jha. BCD Codes
CSCI 220: Computer Architecture-I Instructor: Pranava K. Jha BCD Codes Q. Give representation of the decimal number 853 in each of the following codes. (a) 8421 code (c) 84(-2)(-1) code (b) Excess-three
Very Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
Lecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters
Lecture 6, ATIK Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters What did we do last time? Switched capacitor circuits The basics Charge-redistribution analysis Nonidealties
Top-Down Design of a xdsl 14-bit 4MS/s Σ Modulator in Digital CMOS Technology
Top-Down Design of a xdsl -bit 4MS/s Σ Modulator in Digital CMOS Technology R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla CNM-CSIC