2.CMOS Transistor Theory

Transcription

1 CMOS LSI esig.cmos rasistor heory Fu yuzhuo School of microelectroics,sju Itroductio omar fadhil,baghdad

2 outlie PN juctio priciple CMOS trasistor itroductio Ideal I- characteristics uder static coditios yamic Characteristics No-ideal I- effects /59

3 iffusio&rift activity PN juctio diffusio P-type hole cocetratio>>n-type hole cocetratio N-type electro cocetratio>>p-type electro cocetratio iffusio result Build up space-charge regio(depletio) Stroger diffusio curret, wider space-charge regio rift result Opposite to the diffusio curret Resultig i a zero et flow 3/59

4 epletio Regio _juctio 4/59

5 PN juctio Eergy Bad Example a abrupt juctio has dopig desities of N A =10 15 atoms/cm 3, ad N =10 16 atoms/cm 3, calculate the built-i potetial at 300K, i is the itrisic carrier cocetratio i a pure sample of semi ad equals approximately 1.5X10 10 atoms/cm 3 势垒区 k NN = l( q NN ) = 0.06l( A Φ0 i i A ) 600m 5/59

6 Forward-bias Mode Applied potetial lowers the potetial barrier iffusio curret domiates the drift compoet 6/59

7 Reverse-bias mode Potetial barrier is raised rift curret becomes domiat he umber of miority carriers i the eutral regios is very small, so drift curret compoet ca almost be igored 7/59

8 P-jutio outlie PN juctio aalysis PN juctio curret PN juctio capacitace 8/59

9 iode static behavior Miority carrier cocetratio i the eutral regios ear the p-juctio uder forwardbias coditios Miority carrier cocetratio is supported by p-zoe majority carrier cocetratio 9/59

10 iode static behavior Miority carrier cocetratio i the eutral regios ear the p-juctio uder reverse-bias coditios 10/59

11 How to calculate diffusio curret? 1) (e 0 /Φ p qa I p p 1) (e 0 /Φ 1 qa I p p 1) (e 1) (e ) ( 0 0 /Φ /Φ 1 S p p p I p qa I I I p 11/59

12 iode Curret I = I S (e / 1)=I S (e 0.1/1*0.06 = k/q = 6m at 300K I S is the saturatio curret of the diode 1)=48.3I S 1/59

13 Models for Maual Aalysis + I = I S (e / 1) + + I o (a) Ideal diode model (b) First-order diode model Example 3. 13/59

14 PN juctio outlie PN juctio aalysis PN juctio curret PN juctio capacitace 14/59

15 yamic behavior of p-juctio Juctio capacitace/depletio capacitace -C j iffusio capacitace/dope capacitace -C d C dq d 15/59

16 Juctio capacitace P - + N + - he boudary of PN-juctio could accumulate charge whe bias voltage was chaged, which show capacitace characteristic he forward voltage improved,more charges pass,just like these charges are saved he forward voltage decreased, less charges pass, just like these charges are leaved 16/59

17 Juctio capacitace A A si j N N N N q A Q 0 Φ A A si j N N N N q A C Φ 0 0 A A si j N N N N q 0 1 Φ A A si j N N N N q E 0 Φ Φ 1 Φ 1 Φ 0 0 j j A A si j j C C N N N N q A d dq C epletio-regio charge Maximum electric field epletio-regio width Zero-bias coditios 17/59

18 Juctio Capacitace 18/59

19 iffusio capacitace* iffusio capacitace is domiat whe PN-jutio works uder forwardbias mode, because its curret is supported by miority carrier Charge of diffusio regio Q p qa qa Φ p e 1 p p I ( x ) p 0 p 0 p I dx p p (x) = p I ( ) - p - 0 x+ p Q p qa p p I ( ) - p - p 0 0 /Φ (e 1) 19/59

20 iffusio capacitace cot. p p p Q Q Q I p d I d di d dq C ) (e I I S 1 Φ p iffusio curret rasmit time p I Q 0/59

21 Juctio ad diffusio capacitace Forward-bias mode iffusio cap. Is domiat small RC effect for igorig Juctio cap. Reverse-bias mode Miority carrier cocetratio is very small, so its diffusio cap. Ca be igored Juctio cap. Is domiat large RC effect 1/59

22 PN juctio switch model /59

23 PN juctio switchig model R src 1 src I t = 0 t = Excess charge Space charge ON OFF ON ime 3/59

24 iode Model C d dq d di d I R S + I C C diode I 1 C j0 Φ m 0 - More kowledage: Microelectroic Circuits:Aalysis ad esig Muhammad H.Rashid 4/59

25 outlie PN juctio priciple CMOS trasistor itroductio Ideal I- characteristics uder static coditios yamic Characteristics Noideal I- effects 5/59

26 hat is a rasistor? A Switch! A MOS rasistor GS GS S R o 6/59

27 ermial oltages Mode of operatio depeds o gs, gd, ds ds = d s = gs - gd Source ad drai are symmetric diffusio termials source is termial at lower voltage Hece ds 0 MOS body is grouded. First assume source is 0 too. hree regios of operatio Cutoff Liear Saturatio s gs g + ds + gd - d 7/59

28 MOS threshold voltage MOS Cutoff No chael,i ds = 0 t > gs >0 depletio regio(iversio) is formed below the gate gs = t A strog iversio is built up, the potetial at the silico surface reaches a critical value Further icreases the gate voltage produce o further chages i the depletio layer width 8/59

29 outlie PN juctio priciple CMOS trasistor itroductio Ideal I- characteristics uder static coditios elocity Saturatio yamic Characteristics Noideal I- effects 9/59

30 MOS Liear Chael forms Curret flows from d to s e - from s to d I ds icreases with ds Similar to liear resistor gs > t gs > t gd = gs + + ds = 0 p-type body b + - s g g d + - gs > gd > t s d I ds + + p-type body b 0 < ds < gs - t 30/59

31 Cut-off eak iversio Strog iversio 31/59

32 Liear regime Pich off Saturated state 3/59

33 MOS i liear area μ = 3800cm /v.s,μ p =1800cm /v.s Charge per uit area: Qi ( x) C [ gs ( x) ] ox I v( x) Qi ( x) v( x) E( x) d I Cox[ gs ( x) ] dx L 0 I dx S 0 C ox [ gs ( x) ] d d dx I =μ C ox L [( gs - ) S - S ]=k ' L [( gs - ) S - S ] 33/59

34 he hreshold oltage where = 0 + ( - F + SB - - F ) 0 is the threshold voltage at SB = 0 ad is mostly a fuctio of the maufacturig process ifferece i work-fuctio betwee gate ad substrate material, oxide thickess, Fermi voltage, charge of impurities trapped at the surface, dosage of implated ios, etc. SB is the source-bulk voltage F = - l(n A / i ) is the Fermi potetial ( = k/q = 6m at 300K is the thermal voltage; N A is the acceptor io cocetratio; i 1.5x10 10 cm -3 at 300K is the itrisic carrier cocetratio i pure silico) = (q si N A )/C ox is the body-effect coefficiet (impact of chages i SB ) ( si =1.053x10-10 F/m is the permittivity of silico; C ox = ox /t ox is the gate oxide capacitace with ox =3.5x10-11 F/m) 34/59

35 I- character i resistive or liear regio Page 9 I k ' ' k GS L ( ox Cox t k = k ' L ox = ) S S Cox = L k ( ε t GS ox ox L ) S S Liear depedece betwee ds ad I 35/59

36 MOS Saturatio Chael piches off I ds idepedet of ds e say curret saturates Similar to curret source gs > t + - g + - gd < t s d I ds + + ds > gs - t p-type body b 36/59

37 I- relatio uder Saturatio coditio ds = gs - I k ( GS ) S S ds gs k ( GS ) k ' = u C ox = u ε t ox ox 37/59

38 I- characteristic of saturatio Charge per uit area: Qi ( x) C [ gs ( x) ] ox I v( x) Qi ( x) v( x) E( x) d I Cox[ gs ( x) ] dx d dx L 0 I dx I sat GS 0 = C k ' ox L [ gs ( x) - GS ] d 38/59

39 I (A) Curret-oltage Relatios Log-Chael evice 6 x 10-4 GS= Resistive Saturatio GS=.0 3 S = GS - GS= 1.5 Quadratic Relatioship 1 GS= S () 39/59

40 Aother method for givig I- Characteristics I Liear regio, I ds depeds o How much charge is i the chael? How fast is the charge movig? 40/59

41 Chael Charge MOS structure looks like parallel plate capacitor while operatig i iversio Gate oxide chael Q chael = C C = C g = ox L/t ox = C ox L = gc t = ( gs ds /) t C ox = ox / t ox gate t ox L + + p-type body polysilico gate SiO gate oxide (good isulator, ox = 3.9) g + + source gs C g gd drai - - chael s ds p-type body d 41/59

42 Carrier velocity Charge is carried by e- Carrier velocity v proportioal to lateral E-field betwee source ad drai v = E called mobility E = ds /L ime for carrier to cross chael: t = L / v 4/59

43 MOS Liear I- Now we kow How much charge Q chael is i the chael How much time t each carrier takes to cross I ds Q = t = k( GS c = μc - ox - S L ) ( S GS - k - = k ' S w L ) = u S C ox w L = u ε t ox ox w L 43/59

44 MOS Saturatio I- If gd < t, chael piches off ear drai he ds > dsat = gs t Now drai voltage o loger icreases curret Ids=k(gs-t-dsat/)dsat=k(gs-t) / 44/59

45 summary Shockley 1 st order trasistor models 0 gs<t cutoff I ds = k(gs-t-dsat/)dsat ds<dsat liear k(gs-t) / ds > dsat saturatio 45/59

46 outlie PN juctio priciple CMOS trasistor itroductio Ideal I- characteristics uder static coditios elocity Saturatio yamic Characteristics Noideal I- effects 46/59

47 I (A) Curret-oltage Relatios he eep-submicro Era.5 x 10-4 Early Saturatio GS= GS=.0 1 GS= 1.5 Liear Relatioship 0.5 GS= S () 47/59

48 Attetio : velocity positio μ = 3800cm /v.s,μ p =1800cm /v.s Charge per uit area: I Qi ( x) C [ gs ( x) ] ox I v( x) Qi ( x) v( x) E( x) d I Cox[ gs ( x) ] dx L 0 I C dx ox S 0 ( L C GS ox [ gs ) ( x) SA SA ] d ( SA ) d dx 48/59

49 u (m/s) elocity Saturatio u sat = 10 5 v 1 v sat c for for c c Costat velocity Costat mobility (slope = µ) x c = 1.5 x (/µm) he critical field depeds upo the dopig levels ad the vertical electrical field applied(1-5/um) 49/59

50 elocity Saturatio ) ( ) ( ) ( ) ( 1 S S S GS ox S S GS c S ox L C L L C I Lξ c 1+ 1 = κ() 50/59

51 elocity Saturatio Curret defiitio Assumig GS is high eough I sat C ox ( G SA ) C ox L ( GS ) SA SA ( SA ) ( ) SA G G 51/59

52 Perspective I Log-chael device GS = Short-chael device SA GS - S 5/59

53 I (A) I (A) I versus GS 6 x x quadratic 1.5 liear GS () Log Chael 0.5 quadratic GS () Short Chael 53/59

54 Aother two assumptios v v 1 sat c for for c c v v sat for for c c SA ( G G 1 L c G ) G Lv SA SA cl G SA is early costat 54/59

55 Modify the velocity formula to be coheret with the familiar log-chael equatios SA L c Lv SA I C v sat C ox C ox ox ( L ( L GS GS GS ) ) SA SA SA SA SA ( SA ) 55/59

56 I (A) Quadratic depedece I (A) Liear depedece I versus S 6 x GS=.5 Resistive Saturatio GS=.0 S = GS - GS= x GS=.5 GS=.0 GS= GS= GS= S () S () Log Chael Short Chael 56/59

57 A uified model for maual aalysis G S B 57/59

58 I (A) Simple Model versus SPICE.5 x 10-4 S = SA 1.5 elocity Saturated Liear SA = G S = G Saturated S () 58/59

59 I (A) A pmos rasistor 0 x GS = GS = GS = GS = S () Assume all variables egative! 59/59

60 Summary Strog Iversio GS > Liear (Resistive) S < SA Saturated (Costat Curret) S SA eak Iversio (Sub-hreshold) GS Expoetial i GS with liear I S depedece 60/59