EECS130 Integrated Circuit Devices

Transcription

1 EECS130 Itegrated Circuit Devices Professor Ali Javey 9/04/2007 Semicoductor Fudametals Lecture 3 Readig: fiish chapter 2 ad begi chapter 3

2 Aoucemets HW 1 is due ext Tuesday, at the begiig of the class. Late HWs will ot be accepted. Midterm 1 is o Oct. 4 th, i class. It s closed book, but you may brig ad use oe sheet of ote. Check EE130 web site ofte for lecture otes ad aoucemets. (

3 Last Lecture: Eergy Bad Diagram E c E d E v Eergy bad diagram shows the bottom edge of coductio bad, E c, ad top edge of valece bad, E v. E c ad E v are separated by the bad gap eergy, E g.

4 Carrier Cocetratios From desity of states ad Fermi fuctio, we obtai: p c v e e ( E E c f ( E E f v )/ kt )/ kt At EE f, f(e)1/2

5 Example: The Fermi Level ad Carrier Cocetratios Where is E f for cm -3? Solutio: c e ( E E c f )/ kt E c E f kt l ( ) ( l /10 ) ev c ev E c E f E v

6 The p Product ad the Itrisic Carrier Cocetratio Multiply c e ( E E c f )/ kt ad p v e ( E E f v )/ kt p c v e ( E E kt E c v )/ cve g / kt 2 p i i c v e E g / 2kT I a itrisic (udoped) semicoductor, p i.

7 EXAMPLE: Carrier Cocetratios Questio: What is the hole cocetratio i a -type semicoductor with cm -3 of doors? Solutio: cm -3. p i 10 cm cm 10 5 cm -3 After icreasig T by 60 C, remais the same at cm -3 while p 2 Eg / kt icreases by about a factor of 2300 because e. Questio: What is if p cm -3 i a P-type silico wafer? i Solutio: i 10 cm 17 3 p 10 cm 10 3 cm -3

8 EXAMPLE: Complete ioizatio of the dopat atoms d cm -3 ad E c -E d 45 mev. What fractio of the doors are ot ioized? Solutio: First assume that all the doors are ioized. d cm 3 E f E c 146meV 45meV 146 mev E d E c E f Probability of o-ioizatio e 1 E v 1+ e ( E E ) / kt ((146 45)meV) / 26meV d Therefore, it is reasoable to assume complete ioizatio, i.e., d. f 1

9 Doped Si ad Charge What is the et charge of your Si whe it is electro ad hole doped?

10 Bod Model of Electros ad Holes (Itrisic Si) Si Si Si Si Si Si Si Si Si Silico crystal i a two-dimesioal represetatio. Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Whe a electro breaks loose ad becomes a coductio electro, a hole is also created.

11 Dopats i Silico Si Si Si Si Si Si Si As Si Si B Si Si Si Si -type Si Si Si Si P-type Si As (Arseic), a Group V elemet, itroduces coductio electros ad creates -type silico, ad is called a door. B (Boro), a Group III elemet, itroduces holes ad creates P-type silico, ad is called a acceptor. Doors ad acceptors are kow as dopats.

12 Geeral Effects of Dopig o ad p Charge eutrality: _ a + d + a _ p : umber of ioized acceptors /cm3 : umber of ioized doors /cm3 d + 0 Assumig total ioizatio of acceptors ad doors: a + d + p 0 a d : umber of ioized acceptors /cm3 : umber of ioized doors /cm3

13 Geeral Effects of Dopig o ad p I. >> (i.e., -type) d a i d a p 2 i If d >> a, d ad p 2 i d II. >> a d i (i.e., P-type) p a 2 i p d If >>, a d p a ad 2 i a

14 EXAMPLE: Dopat Compesatio What are ad p i Si with (a) d cm -3 ad a cm -3 ad (b) additioal cm -3 of a? (a) d a cm 3 p 2 i / / cm 3 (b) a cm -3 > d! p a d 2 i / p cm d cm / cm cm d cm -3 3 a cm a cm p cm -3

15 Carrier Cocetratios at Extremely High ad Low Temperatures itrisic regime l d freeze-out regime high temp. room temperature cryogeic temperature 1/T

16 Ifrared Detector Based o Freeze-out To image the black-body radiatio emitted by tumors requires a photodetector that respods to hν s aroud 0.1 ev. I doped Si operatig i the freeze-out mode, coductio electros are created whe the ifrared photos provide the eergy to ioized the door atoms. electro photo E c E d E v

17 Chapter 2 Summary Eergy bad diagram. Acceptor. Door. m, m p. Fermi fuctio. E f. p c v e e ( E E c f ( E E f v )/ kt )/ kt p d a a d p i 2

18 Thermal Motio Zig-zag motio is due to collisios or scatterig with imperfectios i the crystal. et thermal velocity is zero. Mea time betwee collisios (mea free time) is τ m ~ 0.1ps

19 Thermal Eergy ad Thermal Velocity 2 electro or hole kietic eergy kt mv th v th 3kT m eff JK kg K m/s cm/s ~8.3 X 10 5 km/hr

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21 Drift Electro ad Hole Mobilities Drift is the motio caused by a electric field.

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23 Effective Mass I a electric field,, a electro or a hole accelerates. Remember : Fma-qE electros holes Electro ad hole effective masses Si Ge GaAs GaP m /m m p /m

24 Remember : FmamV/t -qe

25 Electro ad Hole Mobilities m p v q τ mp v q τ m p mp v v μ p qτ μ p m mp p μ qτ μ m m μ p is the hole mobility ad μ is the electro mobility

26 Electro ad Hole Mobilities v μ ; μ has the dimesios of v/ cm/s V/cm 2 cm V s. Electro ad hole mobilities of selected semicoductors Si Ge GaAs IAs μ (cm 2 /V s) μ p (cm 2 /V s) Based o the above table aloe, which semicoductor ad which carriers (electros or holes) are attractive for applicatios i high-speed devices?

27 Drift Velocity, Mea Free Time, Mea Free Path EXAMPLE: Give μ p 470 cm 2 /V s, what is the hole drift velocity at 10 3 V/cm? What is τ mp ad what is the distace traveled betwee collisios (called the mea free path)? Hit: Whe i doubt, use the MKS system of uits.

28 Drift Velocity, Mea Free Time, Mea Free Path EXAMPLE: Give μ p 470 cm 2 /V s, what is the hole drift velocity at 10 3 V/cm? What is τ mp ad what is the distace traveled betwee collisios (called the mea free path)? Hit: Whe i doubt, use the MKS system of uits. Solutio: ν μ p 470 cm 2 /V s 10 3 V/cm cm/s τ mp μ p m p /q 470 cm 2 /V s kg/ C m 2 /V s kg/c s 0.1 ps mea free path τ mh ν th ~ s cm/s cm 220 Å 22 m This is smaller tha the typical dimesios of devices, but gettig close.

29 Mechaisms of Carrier Scatterig There are two mai causes of carrier scatterig: 1. Phoo Scatterig 2. Impurity (Dopat) Io Scatterig Phoo scatterig mobility decreases whe temperature rises: μ phoo τ phoo phoo desity carrier 1 1 3/ 2 T 1/ 2 thermal velocity T T μ qτ/m T v th T 1/2

30 Impurity (Dopat)-Io Scatterig or Coulombic Scatterig Boro Io - _ - Electro Electro + Arseic Io There is less chage i the directio of travel if the electro zips by the io at a higher speed. μ impurity a v + 3 th d T + a 3 / 2 d

31 1600 Total Mobility Mobility (cm 2 V -1 s -1 ) Electros Holes 1 1 τ τ 1 μ phoo 1 μ phoo + + τ 1 impurity 1 μ impurity E14 1E15 1E16 1E17 1E18 1E19 1E20 Total Impurity Coceratio (atoms cm -3 a + d (cm -3 ) )

32 Temperature Effect o Mobility Questio: What d will make dμ /dt 0 at room temperature?

33 Velocity Saturatio Whe the kietic eergy of a carrier exceeds a critical value, it geerates a optical phoo ad loses the kietic eergy. Therefore, the kietic eergy is capped ad the velocity does ot rise above a saturatio velocity, v sat, o matter how large is. Velocity saturatio has a deleterious effect o device speed as we will see i the later chapters.