Chapter 2 Motion and Recombination of Electrons and Holes

Transcription

1 Chapter 2 Motio ad Recombiatio of Electros ad Holes 2.1 Thermal Eergy ad Thermal Velocity Average electro or hole kietic eergy 3 2 kt mv th v th 3kT m eff JK kg K m/s cm/s Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-1

2 2.1 Thermal Motio Zig-zag motio is due to collisios or scatterig with imperfectios i the crystal. Net thermal velocity is zero. Mea time betwee collisios is τ m ~ 0.1ps Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-2

3 Semicoductor Devices for Itegra

4 2.2.1 Electro ad Hole Mobilities m p v q τ mp v q τ m p mp v µ p qτ µ p m mp p v µ qτ µ m m µ p is the hole mobility ad µ is the electro mobility Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-4

5 2.2.1 Electro ad Hole Mobilities v µ ; µ has the dimesios of v/ cm/s V/cm 2 cm V s. Electro ad hole mobilities of selected semicoductors Si Ge GaAs IAs µ (cm 2 /V s) µ p (cm 2 /V s) Based o the above table aloe, which semicoductor ad which carriers (electros or holes) are attractive for applicatios i high-speed devices? Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-5

6 Drift Velocity, Mea Free Time, Mea Free Path EXAMPLE: Give µ p 470 cm 2 /V s, what is the hole drift velocity at 10 3 V/cm? What is τ mp ad what is the distace traveled betwee collisios (called the mea free path)? Hit: Whe i doubt, use the MKS system of uits. Solutio: ν µ p 470 cm 2 /V s 10 3 V/cm cm/s τ mp µ p m p /q 470 cm 2 /V s kg/ C m 2 /V s kg/c s 0.1 ps mea free path τ mh ν th ~ s cm/s cm 220 Å 22 m This is smaller tha the typical dimesios of devices, but gettig close. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-6

7 2.2.2 Mechaisms of Carrier Scatterig There are two mai causes of carrier scatterig: 1. Phoo Scatterig 2. Impurity (Dopat) Io Scatterig Phoo scatterig mobility decreases whe temperature rises: µ phoo τ phoo phoo desity carrier 1 1 3/ 2 T 1/ 2 thermal velocity T T µ qτ/m T v th T 1/2 Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-7

8 Impurity (Dopat)-Io Scatterig or Coulombic Scatterig Boro Io - _ - Electro Electro + Arseic Io There is less chage i the directio of travel if the electro zips by the io at a higher speed. µ impurity N a v + 3 th N d N T + a 3 / 2 N d Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-8

9 1600 Total Mobility Mobility (cm 2 V -1 s -1 ) Electros Holes 1 1 τ τ 1 µ phoo 1 µ phoo + + τ 1 impurity 1 µ impurity E14 1E15 1E16 1E17 1E18 1E19 1E20 Total Impurity N Coceratio (atoms cm -3 a + N d (cm -3 ) ) Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-9

10 Temperature Effect o Mobility Questio: What N d will make dµ /dt 0 at room temperature? Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-10

11 Velocity Saturatio Whe the kietic eergy of a carrier exceeds a critical value, it geerates a optical phoo ad loses the kietic eergy. Therefore, the kietic eergy is capped ad the velocity does ot rise above a saturatio velocity, v sat, o matter how large is. Velocity saturatio has a deleterious effect o device speed as show i Ch. 6. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-11

12 2.2.3 Drift Curret ad Coductivity J p ν uit area Curret desity J p qpv A/cm 2 or C/cm 2 sec EXAMPLE: If p cm -3 ad v 10 4 cm/s, the J p C cm cm/s C/s cm 1.6 A/cm Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-12

13 2.2.3 Drift Curret ad Coductivity J p,drift qpv qpµ p J,drift qv qµ J drift J,drift + J p,drift σ (qµ +qpµ p ) coductivity of a semicoductor is σ qµ + qpµ p Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-13

14 Relatioship betwee Resistivity ad Dopat Desity DOPANT DENSITY cm -3 N-type P-type RESISTIVITY (Ω cm) ρ 1/σ Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-14

15 EXAMPLE: Temperature Depedece of Resistace (a) What is the resistivity (ρ) of silico doped with cm -3 of arseic? (b) What is the resistace (R) of a piece of this silico material 1µm log ad 0.1 µm 2 i crosssectioal area? Solutio: (a) Usig the N-type curve i the previous figure, we fid that ρ Ω-cm. (b) R ρl/a Ω-cm 1 µm / 0.1 µm Ω-cm 10-4 cm/ cm Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-15

16 EXAMPLE: Temperature Depedece of Resistace By what factor will R icrease or decrease from T300 K to T400 K? Solutio: The temperature depedet factor i σ (ad therefore ρ) is µ. From the mobility vs. temperature curve for cm -3, we fid that µ decreases from 770 at 300K to 400 at 400K. As a result, R icreases by Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-16

17 2.3 Diffusio Curret Particles diffuse from a higher-cocetratio locatio to a lower-cocetratio locatio. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-17

18 J, diffusio 2.3 Diffusio Curret qd d dx J p, diffusio qd p dp dx D is called the diffusio costat. Sigs explaied: p x x Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-18

19 Total Curret Review of Four Curret Compoets J TOTAL J + J p J J,drift + J,diffusio qµ + J p J p,drift + J p,diffusio qpµ p qd qd p d dx dp dx Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-19

20 2.4 Relatio Betwee the Eergy Bad Diagram ad V, 0.7V V(x) E + N-Si 0.7V 0 x E c ad E v vary i the opposite directio from the voltage. That is, E c ad E v are higher where the voltage is lower. (x) dv dx 1 q de dx c 1 q de dx v x E c (x) E f (x) E v (x) Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-20

21 2.5 Eistei Relatioship betwee D ad µ Cosider a piece of o-uiformly doped semicoductor. -type N-type semicoductor Decreasig door cocetratio E c (x) E f E v (x) d dx Nc kt kt N c kt e e ( ( E de dx q E c c c E E f f ) / kt ) / kt de dx c Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-21

22 2.5 Eistei Relatioship betwee D ad µ d dx kt q d J qµ + qd 0 at equilibrium. dx qd 0 qµ q kt kt D µ q Similarly, kt D µ p p q These are kow as the Eistei relatioship. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-22

23 EXAMPLE: Diffusio Costat What is the hole diffusio costat i a piece of silico with µ p 410 cm 2 V -1 s -1? Solutio: kt D p µ p q (26 mv) 410 cm 2 V 1 s 1 11cm 2 /s Remember: kt/q 26 mv at room temperature. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-23

24 2.6 Electro-Hole Recombiatio The equilibrium carrier cocetratios are deoted with 0 ad p 0. The total electro ad hole cocetratios ca be differet from 0 ad p 0. These differeces are called the excess carrier cocetratios ad p. 0 + ' p p 0 + p' Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-24

25 Charge Neutrality Charge eutrality is satisfied at equilibrium ( p 0). Whe a o-zero is preset, a equal p may be assumed to be preset to maitai charge equality ad vice-versa. If charge eutrality is ot satisfied, the the et charge will attract or repel the (majority) carriers through the drift curret util eutrality is restored. ' p' Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-25

26 Recombiatio Lifetime Assume light geerates ad p. If the light is suddely tured off, ad p decay with time util they become zero. The process of decay is called recombiatio. The time costat of decay is the recombiatio time or carrier lifetime, τ. Recombiatio is ature s way of restorig equilibrium ( p 0). Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-26

27 Recombiatio Lifetime τ rages from 1s to 1ms i Si ad depeds o the desity of metal impurities (cotamiats) such as Au ad Pt. These deep traps capture electros or holes to facilitate recombiatio ad are called recombiatio ceters. E c Direct Recombiatio is ufavorable i silico with respect to mometum coservatio Recombiatio ceters E v Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-27

28 Rate of recombiatio (s -1 cm -3 ) d dt τ p d p dp dt τ τ dt Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-28

29 EXAMPLE: Photocoductors A bar of Si is doped with boro at cm -3. It is exposed to light such that electro-hole pairs are geerated throughout the volume of the bar at the rate of /s cm 3. The recombiatio lifetime is 10µs. What are (a) p 0, (b) 0, (c) p, (d), (e) p, (f), ad (g) the p product? Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-29

30 EXAMPLE: Photocoductors Solutio: (a) What is p 0? p 0 N a cm -3 (b) What is 0? 0 i2 /p cm -3 (c) What is p? I steady-state, the rate of geeratio is equal to the rate of recombiatio /s-cm 3 p /τ p /s-cm s cm -3 Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-30

31 (d) What is? p cm -3 EXAMPLE: Photocoductors (e) What is p? p p 0 + p cm cm cm -3 (f) What is? cm cm -3 ~ cm -3 sice 0 << (g) What is p? p ~ cm cm cm -6 >> i cm -6. The p product ca be very differet from i2. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-31

32 2.7 Thermal Geeratio If is egative, the there are fewer electros tha the equilibrium value. As a result, there is a et rate of thermal geeratio at the rate of /τ. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-32

33 2.8 Quasi-equilibrium ad Quasi-Fermi Levels Wheever p 0, p i 2. However, we would like to preserve ad use the relatios: p N N c v e e ( E E c )/ kt But these equatios lead to p i 2. The solutio is to itroduce two quasi-fermi levels E f ad E fp such that p N N c v e e f ( E E f v ( E E c )/ kt f ( E E fp Eve whe electros ad holes are ot at equilibrium, withi each group the carriers are usually at equilibrium. Electros are closely liked to other electros but oly loosely to holes. v )/ kt ) / kt Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-33

34 EXAMPLE: Quasi-Fermi Levels Cosider a Si sample with N d cm -3 ad p cm -3. (a) Fid E f. N d cm -3 N c exp[ (E c E f )/kt] E c E f 0.15 ev. (E f is below E c by 0.15 ev.) Now assume p cm -3. (b) Fid E f ad E fp. Note: ad p are much less tha the majority carrier cocetratio. This coditio is called low-level ijectio. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-34

35 EXAMPLE: Quasi-Fermi Levels cm -3 N c e ( E E c f )/ kt E c E f kt l(n c / cm -3 ) 26 mev l( cm -3 / cm -3 ) 0.15 ev E f is early idetical to E f because 0. Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-35

36 EXAMPLE: Quasi-Fermi Levels p cm -3 N v e ( E E fp )/ kt E fp E v kt l(n v /10 15 cm -3 ) 26 mev l( cm -3 /10 15 cm -3 ) 0.24 ev v E c E f E f E fp E v Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-36

37 2.9 Chapter Summary v µ p v µ p J qpµ p, drift J qµ, drift p J J, diffusio p, diffusio qd kt D µ q qd kt D p µ p q d dx p dp dx Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-37

38 2.9 Chapter Summary τ is the recombiatio lifetime. ad p are the excess carrier cocetratios. 0 + p p 0 + p Charge eutrality requires p. rate of recombiatio /τ p /τ E f ad E fp are the quasi-fermi levels of electros ad holes. ( E E ) / kt N p N c v e e c ( E E fp f v )/ kt Semicoductor Devices for Itegrated Circuits (C. Hu) Slide 2-38