Semiconductors a brief introduction

Transcription

1 Semicoductors a brief itroductio Bad structure from atom to crystal Fermi level carrier cocetratio Dopig Readig: (Sedra/Smith 7 th editio) Trasport (drift-diffusio) Hyperphysics (lik o course homepage) basic itroductio to semicoductors (almost o equatios) Moder lectroics: F1 semicoductors 1

2 Atomic eergy levels M Quatum mechaics: Wavefuctio gives describes probablility to fid electro M L K L K x 0.1 m 0.1 m Moder lectroics: F1 semicoductors 2

3 2-atomic molecule Pauli priciple Atoms share valece electros 0.2 m Overlappig Valece electros x x x Moder lectroics: F1 semicoductors 0.1 m 0.2 m 0.1 m 3

4 16-atomic molecule 0.4 m 0.4 m x x x,y,z Moder lectroics: F1 semicoductors 0.1 m 0.4 m 4

5 atomic molecule eergy bads ~ levels 1 cm x,y,z x 1 cm Moder lectroics: F1 semicoductors 0.1 m 5

6 Valece ad coductio bads Coductio bad Valece bad Valece Bad: The highest bad that has electros Coductio Bad: The ext bad with higher eergy Metal: The valece bad is partially filled with electros Semicoductor / Isulator: The valece bad is filled x,y,z Moder lectroics: F1 semicoductors 6

7 ergy (ev) metals semicoductors - isulators Metal Coductio bad semicoductors 0 < g < 4 ev Si: g =1.12 ev Ge: g =0.67 ev Ga: g =3.42 ev Coductio bad Coductio bad isulators g > 4eV SiO 2 : g =9 ev Diamod (C): g =5.5 ev Coductio bad g g Valece bad Valece bad Valece bad Valece bad Moder lectroics: F1 semicoductors 7 x

8 What materials are semicoductors? Two atom basis (4 eighbours) 4 ow valece electros III B IV C V total 8 shared electros i valece shell -> filled! Al Ga Si Ge P As 4+14=8 3+5=8 I S Sb C GaP Si Ge IAs S g 5.5 ev 2.24 ev 1.12 ev 0.67 ev 0.34 ev 0 Type isulator Semi cod uc tors metal Moder lectroics: F1 semicoductors 8

9 ergy (ev) Thermal excitatio ach electros gets (average) kietic eergy ki =3/2 kt A electro ca be excited to the coductio bad g Higher T or smaller g -> more electros electro desity i coductio bad = (cm -3 ) electro desity i valece bad = (cm -3 ) p (cm -3 ): hole desity i valece bad =p without dopig Moder lectroics: F1 semicoductors 9

10 ergy (ev) Thermal excitatio Fermi level Fermi-Dirac distributio: The probability of a electro at a eergy level. C f ( ) exp(( 1 F ) / kt ) 1 g F Higher T higher probability that a level i the coductio bad has a electro. V Symmetrical about F (Fermi eergy). 50% chace to have electro at F xcited electro leave a positive hole i valece bad 0 1 probability Moder lectroics: F1 semicoductors 10

11 Holes vs electros Istead of describig all electros remaiig i valece bad, positive holes (missig electros) are itroduced ad treated as particles. T > 0 K C V e electro (egative) hole (positive) Moder lectroics: F1 semicoductors 11

12 lectro trasport - Apply voltage -> electric field moves charged electros - Filled bad: ½ of electros move i oe directio, ½ of electros i the other. - eed to chage velocity of some electros to get curret but all states are filled i.e. eed electros i coductio bad. T 0 K e T >> 0 K e metal semicoductor semicoductor C C V V Partially filled bad o available eergy states to move to leads to zero curret Moder lectroics: F1 semicoductors 12

13 eergy Carrier cocetratio probability of occupyig a state x umber of = available states populatio of coductio bad c Fermi-Dirac distributio x desity of states = carrier cocetratio Moder lectroics: F1 semicoductors 13

14 ergy (ev) Carrier cocetratio - simplified exp v F C p v exp kt g F c F kt c V Igore real desity of states, itroduce C, V effective desity of states at bad edges (describes how dese levels are) (Si: c =3.2*10 19 cm -3 / v =1.8*10 19 cm -3 ) Moder lectroics: F1 semicoductors 14

15 Itrisic carrier cocetratio ach electro excited from the valece bad to the coductio bad become a free carrier available for coductio Itrisic semicoductor: - =p= i (itrisic carrier cocetratio) - F is i the middle of the bad gap i p c v exp 2kT g T=300K Si g =1.11eV i = cm -3 Ge g =0.67 ev i = cm -3 Moder lectroics: F1 semicoductors 15

16 Dopig with door atoms: -type c +1 v III IV V x P atom 5 valece electros B Al C Si P Doates electro to the coductio bad (mobile) Ioized atom positive (immobile) Ga I Ge S As Sb Moder lectroics: F1 semicoductors 16

17 Dopig with acceptor atoms: p-type c -1 v III IV V x Al atom 3 valece electros B Al C Si P Captures electro -> extra hole to the valece bad (mobile) Ioized atom egative (immobile) Ga I Ge S As Sb Moder lectroics: F1 semicoductors 17

18 Dopig extrisic semicoductor p c v F exp( kt v exp( kt c F ) ) p c v exp kt g 2 i Mass actio law p 2 i Idepedet of dopig - D : door atom desity (cm -3 ) / A : acceptor atom desity (cm -3 ) - For D >> i ( A =0) the dopig domiates majority carrier cocetratio = D ad p= i2 / D Moder lectroics: F1 semicoductors 18

19 dopig carrier desity Fermi-Dirac Carrier coc. electros c Itrisic g Fi holes v 0 1 p -type (doors) F V Fi kt l D i p-type (acceptors) Fp V Fi kt l i A Moder lectroics: F1 semicoductors 19

20 dopig carrier desity Fermi-Dirac Carrier coc. electros c Itrisic g Fi holes v 0 1 p -type (doors) F F Fi kt l D i p-type (acceptors) Fp Fi kt l i A Moder lectroics: F1 semicoductors 20

21 dopig carrier desity Fermi-Dirac Carrier coc. electros c Itrisic g Fi holes v 0 1 p -type (doors) F F Fi kt l D i p-type (acceptors) Fp Fi kt l i A Moder lectroics: F1 semicoductors 21

22 Trasport - drift J J p J qp ε Hole curret desity (A/cm 2 ) J v d p q ε J p lectro curret desity (A/cm 2 ) e J q q p 1 p p p +V µ / µ p electro / hole mobility (cm 2 /Vs) / p electro / hole cocetratio (cm -3 ) =1/=coductivity (S/m) = resistivity (Ωm) C V Moder lectroics: F1 semicoductors 22

23 Trasport effect of dopig J qv d qµ e : cotrolled by dopig µ : determied by itrisic semicoductor properties + scatterig phoo scatterig -type p-type Ioized impurity scatterig Moder lectroics: F1 semicoductors 23

24 Moder lectroics: F1 semicoductors Velocity saturatio 24 - At high electric fields (ε c 1.5x10 6 V/m) electros ca emit optical phoos (lattice vibratios) -> velocity saturates sat c d c d c c d d v µ v µ v µ v qµ qv J e e e e e e e e e e e / 1 ) (

25 Trasport - diffusio - Radom thermal motio gives movemet of particles from high to low cocetratio - o exteral forces - o particle iteractio - Rate depeds o cocetratio gradiet Moder lectroics: F1 semicoductors 25

26 (m -3 ) Trasport - diffusio Diffusio curret give by gradiet of electro (or hole) cocetratio J qd d( x) dx q kt q µ d( x) dx qv T µ d( x) dx o additio/removal of carriers betwee 0 < x < L -> costat curret -> liear cocetratio decrease J (0)= 0 (x) (L)= L x Moder lectroics: F1 semicoductors 26

27 2 mi exercise drift/diffusio Later... positio positio Sketch carrier distributio later with 1. o electric field 2. -field i pos. directio (->) Moder lectroics: F1 semicoductors 27

28 Summary - Discrete atomic eergy levels become bads whe atoms are joied i a crystal. - Semicoductors = filled valece bad, o electros i coductio bad (at T=0). Bad gap with o allowed states. - Carrier cocetratio () = Fermi-dirac distributio * desity of states - Dopig: c kt Doors (group V): adds mobile egative electros ad positive static ios. Moves Fermi level towards coductio bad. Acceptors (group III): adds mobile positive holes ad egative static ios. Moves Fermi level towards valece bad. 2 p = D ad p= i2 / D for D >> i - Carrier trasport: Drift: electric field moves charged particles. Depeds o field stregth. Diffusio: radom motio moves particles from high to low cocetratio. Depeds o cocetratio gradiet. J J, drift J, diff q ε qd Moder lectroics: F1 semicoductors i d dx exp( F 28 c )

29 p- juctios Charge distributio -> electric field -> potetial Curret trasport Breakdow mechaisms Small-sigal model Depletio / diffusio capacitaces Readig: (Sedra/Smith 7 th editio) , Moder lectroics: F1 semicoductors 29

30 Why p-juctios? -type diode LD Solar cell P-type mitter BJT Base -type P -type Collector MOSFT Source -type Gate P-type Drai -type Substrate Moder lectroics: F1 semicoductors 30

31 - type P - type electros electros c c g g holes v v holes D door cocetratio 0 electro (majority) cocetratio p 0 hole (miority) cocetratio lectros: mobile, egative Ioized doors: ot mobile, positive A acceptor cocetratio p p0 hole (majority) cocetratio p0 electro (miority) cocetratio holes: mobile, positive Ioized acceptors: ot mobile, egative Moder lectroics: F1 semicoductors 31

32 Recombiatio p i I equilibrium Importat for base curret i BJTs If there is a excess umber free carrriers p > i2 electros ca recombie with holes to reach equilibrium 0 = D + 0 < D + C Three electros recombie leavig three positive ioized door atoms v p > p 0 Moder lectroics: F1 semicoductors 32

33 P-juctio bad structure d J dx + Positive door - egative Acceptor -type Free electros Free holes P-type c v Large coc. differece -> large diffusio curret o e-field o drift curret c v I qa ε V T d( x) dx Moder lectroics: F1 semicoductors 33

34 P-juctio bad structure + Positive door - egative Acceptor Free electros Free holes -type P-type c v e c v I qa ε V T d( x) dx Moder lectroics: F1 semicoductors 34

35 P-juctio bad structure + Positive door - egative Acceptor Free electros Free holes -type P-type c v e c v e W Moder lectroics: F1 semicoductors o free carriers i depletio regio, charge eutral outside 35

36 charge desity -> electric field -> potetial Poisso equatio Depletio width ρ(x) ε s W = = dε(x) dx 2ε s q = d2 V(x) dx 2 - ρ charge desity [C/m -3 ] - ε s permitivity [F/m] - e electric field [V/m] - V potetial [V] 1 A + 1 D V 0 - V 0 built-i potetial [V] Q + =Aq D W 1 ρ [C/m -3 ] න dx e [V/m] න dx V(x) [V] X=W 2 x=w 2 V 0 x=-w x=-w 1 x=0 W=W 1 +W 2 Moder lectroics: F1 semicoductors x=0 36

37 Built-i potetial P W=W 1 +W 2 c c qv 0 F qv 0 Fp v v depletio regio qv 0 = F Fp (built-i) Potetial barrier for electros ad holes! F Fp Fi Fi kt l kt l i i A D D A qv 0 0 kt l l kt l i i D 2 i A homework: calculate depletio width for Si p-juctio with D = A =10 17 cm -3 at bias voltages V=0 V ad V= -1 V. Moder lectroics: F1 semicoductors 37

38 2 mi exercise assymetric p-juctio Cosider a p-juctio with D =5* A (doors > acceptors) Sketch the 1) charge distributio 2) electric field 3) potetial -type D P-type A ρ ε V Moder lectroics: F1 semicoductors 38

39 Diode forward bias - Oly top of the electro distributio ca pass over the barrier - Icrease bias -> expoetially icreasig amout of electros ca pass - Reduce electric field but couteractig built-i potetial - Depletio width is reduced e P e P ev D ev D - V D + D pot =-qv D - V D + Moder lectroics: F1 semicoductors 39

40 cotact depletio regio cotact Miority carrier desity at depletio edges at forward bias forward bias p / p hole cocetratio i -side electro cocetratio i p-side p (x) p (x) p (x) p (x) p 0 p0 At equilibrium: p0 = i2 / A p 0 = i2 / D p -W 1 0 W 2 qvd W ) p exp qvd 1 p ( W2 ) p0 exp kt kt ( 0 Moder lectroics: F1 semicoductors 40

41 V D Diode forward bias e P J qε V T d dx I D pot =-ev D ev D V D J = J S (exp(v/v T )-1) - V D + Moder lectroics: F1 semicoductors J s = q D p p L 0 + D p L p0 = q 1 2 kt L p q μ i p + 1 kt D L q μ 41 i 2 A

42 Diode reverse bias e P J qε V T d dx I D pot =-ev D ev D V D -V D J 0 + V D - Moder lectroics: F1 semicoductors 42

43 Diode total curret J = J s e qv kt 1 Τ J s = saturatio curret desity = ideality factor (1-2) J s = q D p p L 0 + D p L p0 = q 1 2 kt L p q μ i p + 1 kt D L q μ i 2 A zero bias P forward bias reverse bias e diffusio curret drift curret diffusio curret drift curret diffusio curret drift curret Moder lectroics: F1 semicoductors 43

44 1 mi excercise Si vs Ge diode Si ( g =1.11 ev) p-juctio Ge ( g =0.67 ev) p-juctio P P I I V D??? V D Moder lectroics: F1 semicoductors 44

45 Zeer tuelig / Avalache Breakdow - High reverse bias gives eough e-field to eable tuelig - High eergy of electro/hole ca be lost by creatig ew e-h pairs through impact ioizatio tuelig e avalache multiplicatio e BV I V Moder lectroics: F1 semicoductors 45

46 small-sigal model - Wat to replace o-liear compoets with liear oes to simplify circuit calculatios - Costat V D + small varyig v d (t) = total voltage v D (t). v D (t) V D = + v d (t) t Liearize by Taylor expasio Moder lectroics: F1 semicoductors 46

47 Small-sigal model of diode (3.3.7) - Diode IV is o-liear so difficult to do calculatios - Apply costat V D ad small varyig v d (t) - Diode IV almost liear i a small regio Τ J = J s eqv kt D Τ 1 J s eqv D kt Small sigal resistace r d =V T /I D (V T =kt/q) Moder lectroics: F1 semicoductors 47

48 depletio-regio / juctio capacitace xample: paralell plate capacitor Defiitio: C Q V C e re0 W W 1 2 A -Q e r +Q W 1 +W 2 Q J = A q D (W 1 + W 2 ) W V 0 + V R o-liear relatioship betwee V R ad Q -> C(V R ) W 1 W 2 W 1 W 2 Moder lectroics: F1 semicoductors 48

49 depletio regio / juctio capacitace Defiitio C j = dq J dv R Applied bias (V R ) chages depletio width Depletio width W = 2ε s q 1 A + 1 D (V 0 + V R ) Charge o either side Q J = Aq D W 1 = Aq D A A + D W C j C J = A 2ε s q D A A + D 1 V 0 +V R V Icreasig V R Moder lectroics: F1 semicoductors 49

50 1 mi exercise p-juctio with forward bias I forward bias there is a diffusio curret flowig through the juctio. How does the CV curve behave? dq Oly C j C dv A B C C C C V V V o chage i capacitace Larger capacitace for forward bias Moder lectroics: F1 semicoductors Lower capacitace for forward bias 50

51 diffusio capacitace Forward bias -> iject miority carriers i eutral regios (electros i p-regio ad holes i -regio)-> extra charge dq. p p ( W ( W 2 p ) ) p0 p0 exp qv kt D C dq dv V+Dv V DQ -W 1 W 2 p0 W 2 (=0) x W p (legth of p-regio) Moder lectroics: F1 semicoductors 51

52 Total capacitace C tot C tot =C j +C d Add capacitaces i parallel Capacitace (pf) C j C d 10 C j : domiates for reverse bias Voltage (V) C diff : domiates for forward bias. C diff 0 for reverse bias. r d (V D ) C j (V) C d (V) Moder lectroics: F1 semicoductors 52

53 Summary p-juctios p-juctios used i LDs, solar cells, BJT, MOSFTs Poissos equatios: charge distributio -> electric field -> potetial Drift is balaced by diffusio i ubiased p-juctio Curret give by ideal diode equatio: Forward bias: curret (diffusio) icreases expoetially Reverse bias: curret saturates qv J = J s e kt 1 Τ Capacitaces: Juctio capacitace due to chage i depletio width (domiates reverse bias) Diffusio capacitace due to chage i charge i p/ regio (domiates forward bias) Small-sigal model (ok for V << V T ): replace diode with resistor + capacitaces Moder lectroics: F1 semicoductors 53