EE3310 Class notes Part 3. Solid State Electronic Devices - EE3310 Class notes Transistors

Transcription

1 EE3310 Class otes Part 3 Versio: Fall 2002 These class otes were origially based o the hadwritte otes of Larry Overzet. It is expected that they will be modified (improved?) as time goes o. This versio was typed up by Matthew Goecker. Homework Sets Set 8 Due Tuesday Nov. 19 th, 2002 Chapter 6 #: 1, 2, 3, 4, 5, 10, 11 Set 9 Due Thursday Nov. 21 st, 2002 Chapter 6 #: 12, 15, 19, 20 Notes: Do ot do the followig: #12 do ot do the Boro dose part #19 do ot do the substrate (bulk) bias = V part Set 10 Due Tuesday Nov. 26 th, 2002 Chapter 7 #: 3, 6, 7, 8, 10, 11, 24 Solid State Electroic Devices - EE3310 Class otes Trasistors Now we will take our p- juctios ad use them to make trasistors. We will start with the Field Effect Trasistor, FET. We do this mostly for historical reasos. (The first FET was pateted i the 1920 s ad 30 s!) The first moder FET, a Juctio FET JFET, was that produced by William Shockley, i This started the rapid growth i the field that you are ow studyig. Before we start, we eed to establish a few terms. Source This is where the charge carriers come from. By ecessity this meas the locatio at which majority carriers leave the metal cotact ad eter the device. Source also refers to the side of the device coected to that metal cotact. Drai This is where the charge carriers leave the device. Agai by ecessity this is where the majority carriers leave the device. Gate This is what cotrols the flow of charge carriers through the device. (If the is closed, othig ca go though ) UTD EE3301 otes part 3 Page 127of (57+126) Last update 7:55 PM 11/27/02

2 Chael This is the regio i which most of the charge carriers flow. The is used to ope ad close the chael. Juctio Field Effect Trasistor, J-FET source (with metallic cotact) p + drai (with metallic cotact) p + The origial devices looked ot ulike the picture above. It is with this picture that we will build a uderstadig of how they operate. [Uderstad that moder J-FETs ca look very differet! A example is show i the figure below. source drai SiO + p metallic cotact p + Except for some geometric affects that we will ot worry about i this class, this operates i much the same way that the origial versio worked. Qualitative aalysis of J-FETs To establish the basic priciples behid the J-FET we will first look qualitatively at what happes to the device. UTD EE3301 otes part 3 Page 128of (57+126) Last update 7:55 PM 11/27/02

3 source (with metallic cotact) p + drai (with metallic cotact) L 2a p + What do we kow. 1) If there is o bias applied to the, the depletio regios (or juctios i p + - devices) is fairly arrow. 2) Most of the depletio regio aroud the is i the -side of the juctio. This is because the desity of the -side is much lower tha the p + -side. Because the total charge iside the juctio must be zero, more of the juctio must be o the -side. 3) If there is a small bias betwee the source ad the drai, electros will flow from the source to the drai. 4) The source side of the device is assumed to have a zero bias. (This is of course a relative value!) 5) The bias will be assumed to be equal to or egative relative to the source bias. 6) The drai bias will be assumed to be equal to or positive relative to the source bias. a. A + -p- + versio of this will have the opposite polarity with holes beig the domiate charge carrier. 7) The legth of the device, L, is much larger tha the width, 2a. Let us ow draw a ew picture of what the device looks like with the depletio regio show. depletio source (with metallic cotact) p + drai (with metallic cotact) p + Because the depletio regio lacks charge carriers, all of the curret flow must go betwee the top ad bottom depletio regios. (This i quite true. Remember that we ca still have curret flow through a p- juctio, which is simply a depletio regio this however is via the miority carriers! Here however, the area betwee the regios will have may more charge carriers as the majority carriers ca ad do play a major role.) This regio is kow as the chael. Now we ca do oe of two thigs. We ca tur up the bias o the drai or we ca make the bias more egative. Let us chage the first. Whe we do this, the depletio regio grows, makig our Adjustig the UTD EE3301 otes part 3 Page 129of (57+126) Last update 7:55 PM 11/27/02

4 Makig the bias more egative with respect to the source will cause the depletio regio to grow i size. Oce we have made the egative eough, the width of the chael will go to zero, as pictured below. depletio source (with metallic cotact) p + drai (with metallic cotact) p + Whe this happes the majority carriers will o loger be preset, ad the curret will be shut-off. (It is ot a complete shut-off as we will see later.) The voltage at which pich-off occurs for o sourcedrai bias, V sd = 0, is kow as the pich bias, V p. For some reaso, Streetma has labeled this as a positive umber. However, it must be a egative voltage for a J-FET like show above. (If we had the opposite materials, it could ad would be positive.) Now let us go back to a case i which the bias is zero relative to the source bias. Before, we had a very small bias betwee the source ad the drai, say less tha 0.1 V. Now, let us raise the drai bias to +5 V relative to the source. This will cause sigificatly more curret to flow. (We ca uderstad this by realizig that the mobility of the electros will remai about the same, ad thus the velocity of the electros must icrease sigificatly.) Uder these coditios, we have a electric field i the - material that is approximately E V sd L y ˆ (Some geometric affects will cause the electric field to be slightly differet tha this, but if L>>2a, the the differece is ot large.) This meas that the -material has a gradiet of the bias across the system. Assumig our liear approximatio we get a picture that looks like: depletio source (with metallic cotact) p + drai (with metallic cotact) V sg p + V sd No however we have a reverse bias betwee the chael ad the. As this bias gets larger, the larger the depletio regio becomes. This implies that we have growig depletio regio width ad hece arrowig chael width as we move toward the drai. This will look ot ulike: UTD EE3301 otes part 3 Page 130of (57+126) Last update 7:55 PM 11/27/02

5 depletio source (with metallic cotact) p + drai (with metallic cotact) V sg p + V sd Let us cotiue to icrease the source-drai voltage At some poit, the depletio regios will meet ad we get pich off. depletio source (with metallic cotact) p + Pich-off drai (with metallic cotact) V sg p + V sd What will happe ow? Before, we expected the curret to cotiue to grow as we icreased the bias. I fact, we expected the curret to grow i a approximately liear fashio with respect to the voltage. Whe pich-off occurs, we expect the curret to reach a costat value. The pich-off ca ot stop the curret flow as it requires that we have a bias iside the material which i tur requires that we have a curret flow. This meas that we should have a curret-voltage trace that looks like: I sd Narrowig of chael Pich-off Liear regio V sd UTD EE3301 otes part 3 Page 131of (57+126) Last update 7:55 PM 11/27/02

6 Side ote o device resistace: We kow that the coductace is give by: σ = qµ + qpµ p qµ ρ = 1 σ 1 qµ R ρl A = L Aqµ Sice the area that the curret flows through shriks as we icrease the bias, or drai bias, the resistace will icrease. Thus, our device has a resistace that varies with our applied biases. If we ow use both the ad the drai voltage, we fid that we should have curves that look like: I sd More egative bias V sd (This is because as we make the bias more egative, we will close (pich) the chael at lower drai biases.) Now let us derive the curret i a semi-aalytical maer Quatitative Aalysis of the J-FET Let us start with our picture of the system. UTD EE3301 otes part 3 Page 132of (57+126) Last update 7:55 PM 11/27/02

7 depletio source (with metallic cotact) p + drai (with metallic cotact) L 2a V sg p + V sd Now we eed to blow this picture up ad look at thigs i detail L y z (0,0,0) source p + p + w(x) 2a drai x Here we have added a coordiate system with x alog the chael ad y i the directio betwee the two parts of the. (Thus z is out of the page via right-had rule.) To get at a aalytic solutio we eed to make a series of basic assumptios. (These are really just simplifyig assumptios.) They are: 1) The juctios are p + - step juctios. (Keep it simple!) 2) The materials are uiformly doped. (Keep it simple!) 3) The device is symmetric about the x-axis, with the p + material a costat distace a from the axis. (Keep it simple!) 4) The top ad bottom voltages are the same. (Oe does ot eed to have this but it makes aalysis tough exactly what we do ot wat right ow.) 5) Curret flow is via majority carriers ad it is cofied to the o-depleted regios of the device. (Except whe pich occurs!) 6) Curret flow is from the drai to source oly. (- or the -x directio but ot i the y or z directios!) 7) The voltage drop from x = 0 to the source ad from x = L to the drai is egligible. (This meas that the eds do ot play a large role i the operatio of the device.) 8) L>>a 9) The voltage alog the device is simply a fuctio of the positio x. Thus V=V(x). 10) The depleted width, w, is set by the local voltage ad thus is oly a fuctio of the positio x. => w = w(x). 11) The depleted width ca grow to a maximum of a. (This meas that the depleted regios caot overlap.) 12) Breakdow does ot occur hece we are igorig the fact that our device ca become massively o-liear. UTD EE3301 otes part 3 Page 133of (57+126) Last update 7:55 PM 11/27/02

8 For coditios i which we do ot have pich-off, the curret desity is give by: J = J = J x x ˆ = qµ E + qd Withi the chael, the electro desity is approximately uiform ad thus the diffusio term of the curret desity is approximately zero. (This is ot ulike flowig curret though a small piece of material with o ijected charges.) Thus J x qµ E x qµ N D E x = qµ N D x Vx () ( ) Now the total curret is just the curret desity itegrated over the chael area: I x = ( a w( x ) Z dy 0 dz[ qµ N D ( x Vx () ( a w() x) 0 )] Z [ ( )] 0 0 ( a w( x ) = ( a w() x) dy zqµ N D x Vx () ( a w( x ) = ( a w() x) dy[ Z 0 qµ N D ( x Vx ())] ( a w( x ) = 2 dy Z 0 qµ N D x Vx () by symmetry! 0 [ ( )] [( ())Z 0 qµ N D x Vx ()] = 2 a wx I D where I D is the total curret through the device. (Note that the curret is i the egative x directio as make sese, we have electros flowig i the positive x directio!) Now we eed to ote that the curret through the device must be a costat we are ot buildig up charge i the device. We ca set I D = a costat ad try to solve our differetial equatio or we ca ote that as I D is a costat, itegratig alog the legth of the chael is equivalet to multiplyig it by the chael legth. Thus L I D L = 0 I D dx L = 2[ ( a wx ())Z 0 qµ N D x Vx () 0 ]dx VL ( )=V = D 2[ ( a wx ())Z 0 qµ N D ]dv 0 V [ ] 1 wv D = 2Z 0 qµ an D I D = 2Z 0qµ an D L [ ] 0 V D 0 ( ) a ( ) dv 1 wv dv a Now we eed to fid the depletio width as a fuctio of the voltage but we kow this from our study of p- juctios UTD EE3301 otes part 3 Page 134of (57+126) Last update 7:55 PM 11/27/02

9 wv ( )= x 0 w juctio = x 0 + x p0 = 2ε V bi v 1/2 ( A)N ( A + N D ) qn A N D ( ) 2ε V bi v 1/2 A qn D ( ) = 2ε V bi ( V G Vx ()) 1/2 qn D Further the maximum width will occur whe we reach pich-off voltage. a = 2ε V 1/2 ( bi V p ) qn D ( ) 1/2 wv ( ) V = bi V G + Vx () a ( V bi V p ) Here, V p is the local voltage differece (i.e. the voltage at some x) that is required to cause a pich at that locatio. It ca also be described as the voltage at which pich occurs for V G = 0 or the voltage at which pich occurs for V d = 0. These are all equivalet defiitios. Pluggig the above equatio ito the itegral we fid that G I D = 2Z [ 0 qµ an D] L VD 2 3 V bi V p for V Dsat > V D > 0 ad V p < V G < 0 ( ) V D + V bi V G V bi V p 3/2 V bi V G V bi V p Above saturatio e.g. pich-off we eed to replace all of the V D s with V Dsat s. At this poit, we eed to figure out what the saturatio voltage is. Saturatio is the poit at which pichoff first occurs. We kow that this will happe at the ed earest the drai. Further we kow that this will happe whe the depletio width is equal to a. Thus will eed to set the depletio width to a ad determie the voltage from that. 3/2 UTD EE3301 otes part 3 Page 135of (57+126) Last update 7:55 PM 11/27/02

10 V 64 7 D 48 2ε V bi V G + Vx= ( L) wv ( )= qn D = a = 2ε V 1/2 ( bi V p ) qn D V } Dsat ( V bi V p )= V bi V G + VL ( ) V Dsat = V G V p Now we ca plug this i for the drai voltage, gettig the saturatio curret, [ ] I Dsat = 2Z 0qµ an D L G 0 1/2 V G V p 2 3 V bi V p ( ) V G V p + V bi V G V bi V p = 2Z [ 0qµ an D ] L VG Vp 2 ( 3 V bi V p )1 V 3/2 bi V G V bi V p for V D > V Dsat > 0 ad V p < V G < 0 3/2 V bi V G V bi V p 3/2 Compariso betwee this ad experimetal data shows that our aalytical model does a reasoable job of predictig the experimetal data. (Improvemets ca be made to the model by improvig some our assumptios. For example assumptio 7 is clearly ot accurate. Removig the assumptio improves the agreemet betwee the model results ad the experimetal data.) Oe problem with the above equatio is that it is tough to remember. Further, we geerally do ot have the desig characteristics of the device whe we pull it out of the box. However, there is a useful approximatio that is relatively easy to remember that gives a reasoable value for I Dsat. That equatio is: UTD EE3301 otes part 3 Page 136of (57+126) Last update 7:55 PM 11/27/02

11 I Dsat = I D0 1 V G V p 2 [ I D0 = I Dsat VG =0 = 2Z 0qµ an D ] V L p 2 3/2 3 V V ( bi V p )1 bi V bi V p Yes, mathematically it does ot look the same, but it does give a reasoable approximatio ad it is easier to remember. Small ac sigals o J-FETs At this poit it is time to look at small ac sigals o our J-FET. (This is followig our typical patter qualitative assessmet of dc I-V traces, a quatitative assessmet of dc I-V traces, ad the a quatitative assessmet of small ac I-V traces.) To do this, we eed to look at how we use the device. source drai drai source I geeral, we put our sigal i o the lie ad pull our sigal out o the drai lie leavig the source as our effective groud (ot ulike we have doe i our aalysis above). For low frequecies, the curret that flows betwee the ad the source is very low. This is because we have a reversed biased diode. Thus the to source acts like a ope circuit. The curret betwee the drai ad the source is set by the coductace, g, betwee the source ad the drai. Additioally the voltage will cotrol chage the coductace. Let g d be the coductace at zero voltage. The we get a additioal coductace, g m, that is set by the voltage. source drai g i d d source source v g s g m v g g d v d s v d Now let us go high frequecy. Here, the coects to both the drai ad the source as if there were capacitors betwee the termials. Thus we get drai g c gd i d d source source v g s c gs g m v g g d v d s v d UTD EE3301 otes part 3 Page 137of (57+126) Last update 7:55 PM 11/27/02

12 We ca ow use stadard circuit aalysis to arrive at our curret ad voltage relatioships. The total drai curret is give by the sum of the dc ad ac currets. Thus, dc drai ac drai dc ac bias bias bias bias } } } } ac curret } I D V D + vd,vg + vg = I D ( V D,V G )+ i D i D = I D ( V D + v D,V G + v G ) I D ( V D,V G ) At this poit, we eed to uderstad that the total curret is simply a small sigal variatio from the dc curret. Thus, we ca use a Taylor expasio of the total curret to arrive at the approximate total curret. I I D ( V D + v D,V G + v G ) I D ( V D,V G )+ v D I D + v D V G D v D =0 V G v D =cost v G =cost v G =0 I i D v D I D + v D V D v D =0 G V G v D =cost v G =cost v G =0 = v D g d + v G g m g d = I D V D v D =0 v G =cost g m = I D V G v D =cost v G =0 We ca ow differetiate our drai curret to get +... Below pich-off g d = G 0 1 V 1/2 D + V bi V G V bi V p 1/2 V g m = G D + V bi V G 0 V bi V G V bi V p V bi V p 1/2 Above pich-off g d = 0 g m = G 0 1 V bi V G V bi V p 1/2 MESFETs MESFETs are MEtal Semicoductor FETs. These are extremely fast J-FETs. The Major chages are: UTD EE3301 otes part 3 Page 138of (57+126) Last update 7:55 PM 11/27/02

13 1) The is a Schottky diode. (Usually a metal cotact directly o the chael semicoductor.) 2) Drai ad Sources are Ohmic cotacts 3) No diffusio required => ca be very small ad very fast (I commercial applicatios, most MESFETs are made from GaAs.) Isulated Gate Field Effect Trasistors IGFETs. Isulated FETs look somewhat similar to J-FETs except there is a replacemet of the heavily doped semicoductor with a thi layer of dielectric material betwee the metal pad ad the chael. source E drai Isulator (ofte SiO 2 ) chael Depletio Regio p bulk We will fid that the width of the chael is set by the voltage the larger the voltage, the wider the chael. This is exactly the opposite to what we saw with J-FETs. IGFETs come i a few differet flavors: MOSFET Metal Oxide Semicoductor FET The is metal (or heavily doped poly-si) the dielectric is SiO 2, ad the rest of the device is Si. MISFET Metal Isulator Semicoductor FET The is metal (or heavily doped poly-si) the dielectric is somethig besides SiO 2, ad/or the rest of the device is somethig besides Si. NOTE THAT MOSFET IS A SPECIAL VERSION OF MISFET CMOS Complimetary MOS FETs This device cosists of two MOSFETs oe p-chael ad oe -chael The operatio of each of these revolves aroud what happes i the regio. There are two thigs that we ca quickly ote: 1) There is o dc curret flow from the. (Because of the isulator I reality, there is always some leakage curret, just ot much.) 2) The regio betwee the ad the substrate/bulk acts like a capacitor. UTD EE3301 otes part 3 Page 139of (57+126) Last update 7:55 PM 11/27/02

14 Give this simple descriptio, we ca begi to develop a picture of how these devices work. We have three eergy diagrams, oe each for the metal, dielectric ad semicoductor. Before we draw them, we are goig to make a few simplifyig assumptios. 1) We will assume, for simplicity, that the work fuctio for the metal, dielectric ad the semicoductor are the same. 2) That there are o charges i the oxide or at the iterfaces betwee the materials. Thus, we fid Eergy E Vac qχ S qχ D qφ S qφ M qφ D E Ci E cp E FM E i,f E ip E Fp E vp metal dielectric E Vi p-type Positio We ow will put them together to get: Eergy E Vac qφ' qχ' E Ci E FM metal dielectric p-type Positio Note that we have ow defied a ew work fuctio ad a ew χ based o the level of the coductio bad of the isulator. Now what happes whe the device is biased? UTD EE3301 otes part 3 Page 140of (57+126) Last update 7:55 PM 11/27/02

15 Ca we decide what the eergy levels will look like? 1) Let us assume that the bias applied to the metal is egative, thus V A < 0. Thus we would assume that the Fermi eergy of the metal will be above that for the semicoductor. 2) There will be o potetial variatio i the metal e.g. o electric field iside the metal ad hece the Fermi level of the metal will be costat. 3) As there is o charge iside the dielectric, the electric field iside the dielectric will be a costat. This meas that the potetial iside the dielectric must chage i a liear fashio. Mathematically E = ρ = 0 ε 0 E = cost = φ φ()= x φ 0 x 4) Fially, the gap betwee the coductio bad of the isulator ad the coductio bad of the semicoductor must remai costat. So we expect a picture that looks like UTD EE3301 otes part 3 Page 141of (57+126) Last update 7:55 PM 11/27/02

16 Eergy qφ' E=-qdV/dx E Ci E FM qχ' qv A E FS metal dielectric p-type Positio, x (We are ow elimiatig all o-useful eergy levels) What does this look like i terms of charge carriers? We kow that whe we have a structure like this o the semicoductor side, we are accumulatig or removig (depletig) the majority charge carriers. I this particular case, we will have additioal holes right ear the semi-dielectric boudary. (This is because our majority carriers are holes ad because the holes will be at a lower eergy at the boudary.) Thus, we are ACCUMULATING holes at the edge. Because the electric field caot peetrate ito the metal, we must have a equal but opposite amout of chage build up at the metal- dielectric boudary. Thus, we get a charge distributio that looks like: P-type ACCUMULATION, V A < 0. (For -type accumulatio is for V A > 0.) E=-qdV/dx Eergy qφ' E Ci E FM qχ' qv A E FS metal dielectric p-type Q(x) holes Positio, x electros P-type small depletio, V A > 0. (For -type small depletio is for V A < 0.) UTD EE3301 otes part 3 Page 142of (57+126) Last update 7:55 PM 11/27/02

17 Eergy qφ' E=-qdV/dx E Ci qχ' E FS E FM qv A p-type metal dielectric Q(x) holes acceptors Positio, x P-type iversio oset, V A ~ V T. (For -type accumulatio is for V A ~ V T.) E=-qdV/dx qχ' Eergy E Ci E FS qφ' E FM qv A p-type metal dielectric Q(x) holes acceptors Positio, x electros P-type Iversio, V A > V T. (For -type iversio is for V A < V T.) UTD EE3301 otes part 3 Page 143of (57+126) Last update 7:55 PM 11/27/02

18 E=-qdV/dx qχ' Eergy E Ci E FS qφ' E FM qv A p-type metal dielectric Q(x) holes acceptors Positio, x electros We have draw picture of what is goig o but ca we show the same thig usig mathematics? The differece i the pictures has to do with the locatio of the itrisic eergy relative to the locatio of the Fermi eergy. As we push the bias higher, the itrisic eergy siks lower, util it drops below the Fermi eergy at the oxide-si iterface (or dielectric-semicoductor iterface). Whe this happe, the semicoductor begis to act like it is -type. Hece we have coverted a p-type material ito a -type at least right ext to the isulator. Let us defie three more eergy levels. The first will be the eergy betwee the itrisic eergy ad the Fermi eergy, qφ F. The secod will be the amout of bad bedig that occurs i the semicoductor as a fuctio of positio, qφ(x). The fial eergy is the total amout of bedig at the iterface or surface, qφ s. Mathematically this is: qφ F =E i ( bulk) E F qφ s =E i ( bulk) E i ( surface) qφ()=e x i ( bulk) E i () x A picture looks like: UTD EE3301 otes part 3 Page 144of (57+126) Last update 7:55 PM 11/27/02

19 qφ s qφ(x) qφ F E is E FS p-type Note that φ s is differet tha the semicoductor work fuctio Φ s. We kow that iversio will start whe the itrisic eergy drops below the Fermi eergy. Thus we reach the threshold of iversio whe φ s φ F Before φ s is greater tha φ F, we are i depletio mode. Oce φ s is at least equal to φ F, we are begiig to build up a supply of free electros at the oxide-si iterface. If we cotiue to icrease our exteral bias, evetually we will reach a poit at which our iterface material (or chael) is as -type as we had origially doped it to be p-type. This is kow as Strog iversio. Mathematically, this is whe the shift i the itrisic eergy is twice the differece betwee the Fermi eergy ad the itrisic eergy i the Bulk or: φ s 2φ F Puttig this together with our charge carrier desities, we fid: ( )/kt x ()= i e E F E i px ( = i e E F E i ( x) )/kt = i e( qφ F +qφ() x )/kt but 0 = i e( qφ F)/kT = i e( E F E i)/kt = 0 e ( qφ( x) )/kt ( ())/kt ()= i e qφ F qφ x = p 0 e ( qφ( x) )/kt Note that x ()px ()= i 2 Now we have ad p versus φ(x). What is φ(x)? UTD EE3301 otes part 3 Page 145of (57+126) Last update 7:55 PM 11/27/02

20 To uderstad this, let us go back to our picture. E=-qdV/dx Eergy qv i qχ' E FS qφ' E FM qv A p-type metal dielectric Q(x) holes acceptors Positio, x electros First, the charge that is built up o the metal side is i a very thi regio. It is so thi that we will assume that it is effectively a delta fuctio distributio for its width. Likewise the free charge carriers (majority or miority) that we build up o the semicoductor side are also i a thi regio, typically less tha 100 Å wide. These we ca also assume are a delta fuctio distributio. Fially, ay boud charges that are built up o the semicoductor side must be over a fairly wide regio. The width of that regio is give by a equatio that is similar to our juctio width from our study of p- juctios. However, oce iversio begis to happe, the width of the depletio regio does ot grow sigificatly. This ca be uderstood i the followig maer. The electric field will exted oly as far as required to balace the charge that builds up o the opposite side of the isulator. As we have free charge carriers ow o the semicoductor side, they will move i the directio required by a electric field. Thus, they will serve to shorte the distace that the electric field would ormally peetrate ito the semicoductor material i a p- juctio. The fudametal equatio is: Poisso s Equatio: UTD EE3301 otes part 3 Page 146of (57+126) Last update 7:55 PM 11/27/02

21 E = ρ() x ε r ε φ()= x xφ() x we are assumig oly a sigle dimesio = ρ() x ε r ε 0 Durig accumulatio or depletio, the charge build up is primarily o the surface of the metal ad that of the semicoductor. Thus the electric field is i the oxide is approximately a costat ad is give by E()= x surface charge o metal } ρ m ε r ε 0 V is ()= x ρ m x + cost we will pick the costat later to be φ ε r ε s 0 V is ()= x ρ mx +φ ε r ε s 0 This ca be obtaied by itegratig Poisso s equatio from just iside to metal to just iside the dielectric. I the metal, the electric field is zero. I additio, the oly charge i the regio is the surface charge a delta fuctio. Thus, we get the above terms. Durig depletio, the ukow electric field is that i the semicoductor. That ca be foud agai from Poisso s equatio x E()= x charge i semi } ρ s ε r ε 0 E() x qn A ( W x) ε r ε 0 qn A ε r ε 0 assumes p - type material φ qn A ( W x) 2 2ε r ε 0 where W is the width ad the poit at which the electric field goes to zero i the semicoductor. We ca get the width by otig that the itrisic eergy has shifted φ s at the iterface, x = 0. (Note that this just assumed groud to be the bulk semicoductor.) Thus, φ S qn A 2ε r ε 0 W 2 W = 2ε rε 0 φ S qn A UTD EE3301 otes part 3 Page 147of (57+126) Last update 7:55 PM 11/27/02

22 The widest this will become is the width at which a sigificat umber of free electros begi to accumulate at the semi-isulator iterface. This occurs approximately whe we reach the iversiodepletio trasitio or threshold poit, φ s = 2φ F. Replacig φ s i the above equatio, we get the approximate maximum width kow as the threshold width. W T = 4ε rε 0 φ F qn A Gate Voltage relatioship: Now we kow that we are applyig a total voltage across the system that is simply the sum of the voltage shift across the oxide plus the voltage shift across the semicoductor, which is simply the voltage. Thus, V G = V is + V Semi = ρ mx 0 + φ ε r ε s 0 Now we do ot kow what the width of the oxide, x 0, is so that we caot determie which part belog to the semicoductor ad which part belogs to the oxide. (However, oce we have built a device, x 0 is a costat.) There is however, oe more equatio that we ca use. That equatio relates the electric field stregth across a boudary to the charge desity o the boudary ( ε rs ε 0 E s ormal ε riε 0 E i ormal)= Q si where Q si is the charge at the semicoductor isulator iterface. Assumig that this is zero, we get ε rs E s ormal = ε rie i ormal From above, the electric field i the semicoductor at the iterface is: ( ) E s qn A W ε rs ε 0 so E i = ε rs E ε s qn A ( W) ri ε ri ε 0 V is = ε rs ε ri x 0 E s V G = V is + V Semi = ε rs ε ri x 0 E s +φ s If we ow assume that the free carriers o the semicoductor side are delta fuctio, the UTD EE3301 otes part 3 Page 148of (57+126) Last update 7:55 PM 11/27/02

23 x E()= x charge i } semi ρ s ε r ε 0 E() x qn A ( W x) ε r ε 0 φ qn A ( W x) 2 2ε r ε 0 qn A ε r ε 0 assumes p - type material E() x qn A ( W x); W = 2ε rsε 0 φ S ε rs ε 0 qn A E s qn A ε rs ε 0 2ε rs ε 0 φ S 0 qn A E s 2qN Aφ S ε rs ε 0 This equatio provides a reasoable approximatio for (0 φ s 2φ F ) ad ca be plugged ito our equatio above, to get, V G = V is + V Semi = ε rs ε ri x 0 E s +φ s ε rs ε ri x 0 2qN A φ S ε rs ε 0 + φ s If we remember that we reach threshold (effective device tur-o) at φ s = 2φ F the the threshold voltage is simply the voltage at which tur-o occurs or V T ε rs ε ri x 0 4qN A φ F ε rs ε 0 + 2φ F UTD EE3301 otes part 3 Page 149of (57+126) Last update 7:55 PM 11/27/02

24 Curret i IGFETS Now we really eed to kow what the curret will be like i our device. Let us look at a picture of the System s grd g d +V g +V D p Whe there is o bias, there is o curret chael ad hece o curret. Therefore the cotrols the output curret just like i a JFET except the higher the voltage the WIDER the chael ad hece the higher the curret. Also, like a JFET, if V D becomes too large, the curret ca be piched off. This ca be see i the followig figure. s grd g V g =4V d +V D =5V 4V 0V 1V 2V 3V 4V 5V p We see i this case, the is biased at 4 V but the drai voltage has pulled the p-type material up to 5 V. Uder such a situatio, the voltage differece is ot large eough ad thus we will ot have ay free electros but rather we will have free holes ear the drai (i the p-material). (This is because the drai pulls it positive.) Hece we will ot reach iversio. From this, we would expect that the curret voltage traces look like: UTD EE3301 otes part 3 Page 150of (57+126) Last update 7:55 PM 11/27/02

25 I D pich off V g =5V V g =4V V g =3V V g =2V V D I geeral, the device must have some miimum voltage to coduct. Typically, it is a slightly egative voltage that will allow coductor but sometimes it takes a voltage above zero to get coductio. Also ote that the pich off voltage icreases with icreasig voltage just the opposite of what happes i a JFET. Capacitace i IGFETS I additio to the curret flow we will also briefly cosider the capacitace of a ideal MOS device. (This is a simplified versio of reality. We will retur to the cocept later, after we have developed a more realistic versio of the MOS capacitor.) I geeral, we ca cosider the MOS capacitor as the combiatio of two capacitors, the capacitor made up of the oxide layer ad the capacitor made up of the depletio layer. We kow that the voltage across the system is simply the voltage across the oxide plus the voltage across the semicoductor. Thus, V G = V is + V Semi Now if we were to just cosider the sectio across the oxide, we kow that V is = Q si C i where Q si ad the C i are the free charge at the semicoductor-isulator iterface ad isulator capacitace per uit area. We kow from a umber of other subjects that C i ε riε 0 x 0 We kow from our discussio of p- juctios, that the depletio regio ca also have a capacitace associated with it. That is give by C s = dq s dv s = dq s dφ s ε rsε 0 W. Where agai our values, C ad Q, are per uit area. UTD EE3301 otes part 3 Page 151of (57+126) Last update 7:55 PM 11/27/02

26 Graphically the system that we are describig looks like: +V g C i C s p Thus we have a series of capacitors. Combiig these together, we get the capacitace of the whole structure. C mos = C sc i C s + C i ε rs ε 0 ε ri ε 0 W x 0 ε rs ε 0 W + ε riε 0 x 0 ε rs ε ri ε 0 W x = 0 ε rs x 0 +ε ri W Wx 0 ε = rs ε ri ε 0 ε rs x 0 +ε ri W. Whe the depletio regio is very arrow, i.e. very little applied voltage, the the total capacitace is primarily due to the capacitace i the depletio regio. Whe the depletio regio is wide, i.e. either strog accumulatio or strog iversio, the total capacitace is primarily due to the capacitace o the isulator. Thus we would expect that the capacitace as a fuctio of voltage looks like: UTD EE3301 otes part 3 Page 152of (57+126) Last update 7:55 PM 11/27/02

27 C mos 0 V g (Note that the C-V curve is ot ecessarily symmetric ad is typically ot aroud zero bias. If we ow plug i our oxide capacitace ito out total voltage term, we fid V G = V is + V Semi = Q si C i + V Semi Threshold ad hece large-scale coductio will occur whe the voltage drop across the semicoductor is twice φ F. So V T = Q si C i + 2φ F Real devices Real devices very i a umber of ways from the assumptios we made whe we first described a IGFET. Notably, we assumed that the work fuctios of the metal, semicoductor ad isulators were idetical. (Whe o exteral bias is applied, this situatio is kow as FLAT BAND.) The reality of the situatio is that typically the work fuctio of the semicoductor is ofte larger tha that for the metal. (Si is a example of this.) Additioally, the work fuctio for the semicoductor ofte is a fuctio of the dopat cocetratio. (Actually, I do kow of ay case i which the dopat type ad dopat cocetratio does ot ifluece the work fuctio of the semicoductor. Cotamiate materials will also ifluece the work fuctio.) Thus, we would expect that the eergy diagrams for a true MOS capacitor should look like: UTD EE3301 otes part 3 Page 153of (57+126) Last update 7:55 PM 11/27/02

28 Eergy E Vac qφ' qχ' E Ci E FM metal dielectric p-type Positio We kow that the Fermi eergy must alig if we do ot apply a exteral bias, further the eergy differece betwee the metal Fermi ad Oxide coductio bad must be the same as before we put them together. This also applies to the differece betwee the coductio bads of the oxide ad the semicoductor. Thus, we would expect a picture that looks somethig like: E vac Eergy E=-qdV/dx E Ci qχ' qφ' E FM p-type E FS metal dielectric Q(x) holes acceptors Positio, x We ote that because the work fuctio of both the metal ad semicoductor are spatially costats, the dielectric must have a shift i the potetial across it. This i tur gives rise to charge buildup o the metal surface (holes) ad a correspodig charge build up i the semicoductor - as a small depletio regio these will be either acceptors for p-type or excess electros for -type materials. (If the differece betwee the metal work fuctio ad the semicoductor work fuctio is large eough, we ca eve reach iversio but this is ot that commo.) UTD EE3301 otes part 3 Page 154of (57+126) Last update 7:55 PM 11/27/02

29 The importat distictio betwee what we were doig before ad ow, is the shift i the work fuctios. We give this shift a special symbol: Φ ms =Φ m Φ s Note that it is typically egative for may systems of iterest but ot all systems. Iterface traps ad oxide defects I additio to the mior fact that the work fuctios of various materials are ot equal, isulators also ca have charges trapped iside them (defects). Ofte, these come from some metal io (hece a positive charge) that is icorporated ito the dielectric durig the growth stage. (Oxide/itride layers are typically grow i a low-pressure chemical vapor depositio tool (thicker layers) or a plasma ehaced chemical vapor depositio tool (thier layers). While these tools are very clea compared to previous geeratios of processig tools, oe ca still get cotamiatio from the walls of the processig tool. - Uderstadig the mechaisms ivolved i this cotamiatio process is a area of sigificat research.) Additioally, because of the growth mechaisms, iterface traps ca be produced at the boudary betwee the Oxide ad the semicoductor. These are typically daglig bods that where broke durig growth of the oxide. (A Si atom is stripped from the surface to make SiO 2 leavig a hole i the bod structure.) Additioally ad ot talked about i the book iterface traps icrease as the amout of total (time itegrated) curret hece charge icreases. There is a reasoably wellquatified total charge, kow as the charge-to-breakdow at which the oxide fails. This is also a issue i processig of devices ad is the subject of a yearly coferece. The importat thig about these defects is that they add charge to the system, further shiftig the eergy levels away from our ideal flat bad coditio. The voltage shift is give by: V trap = Q trap C i which, based o the locatio of the charge, is a positive value. Thus our total voltage shift betwee the metal ad the bulk semicoductor is give by: Φ total = Φ ms + V trap = Φ m +Φ s + Q trap C i Now comes the questio of how we deal with these extra terms. If oe looks at the eergy diagram above, oe otes that we ca recover most of our flat bad diagram (except the costat Fermi eergy) by applyig a voltage to the that simply shifts the eergies i the semicoductor util we reach our flat bad coditio. This shift is obviously just the egative of Φ total. If we do that, the we have effectively the same system that we started this subject with ad hece we have all of our equatios. We defie the flat bad voltage as: V fb =Φ ms V trap =Φ m Φ s Q trap C i UTD EE3301 otes part 3 Page 155of (57+126) Last update 7:55 PM 11/27/02

30 Now our threshold voltage for iversio is shifted by the same amout ad thus: V T = Φ ms Q si Q trap + 2φ C i C F i Curret-voltage characteristics at the drai Now we are goig to try to look at the drai curret i a little detail. (Note that what we are doig is still a approximatio. There are better approximatios but they are more difficult to arrive at tha what we will do here.) The basic idea of a MOS FET is fairly simple: 1) V D is reversed biased 2) V G is biased to attract miority carriers to the oxide iterface. s grd g d +V g +V D e - e - e - p base grd Now, if the chael does ot exist, we get a device that looks like: UTD EE3301 otes part 3 Page 156of (57+126) Last update 7:55 PM 11/27/02

31 s grd g +V g =grd d +V D p base grd 1) We see that o matter how we bias the drai relative to the source, we always have a juctio that is reversed biased ad hece oly a small amout of curret ca peetrate. 2) If a chael does exist, the chael simply acts like a variable resistor. We kow that the curret voltage trace looks somethig like: I D 3 4 pich off V g >V T 2 1 V Dsat V D We have four importat situatios to look at i the above figure. They are labeled 1, 2, 3 ad 4. Startig with 1. This is uder the coditio that I DS = 0 because V DS = 0. Our picture looks like: UTD EE3301 otes part 3 Page 157of (57+126) Last update 7:55 PM 11/27/02

32 s grd g d +V g >V T +V D =0 chael depletio p base grd 1) Wide ope chael but o drai curret because o drai voltage. [Strictly speakig V g V T i all of these figures but M$ will ot let me use that without crashig o prit (for MacOS 9). It reads fie for Mac OSX but it does ot eve read the i Widows 2000.] s grd g d +V g >V T 0<V D <V Dsat chael depletio p base grd 2) Drai curret because drai voltage ot zero. Chael still ope to curret flow. Note that the chael width is beig costricted at the ed because the drai source voltage reduces the bulk voltage. UTD EE3301 otes part 3 Page 158of (57+126) Last update 7:55 PM 11/27/02

33 s grd g d +V g >V T V D =V Dsat chael depletio p base grd 3) Pich off occurs at this voltage. From ow o the electric field i the chael remais ~ costat because the drai voltage is dropped across the depletio regio. (This is the log chael approximatio. If the chael is short, the the electric field across the chael chages as the drai voltage icreases the iversio legth gets otably shorter but the voltage drop is the same. This is kow as the short chael effect.) s grd g d +V g >V T V D >V Dsat chael depletio p base grd 4) Here all additioal drai voltage get dropped across the depletio regio ad does ot have much impact o the source-drai curret. At this poit, we eed to look at which equatios do we have. We kow that for a ideal MOSFET iversio occurs whe the voltage reaches threshold voltage UTD EE3301 otes part 3 Page 159of (57+126) Last update 7:55 PM 11/27/02

34 V T 2φ F + ε rs ε ri x 0 V T 2φ F ε rs ε ri x 0 4qN A φ F ε rs ε 0 <= -chael devices (as draw above) 4qN A ( φ F ) ε rs ε 0 <= p-chael devices (exact opposite to what is draw above). Clearly whe this occurs, the charge carriers, electros for the -chael, holes for the p-chael, move i the chael ear the semicoductor-isulator iterface. Additioally, the electric field i that area is such that it tries to pull the charge carriers closer to the iterface. Remember that we have the field due to the drai ad the field due to the! This meas that we will have a path that looks like: s grd g d +V g >V T 0<V D <V Dsat e y p x base grd If the electro path were etirely i the Si, the we would already have model of its movemet, via its mobility. Remember: µ= v drift E The mobility is determied by the umbers ad types of collisios i the bulk lattice. Now we also have collisios with the iterface regio, which we kow has more damage sites tha the regular lattice. (This is due to how the device is made ad due to the fact that the semi ad isulators rarely (ever) match exactly causig stresses ad strais. Therefore we expect that the mobility of the electros will be lower tha i the bulk material. I fact, we expect that the mobility is a fuctio of positio i the chael. Thus, µ=>µ ( x, y) Why µ ( x, )? a) The mobility ear the surface is less because of collisios with the iterface. Why µ,y ( )? b) The chael width arrows as we move from source to drai meaig i geeral that the electros sped more time ear the surface as we move from source to drai. c) The chael dopig ca charge across the chael ad ofte is setup to do so. d) The electric field varies across the chael (This is more importat i short chaels) UTD EE3301 otes part 3 Page 160of (57+126) Last update 7:55 PM 11/27/02

35 Because of this, we eed to defie a ew mobility, kow as the chael mobility or effective mobility. It is simply the average mobility/area of all electros (or holes) i the chael x c () y µ ( x,y)x,y ( )dx µ = µ 0 x c () y x,y ( )dx 0 where x c (y) is the width of the chael at y. Now the deomiator of the above equatio is essetially the umber of chage carriers/area i the chael. x Q ()= q y c () y ( x,y)dx 0 so we ca rewrite this as x Q ()µ y = q c () y µ ( x, y)x,y ( )dx 0 Now we have the mobility as a fuctio of positio alog the legth of the chael. If we thik about thigs for a miute, we will realize that the chael is ever very wide, ad i geeral is approximately a costat. (This is at least true for log chaels.) Thus we ca make a approximatio that the mobility is a costat alog the chael. However, we do kow that the mobility is a fuctio of the applied voltage relative to the threshold voltage. A empirical fit, based o experimetal measuremets gives 0 V gs < V T µ µ 0 1 +θ( V gs V T ) V gs V T where µ 0 is the mobility at V gs = V T, ad θ is a voltage fittig parameter. Now the curret desity i the chael is J = J = J yˆ y = qµ E y + qd dφ() y dy 0 } } = qµ E y + qd dφ() y = qµ dy The total source-drai curret is the itegral over the area of the chael I DS = JdA () x =+ c () y Z dφ y qµ 0 0 dy dxdz () x =+Z c () y dφ y qµ 0 dy dx If we ow assume that the electric field does ot chage i the chael, the we ca pull it out of the itegral. (Agai, we ote that this really oly works for log chaels.) UTD EE3301 otes part 3 Page 161of (57+126) Last update 7:55 PM 11/27/02

36 () I DS =+Zq dφ y dy () = Z dφ y dy () µ dx x c y 0 Q ()µ y We ca get rid of our y-depedece by otig that the total curret must be a costat alog the juctio. The if we itegrate from the source to the drai, we should have I DS L. (We have used this trick before!) L I DS dy = I 0 DS L L = Z dφ() y 0 dy Q ()µ y dy V DS ()µ dφ = ZQ φ 0 Now all that we eed it the local charge as a fuctio of local voltage. We kow x Q ()= q y c () y ( x,y)dx 0 If we thik about where the charges are located at, the charge o the must equal the charge o the semicoductor-isulator iterface (e.g. the chael) plus the depletio charge. Q mi = Q chael Q depletio If our voltage is above the threshold the ay chage i the voltage will give rise to chages oly at the metal-isulator ad semi-isulator iterfaces. Q mi = Q chael We kow what this charge is from the capacitace across the isulator Q chael = C i V G ( ) Q chael = C i V G V T Q chael = ε riε 0 x 0 ( V G V T ) But this is for a MOS capacitor. We kow that the voltage will vary as we move across the device. The amout that it reduces is φ(y). Thus, we arrive at: Q chael = ε riε 0 ( V x G φ() y ) V T ) 0 we ca ow plug this ito our equatio for the curret to arrive at: UTD EE3301 otes part 3 Page 162of (57+126) Last update 7:55 PM 11/27/02

37 L 0 I DS dy = I DS L V DS 0 = ZQ φ ()µ dφ V = Z ε DS riε 0 0 I DS Zµ C i L x 0 ( V G φ() y ) V T ) µ dφ ( V G V T )V DS V 2 DS for V 2 G V T, 0 V DS V Dsat So where does pich off occur? Whe Q(L) = 0 From above Q chael ( L)= ε riε 0 x 0 ε riε 0 x 0 = 0 ( ) ( ) ( V G φ( L) ) V T ( V G V DS ) V T ) V Dsat = V G V T Pluggig this ito the above equatio, we fid the saturatio curret I DS Zµ C i [( V 2L G V T )] 2 for V G V T, 0 V DS V Dsat Note that the saturatio curret does ot deped o the drai voltage but does deped o the voltage less the threshold i a square-law term. Like most thigs we have doe i this class, we have used approximatios to arrive at simple models of our devices. This meas that the results are subject to errors ad hece ca be improved o. For example, if we had icluded the fact that the depletio regio varies with locatio across the device, we would have arrived at a better model of the curret-voltage relatioship. This model is kow as the bulk-charge theory. This distictio gives Q chael = ε riε 0 ( V G V T φ() y )+ qn A wy I DS Zµ C i L [ ] () w T x 0 ( V G V T )V DS V 2 DS 2 4 qn A w T φ 3 C F 1 + V 3/2 DS 1+ 3V DS i 2φ F 4φ F V G V T + 1+ qn A w 2 1/2 T 1 + qn A w T 2φ F 4C i φ F 4C i φ F V Dsat = ( V G V T ) qn A w T C i These are cosiderable harder to deal with but more accurate. UTD EE3301 otes part 3 Page 163of (57+126) Last update 7:55 PM 11/27/02

38 Small ac sigals o MOSFETs At this poit it is time to look at small ac sigals o our MOSFET. (This is followig our typical patter qualitative assessmet of dc I-V traces, a quatitative assessmet of dc I-V traces, ad the a quatitative assessmet of small ac I-V traces.) To do this, we eed to look at how we use the device. source drai drai base base/source base/source I geeral, we put our sigal i o the lie ad pull our sigal out o the drai lie leavig the source/base as our effective groud (ot ulike we have doe i our aalysis above). For low frequecies, the curret that flows betwee the ad the source is very low. This is because we have a reversed biased diode. Thus the to source acts like a ope circuit. The curret betwee the drai ad the source is set by the coductace, g, betwee the source ad the drai. Additioally the voltage will cotrol chage the coductace. Let g d be the coductace at zero voltage. The we get a additioal coductace, g m, that is set by the voltage. drai g i d d source source v g s g m v g g d v d s v d g d I DS chael coductace V DS VG =cost g m I DS V G V DS =cost trascoductace Now let us go high frequecy. Here, the coects to both the drai ad the source as if there were capacitors betwee the termials. Thus we get drai g c gd i d d source source v g s c gs g m v g g d v d s v d UTD EE3301 otes part 3 Page 164of (57+126) Last update 7:55 PM 11/27/02

39 We ca ow use stadard circuit aalysis to arrive at our curret ad voltage relatioships. However, this is exactly like what we foud for our JFET so we will ot repeat it. We ca however try to determie what the maximum operatioal frequecy of the device might be. We will defie the maximum frequecy as the frequecy at which the curret i is equal to the curret out. This meas that we have a ac short betwee source ad drai. Our circuit is ow g i i c gd i out d v g s c gs g m v g g d v d s v d Thus i i = ω( C gs + C gd )v g ω( C i A g )v g i out = g m v g i out i i =1 g m v g = ω( C i A g )v g = g m ( ) ω C i A g g ω max m ( C i A g ) = 1 Zµ C i L C i A { g =ZL ( V g V T ) from JFETs f max = 1 µ 2π L 2 V ( g V T ) This meas the faster we wat to operate, the shorter we eed the chael to be BJT Bipolar Juctio Trasistors This is the last topic of this class. UTD EE3301 otes part 3 Page 165of (57+126) Last update 7:55 PM 11/27/02

40 The Bipolar Juctio trasistor is a relatively simple device. I essece, oe takes a p + - juctio ad adds a p-type material o the other side of the material. (Oe ca also do this with a + -p juctio.) They look like: E C E p + p + p C B B Here E stads for emitter, C stads for collector ad B stads for base. This termiology will become clear shortly. To uderstad this device we eed to cosider (or rather remember) what happes with just a p- juctio. Reachig back ito the otes ad lookig at our diodes, we fid that: I = I 0 e qv A /kt 1 ( ) 2 D I 0 = q i A + D p where L = Dτ L N A L p N D We see that i the forward biased coditios, we get a expoetially icreasig curret. However, we see from our picture of a BJT that at least oe of the juctios is always reversed biased. Thus we really eed to examie what happes i the reversed bias coditios. Uder such a coditio, the curret is 2 D I = I 0 = q i A + D p L N A L p N D This meas that the curret is idepedet of the applied bias but it is depedet o the diffusio legth of the carriers ad hece the drift of electros/holes across the juctio. Sice these are the miority carriers, very few of them are aroud. So I 0 depeds mostly o the productio rate of the miority carriers ear the juctio. This last part is due the fact that the miority carriers really eed to be geerated withi a diffusio legth of the juctio for them to fall dow the potetial hill. (Some miority carriers will come from further away, while some miority carriers created ear the juctio will recombie before they fall dow the hill. O average, may of the miority carriers withi L will make it while those outside that legth do ot make it.) Our picture of the situatio was: UTD EE3301 otes part 3 Page 166of (57+126) Last update 7:55 PM 11/27/02

41 Eergy p-type E E cp E ip E Fp E c E vp q(v A +V bi ) E F E i E v -type Positio If some how we could place a source of miority carriers ear the juctio, we could the icrease the curret across the juctio. By ear, we mea that the miority carriers MUST BE WITHIN A DIFFUSION LENGTH for those additioal carriers to make a differece. electro source Eergy E cp p-type E E ip E Fp E c E vp q(v A +V bi ) E F E i -type E v hole source Positio Oe way to create this source of miority carriers is to put a secod juctio, ear our first juctio, through which we supply our required miority carriers. This is the ature of a BJT device. Let s ow examie a typical or stadard BJT. I the typical cofiguratio it is wired as follows: (We will look at oly p + --p devices right ow.) UTD EE3301 otes part 3 Page 167of (57+126) Last update 7:55 PM 11/27/02

42 E holes emitted holes collected C p + p I E R E B R C I C I B +V E +V C THIS IS WIRED CORRECTLY! - see the otes below (NOTE that we ca wire a BJT i a umber of differet ways. If you ca dream it, it has probably bee doe.) We see i this case that the emitter-base (E-B) juctio is forward biased while the collector-base (C-B) juctio is reversed biased. This meas that holes are ijected from the emitter ito the base. These holes are a miority carrier i the -type material. They ow available for trasfer across the reverse biased C-B juctio to the collector. We wat these holes to make it across the device so: a) Make the E-B juctio a p + - juctio so that we have a lot of holes ijected. b) Have the E-B juctio forward biased uder ormal operatio. c) Make the base regio very arrow, such that the width, W, is less tha L P. (Here W is the width of the o-depleted regio of the base material.) d) Strogly reverse bias the C-B juctio. Qualitatively what occurs is: UTD EE3301 otes part 3 Page 168of (57+126) Last update 7:55 PM 11/27/02