Metal Gate. Insulator Semiconductor

Transcription

1 MO Capacitor MO Metal- Oxide- emicoductor MO actually refers to Metal ilico Diide ilico Other material systems have similar MI structures formed by Metal Isulator emicoductor The capacitor itself forms the basis of digital logic circuits, ad DRAM storage uits (storig charge or ca simply supply a capacitace for a aalog itegrated circuit. It will also be the buildig block for the most commo trasistor produced the MO trasistor. The substrate is ormally take to be grouded ad the Gate electrode ca be biased with a voltage, G Metal Gate Isulator emicoductor

2 MO Capacitor Key assumptios: 1 Metal is a equipotetial regio. Oxide is a perfect isulator with zero curret flow. 3 Neither ide or ide-semicoductor iterface have charge ceters. 4 emicoductor is uiformly doped. 5 A ohmic cotact has bee established o the back side of the wafer. 6 Aalysis will be oe-dimesioal. 7 The semicoductor is thick eough to have a quasi-eutral regio (where electric field is zero ad all eergy bads are flat. 8 Certai eergy relatioships exist: Φ M Φ χ + (E C -E B (terms defied i ext few slides

3 MO Capacitor E O acuum Eergy Level. The miimum eergy a electro must have to free itself from the material. Φ M Work fuctio of the metal. This is the eergy differece from the fermi eergy (average eergy of a electro i the metal to the vacuum eergy level. Φ Work fuctio of the semicoductor. This is the eergy differece from the fermi eergy (average eergy of a electro i the semicoductor to the vacuum eergy level. Note that this eergy depeds o dopig sice E depeds o dopig χ Electro Affiity of the semicoductor. This is the eergy differece from the coductio bad miimum i the semicoductor to the vacuum eergy level. Note that this eergy does NOT deped o dopig (E C -E B Φ χ i the quasi-eutral regio where the bads are ot bet or are i flat bad

4 MO Capacitor The isulator is simply a very wide badgap, itrisically doped semicoductor characterized by a electro affiity, χ i. The semicoductor ca have a electric field ear the isulator that forces the eergy bads to bed ear the isulator-semicoductor iterface.

5 MO Capacitor ice the isulator prevets ay curret from flowig, whe we brig the materials together, the fermi-eergy must be flat. Likewise, if o charges are stored o the plates (metal ad semicoductor regios ear the isulator of the capacitor, the bads are ot bet i the isulator or semicoductor. Note the assumptio of a equipotetial surface i the metal simply states that a perfect coductor ca ot support ad electric field (electrostatics.

6 MO Capacitor Capacitor uder bias A positive voltage o the gate puts positive charge o the gate electrode. Gauss s law forces a equal egative charge to form ear the semicoductor-isulator iterface. Charge separated by a distace implies a electric field across the isulator.

7 Capacitor uder bias If G bias voltage applied to the gate (metal. or all G the ermi level i the each layer remais flat due to zero curret through the structure. The applied bias separates the ermi levels at the metal ad semicoductor eds by q G E (metal - E (semicoductor -q G If the semicoductor is grouded (fixed at ay costat potetial we ca call groud: metal side ermi level moves dowward if G > 0 metal side ermi level moves upward if G < 0 Applyig Poisso s equatio to the ide, sice there are o charges i the ide, deide ρ 0 Eide Cos ta t dx E dx Potetial varies liearly with x ide MO Capacitor ice the potetial varies liearly with x, so does the eergy bads

8 MO Capacitor Capacitor uder bias or a -type semicoductor. Whe G > 0 the metal fermi-eergy is lowered (E-q, the isulator has a electric field across it that termiates almost immediately i the ear perfectly coductig metal, but termiates over a fiite distace i the semicoductor of fiite resistivity. The charge model idicates that egative charge must be created i the semicoductor ear the iterface. This charge is i the form of electros. ice i exp[(e -E i / kt], the electro cocetratio i the semicoductor ear iterface icreases. This is called accumulatio

9 MO Capacitor Capacitor uder bias or a -type semicoductor. Whe G < 0 the metal fermi-eergy is raised (E-q, the isulator has a electric field across it that termiates almost immediately i the ear perfectly coductig metal, but termiates over a fiite distace i the semicoductor of fiite resistivity. The charge model idicates that positive charge must be created i the semicoductor ear the iterface. This charge is i the form of ioized doors. ice i exp[(e -E i / kt], the electro cocetratio i the semicoductor ear iterface decreases. This is called depletio.

10 MO Capacitor Capacitor uder bias or a -type semicoductor. or higher magitudes of bias ( G < 0 the fermi-eergy ear the iterface crosses-the itrisic eergy ad the type of material swaps from -type to p-type (oly locally ear the iterface. The charge model idicates that positive charge must be created i the semicoductor ear the iterface. This charge is i the form of ioized doors ad holes. Iversio cotiued o ext slide

11 MO Capacitor Capacitor uder bias Iversio Cotiued The hole cocetratio ear the iterface must equal the door cocetratio. Thus, p iterface N D p iterface i exp[(e i-interace -E / kt] i exp[(e E i-bulk / kt] This is called iversio. The oset of iversio occurs for a voltage called the threshold voltage T (ot thermal voltage Detailed calculatios takig ito accout the charge distributio as a fuctio of positio i the semicoductor idicates that iversio occurs whe, E i-interace -E i-bulk (E -E i-bulk

12 MO Capacitor Capacitor uder bias trog Iversio ( G < T or a -type semicoductor. or still higher magitudes of bias ( G < 0 the hole cocetratio cotiues to icrease resultig i a very high cocetratio of holes ear the iterface. This is kow as strog iversio.

13 MO Capacitor Capacitor uder bias for P-type material

14 MO Capacitor Capacitor uder bias ummary Iversio Depletio Accumulatio T 0 G N-type material Accumulatio Depletio Iversio 0 T G P-type material

15 MO Capacitor Quatitative olutio Let φ(x electrostatic potetial iside the semicoductor at a depth x (measured from the ide iterface φ ( x [ E E ( x ] ad 1 φ q alog with, φ 1 q 1 q i BULK [ E E ] i BULK [ E E ] i BULK i INTERACE i electrostatic potetial surface potetial P-type Example

16 MO Capacitor Quatitative olutio ice, p BULK e i ( E E ( E E i BULK kt N A ad BULK e i i BULK kt N D φ Thus, φ φ kt q kt q N A l i N D l i for a p - type semicoductor for a - type semicoductor at the depletio - ivertio trasitio poit, G T

17 MO Capacitor Quatitative olutio ice the MO-Capacitor is symmetric (equal charge o metal as is i the semicoductor ad has o charge i the ide, we ca solve for the electrostatic variables usig oly the semicoductor sectio of material. Thigs to ote: Charge due to accumulatio bias ad iversio bias results i a very arrow charge distributio ear the iterface. Charge due to depletio bias results i a wide depletio width, W

18 MO Capacitor Quatitative olutio ρ Oce agai, if we apply the Depletio Regio Apprimatio (eglect all charges but those due to ioized dopats ad assume p-type material, ( p + N N qn for (0 x W where W is the depletio width q D A A Ad from Poisso s equatio usig a boudary coditio that the electric field goes to zero at the depletio regio edge, de dx qn K ε A o E( x dφ dx qn K A ε o ( W x Ad fially, the electrostatic potetial ca be foud by itegratig usig a boudary coditio that the electrostatic potetial goes to zero at the depletio regio edge, φ qn A K ε o ( W x

19 MO Capacitor Quatitative olutio The depletio width, W, ca be foud by otig that φφ at x0 W K ε o qn A φ The depletio width at the iversio-depletio trasitio, W T, ca be foud by otig that φ φ W T K ε o qn A K ε kt q N o φ A l N i A NOTE: To obtai the equatios for -type substrates, we simply repeat the above procedure replacig N A with -N D

20 MO Capacitor Quatitative olutio How is the gate voltage G distributed throughout the structure? G φ +φ ide rom before, we said, (o drop i the metal de φ x where K ad K dφ Cos ta t dx ( x But, Gauss's Law states that the electric displacemet, D ε E must be cotiuous i the directio ormal to the iterface. Thus, E ide ide dx ρ 0 E emicoductor at the Iterface 0 ide E ide thickess ide dx E ide ide thickess K K ε ε o o K K E ide ide are the relative dielectric costats i the semicoductor ad the ide

21 Thus, φ ide K K MO Capacitor Quatitative olutio ( x ide thickess Eemicoductor at the Iterface Ad usig the previous expressios, G but E emicoductor at the Iterface G φ Thus, φ + usig + K K K K W ( x ide thickess K qn ε A o φ qn K E emicoductor at the Iterface ε ad A o ( W x qn A ( xide thickess φ for 0 φ φ K φ ε o E( x qn K A ε o at x 0 Relates the applied gate voltage to the surface potetial!

22 MO Capacitor Quatitative olutio But what about i iversio ad accumulatio? or iversio ad accumulatio we ca ot ivoke the depletio apprimatio due to a sigificat amout of charge ear the iterface due to sources other tha just ioized dopats (these charges are the electros ad holes. I iversio ad accumulatio, the vast majority of the gate voltage is dropped across the ide I iversio, the depletio width remais ~ costat Thus, φ ca ot be much less (greater tha 0 for p-type (-type Thus, φ ca ot be much greater (less tha φ for p-type (-type ee discussio cetered aroud figure i Pierret if iterested i more detail.

23 MO Trasistor Qualitative Descriptio low of curret from ource to Drai is cotrolled by the Gate voltage. Cotrol by the Gate voltage is achieved by modulatig the coductivity of the semicoductor regio just below the gate. This regio is kow as the chael

24 MO Trasistor Qualitative Descriptio -chael MO Trasistor p-chael MO Trasistor D + D - D D G + B + B G - B - B G - G Note: All voltages are show i their positive directio. Obviously, YX - XY for ay voltage GGate, DDrai, ource, BBody (substrate, but to avoid cofusio with substrate, B is used +

25 MO Trasistor Qualitative Descriptio Assume a -chael (receives it s ame from the type of chael preset whe curret is flowig device with its source ad substrate grouded (i. e., B 0. or ay value of D : whe G <0 (accumulatio, the source to drai path cosists of two back to back diodes. Oe of these diodes is always reverse biased regardless of the drai voltage polarity. P-type whe G < T (depletio, there is a deficit of electros ad holes makig the chael very highly resistive. > No Drai curret ca flow. High ρ due to Depletio

26 MO Trasistor Qualitative Descriptio Cosider ow the Iversio case: irst, D 0: whe G > T, a iduced - type regio, a iversio layer, forms i the chael ad electrically coects the source ad drai. Iversio layer (-type P-type

27 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: Whe D >0, the iduced - type regio allows curret to flow betwee the source ad drai. The iduced chael ast like a simple resistor. Thus, this curret, I D, depeds liearly o the Drai voltage D. This mode of operatio is called the liear or triode * regio. Iversio layer (-type P-type * Triode is a historical term from vacuum tube techology.

28 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: Drai curret verses drai voltage whe i the liear or triode * regio.

29 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: Whe D icreases a few teths of a volt (>0: The depletio regio ear the drai wides (N+ drai is positively biased I.e. reverse biased with respect to the substrate. The electro cocetratio i the iversio layer ear the drai decreases as they are sucked out by the Drai voltage. Chael coductace decreases resultig i a drop i the slope of the I D - D curve. Reduced electro cocetratio i the Iversio layer ear the drai P-type

30 Iversio case, G > T (cotiued: MO Trasistor Qualitative Descriptio Drai curret verses drai voltage for icreasig D (still i the liear or triode regio.

31 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: The iversio layer evetually vaishes ear the drai ed of the chael. This is called Pich-Off ad results i a lat I D - D curve

32 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: I D - D curve for the aturatio Regio The drai-source voltage, D, at which this occurs is called the saturatio voltage, sat while the curret is called the saturatio curret, I Dsat. I Dsat

33 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: or D > sat the chael legth, L, effectively chages by a value L. The regio of the chael, L is depleted ad thus, is high resistivity. Accordigly, almost all voltage icreases i D > sat are dropped across this portio of the chael. High electric fields i this regio act similarly to the collector-base juctio i a BJT i active mode, strippig or collectig carriers from the chael.

34 MO Trasistor Qualitative Descriptio Iversio case, G > T (cotiued: If L<<L, the voltage at the ed of the chael will be costat ( sat for all D > sat. I D will be costat. If L~L, the voltage dropped across the the chael ( AT varies greatly with D due to large modulatios i the electric field across the piched off regio ( E[ D - AT ]/[ L]. I this case, I D icreases slightly with D.

35 ially, MO Trasistor Qualitative Descriptio I D - D curves for various G : Dsat depeds o G

36 MO Trasistor I- Derivatio With our expressio relatig the Gate voltage to the surface potetial ad the fact that φ φ we ca determie the value of the threshold voltage T φ + ε C qn ε A ( φ (for - chael devices T where, C φ ε x ε C qn ε D ( φ (for p - chael devices is the ide capacitace per uit area Where we have made use of the use of the expressio, ε K ε o

37 MO Trasistor I- Derivatio Coordiate Defiitios for our NMO Trasistor xdepth ito the semicoductor from the ide iterface. ylegth alog the chael from the source cotact zwidth of the chael x c (y chael depth (varies alog the legth of the chael. (x,y electro cocetratio at poit (x,y µ (x,ythe mobility of the carriers at poit (x,y Device width is Z Chael Legth is L Assume a Log Chael device (for ow do ot worry about the chael legth modulatio effect

38 MO Trasistor I- Derivatio Cocept of Effective mobility The mobility of carriers ear the iterface is sigificatly lower tha carriers i the semicoductor bulk due to iterface scatterig. ice the electro cocetratio also varies with positio, the average mobility of electros i the chael, kow as the effective mobility, ca be calculated by a weighted average, [ ] ( 0 ( 0 ( 0 ( 0, (, ( ( / arg, ( (,, (, (, ( y x x x N y x x x N y x x x y x x x c c c c dx y x y x y Q q cm e ch dx y x q y Q defiig or dx y x dx y x y x µ µ µ µ Empirically ( are costats, 1 θ µ θ µ µ ad where o T G o +

39 MO Trasistor I- Derivatio Drai Curret-oltage Relatioship I the Liear Regio, G > T ad 0< D < dsat J N qµ E + qd N Neglectig the diffusio curret, ad recogizig the curret is oly i the y-directio, J N J Ny qµ E y qµ dφ dy

40 MO Trasistor I- Derivatio Drai Curret-oltage Relatioship I the Liear Regio, G > T ad 0< D < dsat D D D c c N D N D N L y y D N y x x x y x x x Ny Ny D d Q L Z I d Q Z L I d Q Z dy I dy d Q Z dx y x y x q dy d Z dx J Z dxdz J I φ φ φ φ φ φ φ µ φ µ φ µ φ µ µ φ ( 0 ( 0, (, ( To fid I D, we eed a expressio relatig φ ad Q N

41 MO Trasistor I- Derivatio Capacitor-Like Model for Q N Assumptios: Neglect all but the mobile iversio charge or the MOET, the charge i the semicoductor is a liear fuctio of positio alog the semicoductor side of the plate. Thus, φ varies from 0 to D ice C dq d, ource Drai Q N C MO Capacitor Oly voltages above threshold create iversio charge ( G T for G T Neglect the depletio regio charge Q N MO Trasistor C φ for G T ( G Note: Assumig a liear variatio of potetial alog the chael leads to a uderestimatio of curret but is a good estimate for had calculatios. T

42 MO Trasistor I- Derivatio Usig Capacitor-Like Model for Q N we ca estimate I D as: I I D D Z µ L L Z µ φ φ 0 φ φ 0 D D Q N C dφ ( φ G T dφ I D Z µ C L D ( G T D 0 D Dsat ad G T This is kow as the square law describig the Curret-oltage characteristics i the Liear or Triode regio. Note the liear behavior for small D (ca eglect D term. Note the egative parabolic depedece for larger D but still D < Dsat (ca NOT eglect D term.

43 MO Trasistor I- Derivatio Capacitor-Like Model for Q N or D > dsat the voltage drop across our chael is Dsat with the remaiig voltage ( D - Dsat dropped across the pich-off regio I D I Dsat Z µ C L Dsat ( G T Dsat Dsat D But the charge at the ed of the chael is zero due to the piched off chael, Thus, Q N ( y But what about the saturatio regio? G ( L C 0 or T G T Dsat Dsat I D I Dsat Z µ C L [( ] G T Dsat D

44 MO Trasistor I- Derivatio ummary of MOET I Relatioship I D 0 Z µ C D L Dsat ( G ad T G D T D I D I Dsat Z µ C L [( G T ] Dsat D Dsat G T

45 MO Trasistor Applicatios oltage variable Resistor A -chael MOET has a gate width to legth ratio of Z/L100, u 00 cm /sec, C0.166 u/cm ad T 1. We wat to develop a resistor that has a resistace that is cotrolled by a exteral voltage. uch a device would be used i variable gai amplifiers, automatic gai cotrol devices, compressors ad may other electroic devices. Defie what rage of D must be maitaied to achieve proper voltage variable resistace operatio. id the O-resistace ( D /I D of the trasistor from 1.5< G <4for small D. irst, to achieve voltage variable resistace operatio, we must operate i the liear regio. Otherwise, the curret is either a costat regardless of drai voltage (saturatio regio or is apprimately zero (accumulatio ad depletio. Thus, G - T > D. Give the values above, 0< D <0.5 Cotiued...

46 MO Trasistor Applicatios oltage variable Resistor Usig the liear regio I D equatio: I R R D D D Z µ C L D I D 00 Thus, 100 Ω R D ( [( ] [( ] ( 0.166e 6 / cm ( [ 1 ] D G Z µ C L 600 Ω T 0.01 D G D T G D Z µ C µ C L L Z [( ] G G T T D for small D

47 MO Trasistor Applicatios Curret ource The same trasistor is to be used for a Curret ource. Defie the rage of drai-source voltage that ca be used to achieve a fixed curret of 50 ua. or a costat curret regardless of Drai-ource voltage, we must use the saturatio regio: I D G I 50uA Dsat Z µ C L [( ] G T ( 00cm / ec 0.166u / cm ( 1 Dsat G D This source will operate over a D > G - T or D >0.173

48 MO Trasistor: Deviatios rom Ideal Chael Legth Modulatio Effect Above pich-off (whe D > Dsat G - T the chael legth reduces by a value L. Thus, the expressio for drai curret, I D I Dsat Z µ C L [( ] G T Dsat D Becomes, I I D D I I Dsat or sice* Dsat Z µ C [ ] ( ( G T L L L L, Z µ C L 1 L L 1 1+ L L L Dsat L L [( ] G T 1+ Dsat D D *I may moder devices, this assumptio does ot hold. Thus, the chael legth modulatio parameter we are derivig does ot describe the I expressios well.

49 MO Trasistor: Deviatios rom Ideal Chael Legth Modulatio Effect But the fractio of the chael that is piched off depeds liearly o D because the voltage across the pich-off regio is ( D - Dsat so, L λ D L where λ is kow as the Chael-Legth Modulatio parameter ad is typically: < λ <0.1 1 Chael Legth Modulatio causes the depedece of drai curret o the drai voltage i saturatio. I D Z µ C [ ( G T ]( 1+ D Dsat D I Dsat λ L

50 MO Trasistor: Deviatios rom Ideal Body Effect (ubstrate Biasig Util ow, we have oly cosidered the case where the substrate (Body has bee grouded. but the substrate (Body is ofte itetioally biased such that the ource-body ad Drai-Body juctios are reversed biased. The body bias, B, is kow as the backgate bias ad ca be used to modify the threshold voltage. Note that ow our chael potetial has a offset equal to B,.

51 T T φ φ ε + C ε C qn ε qn ε A D MO Trasistor: Deviatios rom Ideal Body Effect (ubstrate Biasig Thus, our threshold potetial with the body grouded, ( φ (for - chael devices ( φ (for p - chael devices Becomes, GB GB Threshold Threshold φ φ B B urface Potetial φ ε + C ε C qn ε qn ε D A ( φ (for p - chael devices ( φ + (for - chael devices B B But we would like to have this i terms of G istead of GB. ice, G GB + B ε qn A φ + ( φ T G G Threshold Threshold φ C ε C ε qn ε D (for - chael devices ( φ + (for p - chael devices B B

52 T T MO Trasistor: Deviatios rom Ideal Body Effect (ubstrate Biasig This ca be rewritte i the followig form (more coveiet to referece the threshold voltage to the B 0 case. ( φ ( φ ( Pierret TN ( Jaeger TO + γ ( φ B ( Pierret ( Jaeger γ ( φ where, γ qn A ε C TP TO is kow as the body effect parameter B (for - chael devices (for p - chael devices

53 MO Trasistor: Ehacemet Mode verses Depletio Mode MOET We have bee studyig the ehacemet mode MOET (Metal-Oxide-emicoductor ield Effect Trasistor. It is called ehacemet because coductio occurs oly after the chael coductace is improved or ehaced. I this case, TN >0 ad TP <0 Trasistors ca be fabricated such that: These trasistors have coductio for G 0 due to a chael already existig without the eed to ivert the ear surface regio. To modulate currets, a field must applied to the gate that depletes the chael. Thus, trasistors of this ature are called Depletio mode MOETs. TN 0 ad TP 0

54 MO Trasistor: Ehacemet Mode verses Depletio Mode MOET

55 Ehacemet MO Trasistor: ummary 4-Termial Depletio Ehacemet 3-Termial Depletio NMO (-chael PMO (p-chael Jaeger uses the otatio: NMO K PMO K p K K ' ' p W L W L µ µ C C W L W L where W is the Gate Width (Z i Pierret where W is the Gate Width (Z i Pierret

56 Regardless of Mode MO Trasistor: ummary NMO PMO ' W W ' W W K K µ C (Note : W Z i Pierret K p K p µ C (Note : W Z i Pierret L L L L Cutoff i D 0 for vg TN id 0 for vg TP Liear i D Z µ C L v G ( v TN G v D TN v D 0 v D i D Z µ C L v + G ( v TP G v D TP v D 0 v D aturatio i D Z µ C L for v [( v ]( 1+ λ v D G v G TN TN 0 D i D Z µ C L for v [( v + ]( 1+ λ v D G v G TP + TP 0 D Threshold oltage TN TO ( ( φ v φ + γ B TP TO ( ( φ + v φ γ B T for Ehacemet Mode TN > 0 TP < 0 T for Depletio Mode TN 0 TP 0

57 MOET mall igal Model ad Aalysis Just as we did with the BJT, we ca cosider the MOET amplifier aalysis i two parts: id the DC operatig poit The determie the amplifier output parameters for very small iput sigals.

58 + 1 - MOET mall igal Model ad Aalysis i 1 i + No-Liear I- relatioship (BJT, MOET, etc - Liearize over small sigal rage i 1 Liear i + Two Port Network - i D i G v G v D Geeral y-parameter Network I 1 y y 1 I y y MOET y-parameter Network I G y 11 G + y 1 D I D y 1 G + y D

59 MOET mall igal Model ad Aalysis [ [ [ I G y 11 y 1 G [[ [ I D y 1 y D y ij I j i G, Q, D, Q I G y 11 G + y 1 D I D y 1 G + y D Derivative of curret-voltage equatio evaluated at the Quiescet Poit MOET Amplifiers are biased ito aturatio (or Active Mode I D K [ ( G TN ]( 1+ D for D G TN λ 1. Iput Coductace. Output Coductace 3. Trascoductace I G I G I G 0 0 ad 0 y 0 ad y1 G I I D D y y 11 D 1 G T D G D λ K K ( G ( ( 1+ λ T 0

60 MOET mall igal Model ad Aalysis Compare with BJT Results There is a large amout of symmetry betwee the MOET ad the BJT MOET BJT y g o λ K ( G T I D 1 + λ D Each of these parameters act i the same maer y A I C + CE y 1 g m K ( ( 1+ λ G T D G I D TN y 1 I C T

61 MOET mall igal Model ad Aalysis Puttig the mathematical model ito a small sigal equivalet circuit Compare this to the BJT small sigal equivalet circuit

62 MOET mall igal Model ad Aalysis Overlap of Gate Oxide Add i capacitaces Overlap of Gate Oxide LD Gate to chael to Bulk capacitace LD Reverse Bias Juctio capacitaces

63 MOET mall igal Model ad Aalysis Complete Model of a MOET Overlap of Gate Oxide g mb g m B γ + φ Due to effective modulatio of the threshold voltage. Overlap of Gate Oxide ad Gate to chael capacitace Gate to chael to Bulk capacitace Reverse Bias Juctio capacitaces