Semiconductor Device Modeling and Characterization EE5342, Lecture 21 -Sp 2002
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1 Semicoductor Device Modelig ad Characterizatio EE5342 ecture 21 -Sp 2002 Professor Roald. Carter Apr02 1
2 Fully biased -MOS capacitor Chael if G > G S E x > 0 + e - e - e - e - e - e - + D Depl Reg sub = B 0 p-substrate Acceptor y s 21 02Apr02 2
3 Flat bad with oxide charge (approx. scale) If at o E x FB a the the charge the charge at Q ms /Si ' ss FB Q' m gate 1 q Q' ss cod boud Q' de dx c ss a surface is ms is x C ' ss ' Q Al SiO 2 p-si +<-- ox -->- q( ox ) q( m - ox ) E Fm q( FB ) E c E x E gox ~8e q( fp - ox ) 21 02Apr02 3 E v E c FB = G - B whe Si bads are flat E Fp E v E Fi
4 MOS eergy bads at Si surface for -chael Fig 8.10** 21 02Apr02 4
5 Fully biased - chael calc p substrate : x p dmax C t l N FB i a p G at threshold p 0 qn Q' a Q' 21 02Apr02 5 B dmax dmax C FB qn x a dmax 0
6 Q dmax ad x dmax for biased MOS capacitor Fig 8.11** xdmax (micros) Q dmax /q (cm-2 ) 21 02Apr02 6
7 -chael for C = B = 0 Fig 10.20* 21 02Apr02 7
8 Flat-bad parameters for p-chael (-subst) substrate : x For a p poly - Si gate ms t Q' ss N N l v 2 i d FB is the /Si chg de N l (o chage) Apr02 8 ms Q' Eg t 2q s ss m d i s E g q
9 Fully biased p- chael calc substrate : x dmax C t N l FB d i G at threshold 0 qn Q' d Q' 21 02Apr02 9 C dmax dmax B FB qn x d dmax 0
10 p-chael for C = B = 0 Fig 10.21* 21 02Apr02 10
11 Differetial charges for low ad high freq high freq. From Fig 10.27* 21 02Apr02 11
12 Ideal low-freq C- relatioship Fig 10.25* 21 02Apr02 12
13 Compariso of low ad high freq C- Fig 10.28* 21 02Apr02 13
14 Effect of Q ss o the C- relatioship Fig 10.29* 21 02Apr02 14
15 Coductace of iverted chael Q = - C ( GC - ) s = C ( GC - )/q (# iv elect/cm 2 ) he coductivity = ( s /t) q G = (Wt/) = s q (W/) = 1/R so I = /R = d/dr dr = d/( s q W) I 0 d D S Wd G 21 02Apr02 15 C
16 21 02Apr02 16 Basic I- relatio for MOS chael 2 G Dsat D G sat sat D D G sat G 2 G D 2 C W I I so for I by give be I let so Sat. 0 y Q' At 2 2 C W I
17 -chael ehacemet MOSFE i ohmic regio Chael 0< < G S = 0 0< D < sat E x > 0 + e - e - e - e - e - + Depl Reg p-substrate B < 0 Acceptor s 21 02Apr02 17
18 Coductace of iverted chael Q = - C ( GC - ) s = C ( GC - )/q (# iv elect/cm 2 ) he coductivity = ( s /t) q G = (Wt/) = s q (W/) = 1/R so I = /R = d/dr dr = d/( s q W) I 0 d D S Wd G 21 02Apr02 18 C
19 I- relatio for -MOS (ohmic reg) W I 2 I D is result At G sat assume 2 is cost ' that for sy W G sat 0 chael o - physical. sat 2 2 Dsat GS 2 sat 21 02Apr02 19 curr. I D I Dsat. Note ohmic for o-physical saturated
20 Uiversal drai characteristic I D1 2 9I D1 I D W 1 2 I Dsat 2 W 2 ohmic GS = +3 saturated > GS - 4I D1 GS = +2 I D1 GS = Apr02 20
21 I Characterizig the -ch MOSFE G Dsat D D S I D B 2 W GS GS 2 GS 21 02Apr so I D 2 slope GS W
22 21 02Apr02 22 ow field ohmic characteristics GS D GS GS D G 2 GS D W KP d di KP W KP W I that so let Furthermore regio. ohmic for 2 W 2 I G
23 MOSFE circuit parameters g g g m ms m rascoduc ta ce I D GS W W saturatio ohmic regio GS 21 02Apr02 23
24 MOSFE circuit parameters (cot) g g g d ds d Output I 0 D GS saturatio W or drai GS coductace ohmic 21 02Apr02 24
25 Substrate bias effect o (body-effect) ettig x dmax Si a SB S FB 2 calculatio be 2 2 p qn 2 p a SB qn qn x a so relative dmax p where SB to Source SB p 21 02Apr02 25
26 Body effect data Fig 9.9** 21 02Apr02 26
27 Refereces *Semicoductor Physics ad Devices by Doald A. Neame Irwi Chicago **Device Electroics for Itegrated Circuits 2d ed. by Richard S. Muller ad heodore I. Kamis Joh Wiley ad Sos New York Apr02 27
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