Charge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )


 Maximillian Rose
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1 The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max =  φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation: q = C ox (v  v F )... parallel plate capacitor epletion: q =  q (v ), with the () charge in the silicon being a nonlinear function of v Inversion: q =  q N  q,max, where q,max = q (v = V T ) is the charge at the onset of and ketch of the gate charge as a function of gate voltage: V  V F 5 mv  t ox φ s,max = 4 mv Xd,max x  5 mv φ p Q Q N (V ) What is the charge Q N? Q (V ) Q,max see ection 3.7 for the derivation consider: charge is constant for V > V Tn > all of the additional charge in the silicon is stored in the layer, once occurs. The layer is separated from the gate by the gate oxide; we can relate the charge (per cm ) to the applied voltage over V Tn through C ox the capacitance (per cm ) of the oxide V F =.97 V V Tn =.6 V V (V) Q N = ÐC ox ( V Ð V Tn )
2 MO Capacitance Physical Interpretation of MO Capacitance The capacitance of the MO structure is deþned as dq C = dv V From sketch, determine the slope and plot as the capacitance q N (v ) q Q (v ),max V F =.97 V V Tn =.6 V C/C ox..8 q v (V) Accumulation: parallel plate capacitor > C = C ox epletion: increment in gate charge is mirrored at bottom of region, so capacitance model is C ox in series with the region capacitance C b gate i/io surface ε ox C ox = t ox ε s C b = X d C = C ox C b Note that X d is a function of V Inversion: charge is no longer changing with V > an increment in gate charge is mirrored in the layer under the gate. The capacitance is therefore the same as in > C = C ox.6.4 V F =.97 V. V Tn =.6 V V (V)
3 Understanding MO Capacitors MO CapacitanceVoltage Curve tep : identify the ßatband voltage from the gate and potentials in equilibrium tep : determine whether V > V F leads to or to substrate is ntype > substrate is ptype > Why? positive charge on gate ( since V  V F > V) must be mirrored by a negative charge in the substrate. ntype substrate: negatively charged electrons are accumulated under the gate ptype substrate: negatively charged ionized acceptors are left, after holes are repelled away from positive charge on gate tep 3: construct C(V ) plot, using the knowledge that the substrate is depleted on the other side of V F from in tep and that occurs after. Calculation of V T and C min is necessary to quantify the plot Additional data point: determine state of MO structure in thermal equilibrium (V = V)... or [/] Example: gate: p polysilicon (where φ p =  55 mv); gate oxide thickness =, substrate: n type silicon, φ n = 48 mv (N d = 8 cm 3 ) V F =  (55 mv  48 mv) =.3 V V  V F > V > accumulated; substrate is depleted for V <.3 V Check: V = > negative charge on gate; positive in (since gate is at .55 V and substrate is at.48 V in thermal equilibrium) > positive donors in region under gate... and possibly holes due to Evaluate threshold voltage V Tp qε s N d ( φ n ) V Tp = V F Ð φ n Ð =.3 Ð (.48) Ð 3.8 = Ð 3. V C ox Minimum capacitance occurs just prior to and is the series combination of the oxide capacitance and the maximum capacitance: ε ox ε s Ð Ð.4 C min = = =.6 ff/cm t ox X d, max Ð6 Ð6.9 Maximum capacitance is C ox =.7 ff/cm. C/C ox.75.6/.7 = V.3 V V
4 MO Field Effect Transistors MOFET Circuit ymbols A,,,,,,,,,,,, gate contact gate n polysilicon gate contacts W, deposited oxide n polysilicon gate active area (thin oxide area) polysilicon gate contact metal drain contacts edge of active area contact drain field n diffusion oxide [ ptype ] L, gate oxide drain A n drain diffusion L diff Two complementary devices (each with two symbols): both are very useful psubstrate (ntype channel under gate oxide) nsubstrate (ptype channel under gate oxide) I n nchannel MOFET ate V > V V rain ource n p n I n ulk or ody _ V Four electrical terminals: (lowest potential for nchannel, highest for p channel), drain, gate, and. I p V _ V > pchannel MOFET ate ource rain p n p I p ulk or ody p asic concept: layer (called the channel) formed under gate between and drain enables drift current
5 nchannel MOFET rain Characteristics etup: I =, V = V > to reversebias pn junctions to. Measurement scheme: short to to make it a three terminal device, vary gate voltage, drain voltage and see effect on drain current. pchannel MOFET rain Characteristics etup: I =, V = V > to reversebias pn junctions to. Measurement scheme: short to to make it a three terminal device, vary gate voltage, drain voltage and see effect on drain current I V I n (V, V ) V V V _ V I _ p V I (V,V ) 5 V 6 V = 3.5 V 3 V = 3.5 V 5 4 I n (µa) 3 (triode region) 3 4 V = V V Tn = V V constant current (saturation) region V = 3 V V =.5 V =,.5, V (cutoff region) V = V V =.5 V 5 V (V) 5 I p (µa) 5 5 (triode region) 3 4 V = V V Tp = V V (saturation region) V = 3 V V = 5 V =,.5, V (cutoff region) V = V 5 V =.5 V V (V)
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