Homework Assignment No. 1 - Solutions
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1 Homework Assignment o. 1 - Solutions Problem P1.7 This question is as easy as it looks, no tricks here. a. The delay from a to b is simply the delay of an inverter times the number of inverters which would be ns. b. i. The period in this case is simply twice the delay around the loop, T=2 ns. ii. The frequency is 1/T =5 MHz. Problem P1.8 The delay of an R circuit with a step input applied is: n our case, we are solving for t: c. For (t=.6: d. 1.2: Problem P1.9 ( t = 1.2(1 e t R 1.2 t = = ( = ( ( ln 12.5x ln ps This circuit will never read 1.2. e. The delay from % to 9% DD : % t = t.1 = (1 e R t = 132 ps t.9 = (1 e R t = 2.88ns 9% t = t9% t% = = 2.75ns The delay for f and g uses the exponential rise/fall equation: f. For R DOW : g. For R UP : h. The ratio of delays is: t ( t = 1.2e R t = 8.66ms DOW t ( t = 1.2(1 e R t = 2.8ms UP
2 t RATO tup 2.8 = = = 2.4 t 8.7 DOW or.42 (depending on which way you did the ratio. Problem P2.1 P1.2. a The solution for the MOS case is based on Example 2.4: B The equation for T is: T = FB 2φ F alculate each individual component. 17 kt ni φfp = ln =.26ln =.44 q A 1.4 φ = φ φ = =.99 G Fp G( gate 13 2 = 4ε = 3.5 F/cm = F/cm B B = / cm = = = =. 6 ε =.99 (.88 ( =+.18 TO For the PMOS device: 17 kt D φfn = ln =.26ln =.44 q ni 1.4 φ = φ φ = =+.99 G Fn G( gate 7 B 7 2 B cm 11 6 = =.6 TO = / = =.188 =.99 (.88 ( =.138 b The magnitude of T would be higher. Since the device is PMOS this means that T is lowered. Since the only thing that s been changed is the doping of the gate, only φ G changes. The new T then becomes: T = = 1.24
3 Problem P2.1 - ontinued c Since T will be adjusted with implanted charge ( : =.4.18 =.382 = (1.6 (.382 To calculate the threshold implant level : q For the MOS device from part(a: = = q.6 = = = 3.82 ions / cm q (p-type For the PMOS device from part(a: ( ( = = = 2.62 ions / cm q (n-type For the PMOS device from part(b: ( ( = = = 8.4 ions / cm q (p-type d The advantage of having the gate doping be n + for MOS and p + for PMOS could be seen from analysis above. Doping the gates in such a way leads to devices with lower threshold voltages, but enables the implant adjustment with the same kind of impurities that used in the bulk (p-type for MOS and n-type for PMOS. f we were to use the same kind of doping in gate as in the body (i.e. n + for PMOS and p + for MOS that would lead to higher un-implanted threshold voltages. Adjusting them to the required lower threshold voltage would necessitate implantation of the impurities of the opposite type near the oxide-si interface. This is not desirable. Also, the doping of the poly gate can be carried out at the same time as the source and drain and therefore does not require an extra step.
4 Problem P2.3 P1.3. a For each transistor, derive the region of operation. n our case, for =,.4, the transistor is in the cutoff region and there is no current. For =.8,1.2, first calculate the saturation voltage Dsat using: DSAT ( T EL = + E L T For our transistors, this would be: =.8 = 1.2 MOS PMOS ext, we derive the characteristics using the linear and saturation current equations, we get the graphs shown below. haracteristic of MOS urrent (ua olts ( gs = 1.2 gs =.8
5 Problem P2.3 - ontinued haracteristic of PMOS urrent (ua gs = -1.2 gs = -.8 olts ( -3 To plot DS vs., first identify the region of operation of the transistor. For < T, the transistor is in the cutoff region, and there is negligible current. For > T and DS, the transistor is in the saturation region and saturation current expression should be used. The graph is shown below. learly, it is closer to the linear model. ds vs. gs of MOS ds ( gs (
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