Monolithic semiconductor technology

Transcription

1 Moolithic semicoductor techology 1

2 Ageda Semicoductor techology: Backgroud o Silico ad Gallium Arseide (GaAs) roerties. Diode, BJT ad FET devices. Secod order effect ad High frequecy roerties. Modelig 2

3 . atoms Covalet Bodig betwee Bad Ga 1eV betwee Metal ad. Isulator GaAs have better -doed mobility erformace. Silico is cheaer. Silico ad GaAs as itrisic semicoductors 3

4 Doig The Doig add a states that are close to the coductio or valace for. curret electro ad hole The material will have more electros ad holes to coduct. If the ew Fermi level is close to the coductio or valace bad, all these doig will be available for coductio ad almost equal to the carrier cocetratio. 4

5 Doig The electro cocetratio () ad the holes cocetratio () are fuctios of the robability of fidig the article ad the allowed eergy state. The umber of times equal a costat itrisic carrier cocetratio. 5 kt E E i kt E E v kt E E i kt E E c F i V F i F F C e e N e e N

6 Curret Drift Curret desity charge_x_seed. field Due to collisios we get limited mobility uder electric Imurity ad lattice vibratio reduce mobility. There is a saturatio curret limit There is avalache breakdow limit j q Charge Seed 6

7 Curret Diffusio Flow from high cocetratio towards low cocetratio Due to collisios we get limited electro diffusio. coefficiet j q D d dx D d dx Flax Flax 7

8 Deletio regio (W). Build i voltage (Vbi=V) The charge is uiform from the uiform doig The electric field ad the voltage comes from itegratio Diode Ec Ei Ev + qv Charge Field Volt Ef Ei qv The charge is costat that give Electric field (E) of triagle with Emax from itegratio. Both sides charge times legth is equal ad we ca exress X from W, Na ad Nd. 8

9 Diode: Doig, Charge, Electric- Field, Eergy Bad ad Voltage 9

10 Diode We ca itegrate for the voltage from the Electric field triagle shae. Ad exress it with Emax ad X from revious. Now we ca fid W ad Cde Vbi Voltage comes from doig ad the relatio betwee Bad Eergy ad q. Ei Ec Ev + qv Ef Ei qv Charge Field Volt 10

11 Charge x, t x, t t Flax Coductivity Equatio geeratio x g R t D 2 x 2,,, x t x t x t Recombiatio There is o drift outside deletio Sice there is o Electric field x x x x x L x x x L D Ae D C curret L L 2 x A 0 D 0 x A D C curret L L 2 x x L 11

12 Forward voltage : Access electros ad holes ijectio overcome barrier. Diode Curret Diffusio Curret from Diffusio Equatio. The ic shows electros ad holes i log scale from both side of the deletio regio From the + ad doig differece the access electro are domiat curret. 12

13 We start by exressig the Vbi with holes differece i + ad regios. We comare the equatio with/without forward voltage to miority state. The Δ is the access at the edge of the deletio The δ is the fuctio of the access as it decays from the coductio equatio. Fially we exress it as diffusio curret Diode Curret 0 0 V P P 0 0 I bi 0 0 q D qa L Q C diff kt N N a l 2 q i P P P qa e e dq dv e qv kt V bi bi qv kt V kt x q F F 0 dx 2 1 AL kt d D L P P qal 0 e kt P l q P P 0 P qv kt 0 e x e e qv qv kt qv F 0 0 e kt F kt 1 0 F F q I kt 1 We ca also itegrate to fid the charge from the two side of the deletio. Now we ca differetiate this as the diffusio ca x L 13

14 Diode 14

15 Questio 15

16 Solutio A kt N N a d 2 V l 8.625e l 2e17 0.5e15 / 1.5e V bi q B w 2.2um i V V e bi r 1 1 w q N N 1.6e 19 2e17 0.5e15 a d c C A e r w ff 16

17 BJT Biolar Juctio Trasistor Diffusio betwee base emitter diode Higher diffusio curret from emitter comared to base by high doig at base the emitter ad low doig at the Higher diffusio curret from emitter by arrow base with o recombiatio (L<< recombiatio legth) Drift from base to collector by high field electric j j qd qd D w D L P B L w e B e qv kt qv kt Ec Ef Ev BJT 17

18 BJT Iut Small Sigal Model Very basic model. Amlifies currets. Diffusio ca causes the diode to be o eve at reverse voltage We ca fid iut resistace We have derived the iut caacitaces b c e 18

19 For outut side: BJT Outut Small Sigal Model We foud β ad ᶢm from Ic/Ib. The ro is from differetiate curret slo from the I/V curves The deletio caacitace is a diode i reverse voltage. 19

20 BJT > HBT Heterojuctio Biolar Trasistor reduce I classical BJT for high gai, the base width must be i additio to emitter over base cocetratio ratio. Low base cocetratio icreases the base resistace ad. frequecy degrades the oeratig I HBT, the base doig is higher ad the holes are blocked. differece from the bad ga + Ec Ef Ev + P+ Ec Ef Ev BJT HBT 20

21 Bad Diagram Costructio for Start with lacig the bads from vacuum level before cotact Adjust the all bads to have Fermi level equal. The deletio width is deedet o cocetratio. Hetrojuctio 21

22 MOSFET Metal Oxide Semicoductor Field Effect Trasistor 22

23 Mosfet gate bulk 23

24 Mosfet accumulatio Drai, Source ad Bulk equal 0V VGS<0 Mobile holes are attracted Costat caacitace from oxide thickess ad high resistace from bulk. 24

25 Drai, Source ad Bulk equal 0V Mosfet deletio VGS is ot egative to attract holes ad ot ositive eough to attract electros. Deletio balace the added charge at the gate. Low caacitace from oxide ad deletio. Deletio Iversio 25

26 Mosfet Iversio Drai, Source ad Bulk equal 0V VGS > Vth Electros are attracted Itrisic eergy level cross the Fermi level this mea iversio The Gate Source/Drai caacitace is the oxide thickess without substrate resistace 26

27 Threshold voltage For simlicity let V is the otetial uder the oxide We get the deletio ad build i voltage as i diode We ca idetify accumulatio Q=0. V= 0 we get charge ad deletio. V= -Vbi the chael is iverted If Bulk<source otetial, the threshold voltage icreases X 0 d 2 E i si E V V qn N e V F Q qn X 2 qn V V Q 2 qn V V V a bi kt a i bi kt l q a d si a bi si a bi SB N i a 27

28 Mosfet curret V V gs TH V gs TH V V V V V V gs TH gs TH ds S G D S G D I Q I d Qv x d WC WC ox ox V V x x V x V V V GS GS TH TH dv dx I I d _ liear d _ sat W C L W C 2L ox ox V V V 2 GS GS V TH TH V DS 1 V 2 2 DS g m W C 2 ox L W V V C I gs TH ox d L 28

29 Mosfet Well For isolatig the substrate oise. For chagig Threshold effect For PNP MOSFETs Bulk effect o Vth: Vgs charge = ew_delitio+iversio. _ B + S G D Delitio 29

30 MOSFET secod order effect: Short Chael Chael legth modulatio L_effective. Outut resistace degradatio. Vds uch trough from deletio: We eed to icrease substrate doig for arrow deletio. This will reduce mobility ad icrease the Vth. We eed to shrik oxide to correct Vth. This cause oxide breakdow. I d S G D _ W C 1 ox gs TH 2 L 2 V V V ds 30

31 As L reduces i legth, the high electric field cause the electro to reach velocity saturatio ad reduce the mobility The drai curret icreases liear with VGS By addig lightly doed drai betwee the gate oly ad drai, we ca reduce the voltage that the drai sees ad by that save the high mobility Other effects; Short Chael Temerature sesitivity to saturated velocity ad mobility Oxide breakdow (L) VTH reductio from tras Substrate curret D ox G S TH y If oxide is thi that we ca get gate curret 31 v E dv y I W C V V V dy evaluate at the drai dv v y sat / dy I W v C V V V D sat ox G S TH D S, sat

32 Carrier diffusio from source to the body uder the gate ad collected by the drai. Weak-Iversio W I I e D D 0 L / q V V kt G S TH 32

33 Breakdow 1.Drai to source uch through 2.Drai to substrate diode at reverse voltage 3.Oxide breakdow 33

34 MESFET Gate MEtal Semicoductor Field Effect Trasistor Gate chael is a reverse bias Schottky diode (metal-semicoductor) Bad diagram is iflueced by Vacuum Eergy Curret flow from the semicoductor to the metal for equalizig the Fermi level. Usually we do ot have comlemetary PNP. The two materials before joi E0 The two materials after joi Source Gate Deletio Chael layer Drai Ef Ec Ef Ev Semi-Isulatig Buffer 34

35 MESFET Liear Oeratio Very simle device to maufacture. Curret is domiate by the chael oeig (B) ad the electric field. Build i voltage lus close chael VGS is otetial relates to the chael oeig (B). For the aalysis the vertical field is domiat Start Aalysis with ohm law 1 1 I dx dv I dx d d A qn w a h L ds 1 1 I dx dv d qn w a h 0 d x 0 Vds h x I L 1 d qn w a d dv a 0 Vds V V V bi gs ch x I G 1 dv d 0 V 0 o G 0 d qn w a 2V d 0 r ad deletio L qn V x d for sm all V V V bi gs I G 1 V d 0 V o for l arg e V ds ds 2 I G V V V V V V 3 V o 3 / 2 3 / 2 d 0 ds bi gs ds bi gs ds 35

36 MESFET Saturatio Oeratio Vds reaches the Vo, ich off, voltage Hel with Tailor series. Result i the same equatio as the Mosfet. V V V V V V V V o bi gs dsat dsat o gs bi 2 I G V V V V 3 V o 3 / 2 3 / 2 d 0 dsat o bi gs V V V th bi o 2 2 V V gs I G V V V V 1 d 0 gs th o o 3 3 V o 3 / 2 3x 3x 1 x I d G 0 4V 2 V V gs th qn d o 2 wa 2 w w I V V C V V 2L a 2L r d gs th s gs th L 0 qn a d r 2 th V gs 3 / 2 4 V th 2 36

37 MESFET Oeratio Very simle device to maufacture. Curret is domiate by the chael oeig (B) ad the electric field. Build i voltage lus close chael VGS is otetial relates to the chael oeig (B). VGS Chage Source Gate Deletio Chael layer B Semi-Isulatig Buffer Drai I ch I I qn G G 0 0 V ds 0 d V Wa 1 1 ds V bi 2 3 V V o h dv a gs V V o 1.5 V V V V V bi ch V gs dv ds h x qn I bi gs d 2 0 Wa L r 1.5 V bi V V qn ds 0 d 1 gs V h dv a ch x Source VDS Chage Gate Deletio Chael layer Semi-Isulatig Buffer Drai I sat G 4V 0 o CW 2 2 V V V V V V V gs th gs th th bi o 2 L 37

38 HEMT - Chael Gettig the electros to travel without scatterig effect highest gai BW erformace. Usually we do ot have comlemetary PNP. Source Gate Drai N-AlGaAs Udoed AlGaAs i GaAs There are differet versio with differet materials for: high voltage ad low oise Drai Source 38

39 Caacitace, Threshold voltage ad Pich off voltage the same as MOSFET. I comariso to MOSFET :µ ad trasistor gai (by C) is imroved. If we would have wat to icrease C for gai, Nd is limited by Schottky barrier. HEMT I d _ liear W C L V gs V th V ds 1 2 V 2 ds I d _ sat W C 2 L V gs V th 2 g m W C 2 L V gs V th 39

40 HEMT Fabricatio First active layer is etch out form uused area. The gate is formed after etchig the + layer ad some of the layer for high breakdow voltage We use mushroom gate for low resistace ad mi gate legth. The gate is located closer to source with less mushroom for low Cgs ad far from the drai for high breakdow voltage. 40

41 FET Simlified Model Characterizig iut caacitace ad high frequecy degradatio. Characterizig outut gai ad early voltage for DC ad high frequecy gai curret degradatio. Characterizig feedback g d s 41

42 Modelig FET v1 y11 y12v2 y21v1 y22 v2 v1 y11+y12 -y12 (y21-y12)v1 y22+y12 v2 42

43 Bibliograhy BGU course Itroductio to Semicoductor devices. William Liu, Fudametal of III-V Devices HBTs, MESFETs ad HFETs/HEMTs. R. Jacob Baker, CMOS circuit desig, layout, ad simulatio 43