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2 1.5um 3.um 6.um calig Rule for Very hallow Trech IGBT toward CMO Process Comatibility Masahiro Taaka ad Ichiro Omura Kyushu Istitute of Techology 1-1 esui-cho, Tobata-ku, Kitakyushu-city, Fukuoka, , JAPAN. Phoe/Fax: Abstract Dee trech gate is used for latest IGBT to imrove device erformace. By large differece from dee submicro CMO structure, there is o rocess comatibility amog CMO device ad trech gate IGBT. e roose IGBT scalig rule for shrikig IGBT cell structure both horizotally ad vertically. The scalig rule is theoretically delivered by structure based equatios. Device erformace imrovemet was also redicted by TCAD simulatios eve with very shallow trech gate. The rule eables to roduce trech gate IGBT o large diameter wafer i CMO factory with suerior roductivity. P-float 3um Tox=1m N-Base Keywords: 3-45mm wafer, CMO rocess, hallow trech I. INTRODUCTION The 3mm to 45mm wafer CMO techology ehaces the mass-roductivity i digital itegrated circuits, ad hece every semicoductor devices, icludig ower semicoductors, will be forced to be desiged i the comatibility of the large diameter wafer rocess techology, so that IGBTs wo t be a excetio. I revious works, rather dee trech gate structures have bee emloyed to imrove the device erformace ([1]- [4]) uder reset rocess techology stadard for discrete ower. ome extreme structures such as aometer trechtrech sacig have bee demostrated showig limits ad ossibilities of the future IGBT ([5]-[7]). I this aer, we theoretically show a roadma of IGBT techology by the scalig rule with a factor k. cale dow cocet is show i Fig. 1. The ratios of the desig arameters are maitaied similar to CMO scalig for all scalig factor k. e show the simulatio results to rove the scalig rule for IGBT desig i scaled structure with shallower trech gate, lower thermal budget, shallower doig ad etchig rocesses similar to CMO scalig roadma [8]. Based o reviously roosed tructure Orieted aalytical model [9], the scalig rule is established ad the results show that very shallow structure eve imroves the erformace of IGBT. This scalig rule ca redict the device erformace with high scalig factor because the roosed model shows high uracy for wide rage of structure ad temerature. (a) 1.5um Tox=5m (b).6um Tox=2m (c) 3.um.6um 1.2um Fig. 1. Cocet of trech gate IGBT scalig rule. II. IGBT CALING RULE A. Cathode ide Formulatio by Quasi-2D MO-ADE model e firstly modelled Cathode side ijectio efficiecy by oly structure arameters of trech gate IGBT. The model, amed Quasi-2D MO-ADE model, is simle yet very urate for wide rage of structure arameters ad device
3 temerature. I this model, the electro curret flowig from MO gate is assumed to be divided for two aths, regio betwee treches uder ad umulatio layer of MO gate, as show i Fig. 2. I J cell J cell J J N-Base Fig. 2. Curret flow of trech gate IGBT. Electro curret i regio is assumed to divide J ad I. First, the electro curret flowig i regio (J ) is modelled as followig. The electro ad hole are assumed to distribute oe dimesioally. Ad they kee same cocetratio by coductive modulatio. I result, followig differetial equatio ca be formed as ADE (Ambiolar Diffusio Equatio). d J J 2 kt (1) here, ad are the mobility for hole, electro ad carrier cocetratio, resectively. ecod, the electro curret flowig via the umulatio layer of trech MO gate (I ) ca be formed with the electro mobility of the umulatio layer, umulated charge Q ad otetial as followig. I d Q (2) Here, we assume same otetial is alied for both electro curret elemets. By cosiderig cell width ad width as show i Fig. 2, followig equatios ca be formed for cell curret ad curret. cell J J (3) J I J (4) cell Followig differetial equatio ca be established by combiig (1) to (4). Q 1 q x ( ) 1 2q D 1 1 J d here is electro ijectio efficiecy from trech structure. It will be fudametal equatio for the scalig rule. B. The IGBT calig Rule Proosed scalig rule is summarized i Table 1. The rule is theoretically delivered from revious equatio. Equatio (5) idicates that the scaled device has same ijectio efficiecy of origial device with followig coditios: Q cost. q ( x) d (5) (6) cost. (7) By alyig the scalig rule with scaled electric field i gate oxide as E ox =E ox /k, (6) ad (7) are held comletely. voltage is squarely scaled as V g =V g /k 2 i this case. By alyig the scalig rule with costat electric field i gate oxide as E ox =E ox, the left had side of (6) should be higher. o, higher ad lower V ce (sat) are obtaied. voltage is scaled as V g =V g /k i this case. IGBT erformace imrovemet ca be doe with shallower trech, without higher stress for gate oxide by the scalig rule. Table 1. ummary of roosed scalig rule Parameters Electric field i gate oxide E ox =E ox /k calig Ratio Electric field i gate oxide E ox =costat voltage V g 1/k 2 1/k Half width 1/k Half cell itch 1 N-Emitter width E 1/k Trech deth D T 1/k deth D P 1/k N-Emitter deth D E 1/k Half cotact hole width C 1/k oxide thickess T ox 1/k -Emitter caacitace C ge 1 -Collector caacitace C gc 1 Collector-Emitter caacitace C ce 1/k Curret desity i cotact hole J ch charge Q g 1/k 2 1/k Electro ijectio efficiecy 1 >1 tored carrier desity = 1 >1 k
4 J c [A/cm 2 ] Carrier Cocetratio[1/cm 3 ] J c [A/cm 2 ] III. CALCULATION REULT AND DICUION Two-dimesioal TCAD simulatios were erformed to rove the scalig rule ad redict erformace imrovemet. 1.2kV-class Field-to tye IGBT structures were assumed. A. O-state characteristic I c -V c characteristics of scaled devices with scaled electric field i gate oxide as E ox =E ox /k, are show i Fig. 3. The curves for ad 2 show good agreemet but more scaled devices show smaller saturatio curret. It is due to V th shift by the scalig V th 2 qn i C ox A here C ox is gate caacitace er uit area, N A is etor cocetratio i ad is surface otetial of MO chael. V th is reduced by scale dow because gate caacitace er uit area is icreased as C ox =kc ox. But V th is ot scaled by k exactly eve if N A ad are uchaged. I c -V c characteristics with costat electric field i gate oxide as E ox =E ox, are show i Fig. 4. Lower V ce (sat) is obtaied by scale dow. O-state carrier distributio i N-Base regio is show i Fig. 5. Cathode side carrier cocetratio is icreased by scale dow. Higher ad lower V ce (sat) are achieved by scale dow eve with shallower trech, as metioed i revious sectio. (8) Fig. 4. Calculated I c -V c characteristics of scaled devices with costat electric field i gate oxide as E ox =E ox. V ce (sat) is imroved by icreasig scalig factor k. 3E+16 3x1 2E+16 2x E+16 1x Fig. 3. Calculated I c -V c characteristics of scaled devices with scaled electric field i gate oxide as E ox =E ox /k. ad 2 show good agreemet but more scaled devices show lower saturatio curret Distace from /N-Base boudary[um] Fig. 5. Calculated carrier distributio i N-Base regio for scalig factor to 5. The zero oit of horizotal scale is set to /N-Base boudary. Cathode side carrier cocetratio is icreased by scale dow. B. Tur-off characteristic Tur-off waveforms of scaled devices with costat electric field i gate oxide are show i Fig. 6. Exteral gate resistace is costat. caled devices show slight delays because the differece of gate voltage ad threshold voltage, (V ge -V th ), is ot scaled by k exactly. The legth of miller lateau is costat because of C ge ad C gc are costat.
5 I c [A] I c [A] time[us] Fig. 6. Calculated Tur-off characteristics of scaled devices with costat electric field i gate oxide as E ox =E ox ad same exteral gate resistace. C. hort-circuit characteristic hort-circuit waveforms of scaled devices are show i Fig. 7. caled device shows slightly higher saturatio curret because (V ge -V th ) is ot scaled by k exactly time[us] Fig. 7. Calculated short-circuit waveforms of scaled devices with costat electric field i gate oxide as E ox =E ox IV. CONCLUION e roosed trech gate IGBT scalig rule, which is theoretically delivered from Quasi-2D MO-ADE model. The rule is simle ad urate as demostrated by twodimesioal TCAD simulatios. The scalig rule theoretically roves, for the first time, that the higher carrier storage is realized with shallower trech gate ad shallower doig structure. The scalig dow i the trech IGBT structure omlishes both the higher device erformace ad the higher comatibility to the large diameter wafer rocess with reduced trech deth, thermal budget, doig deth ad oxide thickess. The collector-emitter voltage dro has sigificatly reduced with the scalig factor without icreasig gate oxide electric field stress. The roosed scalig rule reresets a ossibility of techology directio ad roadma for future IGBT for imrovig the device erformace with high volume roductivity by CMO comatible large diameter wafer techology. REFERENCE [1] M. Kitagawa et al., A 45V ijectio ehaced isulated gate biolar trasistor (IEGT) oeratig i a mode similar to a thyristor, IEDM Techical Digest, , [2] M. Harada et al., 6V Trech IGBT i Comariso with Plaar IGBT A Evaluatio of the Limit of IGBT Performace-, Proc. Of the 6th iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , [3] M. Momose, et al., A 6V uer Low Loss IGBT with Advaced Micro-P tructure for the ext Geeratio IPM, Proc. Of the 22d iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , 21. [4] T. Laska, et al., The Field to IGBT (F IGBT) A New Power Device Cocet with a Great Imrovemet Potetial, Proc. of 12th IPD, , 2. [5] A. Nakagawa, Theoretical Ivestigatio of ilico Limit Characteristics of IGBT, Proc. Of the 18th iteratioal ymosium o Power emicoductor Devices & IC s(ipd), essio 1-2, 26. [6] M. Takei, et al., DB (Dielectric Barrier) IGBT with Extreme Ijectio Ehacemet, Proc. Of the 22d iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , 21. [7] M. Baus, et al., Fabricatio of Moolithic Bidirectioal witch (MB) devices with MO-cotrolled emitter structures, Proc. Of the 18th iteratioal ymosium o Power emicoductor Devices & IC s(ipd), essio 6-28, 26. [8] Robert H. Deard et al., Desig of Io-Imlated MOFET s with Very mall Physical Dimesios, IEEE Joural of olid-tate Circuits, Vol. C-9, No. 5, , Oct [9] M. Taaka et al., tructure Orieted Comact Model for Advaced Trech IGBTs without Fittig Parameters for Extreme Coditio: art I, Microelectroics Reliability 51, , 211.
doi: info:doi/ /j.sse
doi: ifo:doi/1.116/j.sse.1.1. IGBT calig Pricile Toward CMO Comatible Wafer Processes Masahiro Taaka* ad Ichiro Omura Kyushu Istitute of Techology, 1-1 esui-cho, Tobata-ku, Kitakyushu-city, 84-855, APAN
More informationdoi: info:doi/ /j.microrel
doi: ifo:doi/10.1016/j.microrel.2014.07.158 Structure orieted comact model for advaced trech IGBTs without fittig arameters for extreme coditio: art II J. Takaishi a, *, S. Harada a, M. Tsukuda b, I. Omura
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