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1 doi: ifo:doi/1.116/j.sse.1.1.

2 IGBT calig Pricile Toward CMO Comatible Wafer Processes Masahiro Taaka* ad Ichiro Omura Kyushu Istitute of Techology, 1-1 esui-cho, Tobata-ku, Kitakyushu-city, , APAN 1. Abstract A scalig ricile for trech gate IGBT is roosed. CMO techology o large diameter wafer eables to roduce various digital circuits with higher erformace ad lower cost. The trasistor cell structure becomes laterally smaller ad smaller ad vertically shallower ad shallower. I cotrast, latest IGBTs have rather deeer trech structure to obtai lower o-state voltage dro ad tur-off loss. I the asect of the rocess uiformity ad wafer warage, maufacturig such structure i the CMO factory is difficult. I this aer, we show the scalig ricile toward shallower structure ad better erformace. The ricile is theoretically exlaied by our reviously roosed tructure Orieted aalytical model. The ricile reresets a ossibility of techology directio ad roadma for future IGBT for imrovig the device erformace cosistet with lower cost ad high volume roductivity with CMO comatible large diameter wafer techologies. Keywords: IGBT, More tha Moore, costat field scalig, roadma, comact model 1. Itroductio The 3mm to 45mm More Moore field semicoductor techology based o the high resolutio lithograhic techiques ehaces sigificat erformace ad mass-roductivity imrovemets i the digital itegrated circuits by Moore s Law as a scalig by a factor of.7 every years for critical dimesio [1] [17]. O the other had, the imortace of More tha Moore field like that aalog ad mixed sigal rocessors, sesors ad actuators, micro-mechaical devices, ad ower devices, is icreased a lot. Ad these More tha Moore devices also will be forced to be desiged i the comatibility of the large diameter wafer rocess techology to realize better erformace ad lower cost. Trech gate IGBTs are curretly mass roduced o the wafers of ~mm diameter. Curret structures have rather dee trech gate o the Cathode side to obtai better trade-off relatioshi betwee o-state voltage dro V ce (sat) ad tur-off loss[]-[16]. Thus, curret techical directio for the trech gate IGBT is differet from the More Moore rocess techologies. I this aer, we roose a scalig ricile for the trech gate IGBT. By alyig the ricile, the More Moore rocess techologies ca be used for the trech gate IGBT fabricatio ad the scaled IGBT shows better erformace eve with shallower Cathode structure; shallower trech gate ad shallower P-base. The ricile directs ew IGBT desig treds with the comatibility for the large diameter wafer rocess techology. * Corresodig author. mtaaka@hotmail.com Tel/Fax: +81 (93)

3 1.5um 3.um 6.um From ext sectio, we begi with the cocet for our scalig ricile. The we show the verificatio results for the scalig ricile by two-dimesioal TCAD simulatios. The results show that the IGBT eve with shallower Cathode structure which desiged by the roosed scalig ricile has lower o-state voltage dro tha the covetioal structure. After that, we discuss about this imrovemet by referrig our reviously roosed tructure Orieted aalytical model [18]. The imrovemet ca be theoretically exlaied by the comact model formatio. Fially we show a otetial of the IGBT s further erformace imrovemet by reducig wafer thickess margi, which is eabled by arrower trech-trech sacig.. IGBT calig Pricile D D T tn-base P-float P-Base 3.um N-Base N-Buffer P-Emitter W Tox=1m 16um (a) Covetioal structure k=1 The scalig ricile is based o the geeral CMO scalig ricile with cosiderig the Cathode side electro ijectio efficiecy. The ricile realizes both shallower Cathode structure ad higher tha the covetioal structure. It leads higher carrier cocetratio i the Cathode side ad lower o-state voltage dro. Figure 1 shows the cocet of the scalig ricile. Figure 1 (a) shows commercially available IGBT that has a 6um deth trech gate ad a 3um deth P-base. Trech-trech sacig is 3um ad cell itch is 16um. It uses a 1 agstrom gate oxide thickess ad the P-base cocetratio is chose to give suitable gate threshold voltage V t of aroud 5V. The alied gate voltage is 15V. I this aer, we itroduce a scalig factor k for these structure arameters ad the gate voltage. Figure 1 (b) ad (c) show the scaled IGBTs with k= ad 5 resectively. Four arameters are reduced by the scalig factor k; trech-trech sacig, gate oxide thickess T ox, trech deth D T ad P-base deth D P. I the other words, =/k, T ox =T ox /k, D T =D T /k ad D P =D P /k where the rimed arameters refer to the scaled device. The cell itch W kees costat. There are o arragemets i the Aode side. For examle, the scaled device with k= has a 3um deth trech gate, a 1.5um deth P-base, a 1.5um trech-trech sacig ad a 5 agstrom thickess gate oxide. But the cell itch kees 16um as the covetioal structure. 1.5um 3.um Tox=5m 16um (b) caled structure k= P-Base.6um P-Base.6um Tox=m 1.um 16um (c) caled structure k=5 Figure 1. caled trech IGBT Ulike the CMO scalig ricile, the P-Base doig cocetratio is ot scaled to kee similar saturatio curret level to the covetioal structure. But, as discussed later, slight adjustmet for the P- Base cocetratio is required to obtai same switchig characteristics ad saturatio curret as the covetioal structure.

4 Carrier Cocetratio[1/cm 3 ] c[a/cm ] The gate voltage for the scaled device is reduced by the scalig factor. I the other words, V g =V g /k. o, for examle, the gate voltage for k= device is 7.5V. The alied electric field i the gate oxide is ket as the covetioal structure. I order to roduce highly scaled device such as k=5, several develomets for the fabricatio rocess would be required. First, high quality large diameter Floatig Zoe (FZ-) wafers should be established while the Czochralski (CZ-) wafers or eitaxial wafers are used for the More Moore devices. ecod, the short chael effect due to the shallower P-Base should be elimiated to reduce leakage curret. Third, the high-k gate dielectric ad the metal gate rocesses should be develoed for the trech gate to kee dielectric reliability ad lower gate resistivity. 3. Verificatio of the calig Pricile Proosed scalig ricile was verified by twodimesioal TCAD simulatios. We used 1.kV thi wafer PT-IGBT vertical structure for the validatio. Table 1 shows structure arameters for k=1 to 5. CP- Base is the P-Base doig cocetratio at the juctio betwee the N-Emitter ad P-Base. Gaussia distributios are assumed to P-Base doig rofiles. The cocetratios are adjusted so that the threshold voltage of the scaled devices are 1/k of the covetioal (k=1) device. The N-Base doig cocetratio is 7.x1 13 cm -3. The P-Emitter doig cocetratio ad thickess are 1.x1 17 cm -3 ad 1um resectively. The N-Buffer doig cocetratio ad thickess are 9.x1 16 cm -3 ad 1um resectively. A costat doig rofile is assumed for the P-Emitter ad N-Buffer. Table 1. tructure arameters used for the scalig ricile verificatio. k W[um] D T [um] D P [um] [um] T ox [A] V g [V] CP-Base [x1 17 cm -3 ] tn-base[um] Calculated I c -V ce characteristics of the scaled structures are show i Figure. The o-state voltage dro is reduced with icremetig k. Calculated N-Base carrier distributios of the scaled structures are show i Figure 3. It shows that higher carrier cocetratio ca be obtaied i the Cathode side with icremetig k. The result meas that this IGBT scalig ricile realizes higher electro ijectio efficiecy tha the covetioal structure. It also meas the erformace of the scaled device is better tha the covetioal structure. Calculated iductive tur-off waveforms are show i Figure 4. The scaled devices show same switchig characteristics because the gate charge Q g ad the differece of the gate voltage ad threshold voltage, V g -V t, are equally scaled by k. The Q g is scaled as Q g =Q g /k due to T ox =T ox /k, D T =D T /k ad V g =V g /k. Calculated breakdow characteristics are show i Figure 5. The scaled devices show higher breakdow voltage because the electric field distributio aroud the bottom of the trech gate is imroved by arrower trech-trech sacig k=1 Vge=15.V k= Vge=7.5V k=3 Vge=5.V k=4 Vge=3.75V k=5 Vge=3.V Vce[V] Figure. Calculated I c -V ce characteristics for the scalig factor k=1 to 5. 3.E+16.E+16 1.E+16 k=1 Vge=15.V k= Vge=7.5V k=3 Vge=5.V k=4 Vge=3.75V k=5 Vge=3.V.E Distace from Aode[um] Figure 3. Calculated carrier distributio i the N-

5 c[a/cm ] c[a/cm ] Vce[V] Vg[V] Base regio for the scalig factor k=1 to 5. (c=15a/cm ) k=1 Vge=15.V k= Vge=7.5V k=3 Vge=5.V k=4 Vge=3.75V k=5 Vge=3.V 6 4 I this model, we assumed a coductive modulatio (~) ad o carrier recombiatio i the mesa regio. We also assumed that a art of electro curret flows alog the accumulatio layer beside the trech gate. Figure 6 shows the curret elemets uder the P-base regio. I acc is the electro curret via the accumulatio layer er uit legth for the third directio. mesa ad mesa are the electro curret desity ad hole curret desity i the mesa regio, resectively. cell ad cell are the electro curret desity ad hole curret desity i the N- Base regio, resectively. W x time[us] Figure 4. Calculated iductive tur-off waveforms for the scalig factor k=1 to 5. P-Float P-Base P-Float acc mesa mesa I x 3 x 1.E-3 1.E-4 1.E-5 k=1 k= k=3 k=4 k=5 cell cell N-Base Figure 6. Assumed curret elemets i the trech gate structure 1.E-6 1.E-7 1.E Vce[V] Figure 5. Calculated breakdow characteristics for the scalig factor k=1 to Discussio with the tructure orieted comact model. Cathode side aalytical modellig I this sectio we discuss about the detailed mechaism to obtai lower o-state voltage dro istead of shallower Cathode structures. It ca be exlaied by reviously roosed tructure Orieted aalytical model for the trech gate IGBTs [18]. trie cell structure is assumed i this aer. We review the Cathode side formulatio. Followig relatioshis are held betwee the mesa regio ad N-Base regio. W cell mesa ( x ) ( (1) cell acc mesa W ( x ) I ( ( () The electro curret flowig i the accumulatio layer ca be calculated by the electro quasi- acc I Fermi otetial ad the electro mobility of MO gate. I acc Vg d ( acc ox (3) T ox The electro mobility i the accumulatio layer acc is degraded by the ormal electric field ad ca be calculated by [19].

6 The electro curret desity i the mesa regio ca be formed by the electro cocetratio ad electro quasi-fermi otetial as mesa d ( q ( (4) From the drift-diffusio equatios uder the coductive modulatio coditio, followig differetial equatio for the carrier desity ca be formulated i the mesa regio. mesa mesa d ( ( kt (5) From (1) to (5), we obtai the Cathode side carrier distributio equatio with the structure arameters as oxaccvg 1 Toxq ( qd d W Where cell cell ( x ) ( x ) 1 cell 1 1 ( x ) ad is the total curret desity. (6) (7) 1.1. Theory for IGBT erformace imrovemet The theory for the ricile is delivered from eq. (6). The differetial equatio ca be arraged to the scaled Cathode structures. oxacc( Vg / k) 1 ( Tox / k) q( ( / k) qd ( / k) d k W 1 (8) 1 ' 1 The right had side of (8) is equal to that of (6). For the left had side of (6) ad (8), followig relatioshi is held for k > 1. oxaccvg oxacc( Vg / k) T q ( ( T / k) q ( ( / k) ox ox (9) It leads higher ijectio efficiecy from the Cathode side. ' (1) It leads higher carrier cocetratio i the N-Base Cathode side ad lower o-state voltage dro. It meas the device characteristic imrovemet ca be obtaied by scaled Cathode structure ad alyig same electric field for the gate oxide. Other electrical characteristics are chaged by itroducig the scalig factor k as Table : The gateemitter caacitace C ge is uchaged because T ox =T ox /k ad D =D /k. The gate charge Q g is reduced by the scalig factor k as described before, Q g =Q g /k. The curret desity of the cotact metal Metal is icreased by the scalig factor k, Metal =k Metal because the cotact hole width is reduced by k. Electro migratio should be cosidered for large k structures. Oe characteristic that the ricile fails to scale is the threshold voltage. The threshold voltage V t ca be calculated as followig V t qn i C ox A (11) Where C ox is the gate caacitace er uit area, N A is the accetor cocetratio ad is the surface otetial of the MO chael. V t is reduced because the gate caacitace er uit area is icreased by the scalig ricile as C ox =kc ox. But the V t is ot scaled by k exactly. To adjust the threshold voltage so that keeig scalig ricile, V t =V t /k, the P- Base doig cocetratio at the juctio betwee the N-Emitter ad P-Base should be set as followig. ( kco ( Vt / k ) N A' q i Established scalig ricile is summarized i (1)

7 Table.

8 c[a/cm ] c[a/cm ] Table. Established scalig ricile. Parameters ad Characteristics ymbol calig Factor k Cell Width W 1 Trech-Trech acig 1/k P-Base Deth D P 1/k P-Base Doig Cocetratio CP-Base Eq.(1) Trech Deth D T 1/k Oxide Thickess T ox 1/k Voltage V g 1/k Estimated Resistace R g 1 Electric Field i Oxide E ox 1 -Emitter Caacitace C ge 1 Charge Q g 1/k Curret Desity of Cotact Hole Metal k O-state Voltage Dro V ce (sat) <1 Electro Ijectio Efficiecy γ >1 tored Carrier Desity >1. Further trade-off imrovemet for o-state voltage dro ad tur-off loss As calculated before, the breakdow voltage is imroved by alyig the scalig ricile because arrower trech-trech sacig relaxes the electric field aroud the bottom of the trech. With large scalig factor, the electric field distributio should be closed to that of a ideal oe-dimesioal BT structure. The margi of the N-Base thickess ca be reduced with icremetig k. It leads further erformace imrovemet. TCAD simulatios with adjusted N-Base thickess were erformed. The structure arameters are show i Table 3. The N-Base thickess tn-base is set to obtai similar breakdow voltage of k=1 as show i Figure 7. Calculated I c -V c characteristics are show i Figure 8. As comarig with Figure, o-state voltage dro imrovemet of the reduced N-Base thickess devices are greater tha simly scaled devices. Table 3. tructure arameters used for the scalig ricile verificatio with reduced N-Base thickess. calig Factor k W[um] D T [um] D P [um] [um] T ox [A] V g [V] CP-Base[x1 17 cm -3 ] tn-base[um] E-3 1.E-4 1.E-5 1.E-6 1.E-7 k=1 tn-base=1um k=3 tn-base=11um k=5 tn-base=1um 1.E Vce[V] Figure 7. Calculated breakdow characteristics for scalig factor k=1, 3, 5 with reduced N-Base thickess k=1 tn-base=1um Vge=15.V k=3 tn-base=11um Vge=5.V k=5 tn-base=1um Vge=3.V Vce[V] Figure 8. Calculated I c -V c characteristics for scalig factor k=1, 3, 5 with reduced N-Base thickess. 3. Coclusio We roosed ew scalig ricile for the Trech gate IGBT to make comatibility with the CMO large diameter wafer rocess. By the ricile, the scaled device has shallower trech gate, shallower P- Base ad thier gate oxide. The scaled device ca have rocess comatibility to the CMO with better rocess uiformity ad o wafer bowig. I site of the shallower trech gate, lower o-state voltage dro ca be obtaied by alyig scaled gate voltage which gives same electric field i the gate

9 oxide. The imrovemet was simulated by twodimesioal TCAD ad theoretically roved by referrig our reviously roosed comact model. Additioally, further imrovemet was redicted by reduced N-Base thickess margi. The ricile has large imact to be used for ew IGBT develomet directio. The roductivity should be imroved dramatically because it is formed o the large diameter wafer with smaller thermal budget ad shorter etchig time. P-float P-Base N-Base x ( Aedix: N-Base modellig Figure 9 shows cross-sectioal view of the trech gate IGBT. The N-Base carrier cocetratio ( ca be formulated by the ambiolar equatio that has the carrier lifetime ad diffusio legth L A of high ijectio coditio []. d ( d( L A ( (1) dt For the steady state coditios, the time deedet term is omitted ad the solutio ca be formed as [1] ( L (11) A d x x d x x1 ( x 1) cosh ( x ) cosh LA LA x x1 sih LA where x 1 ad x are the ositios of Aode edge ad Cathode edge of the N-Base regio as show i Figure 9. Eq.11 meas that the N-Base carrier distributio deeds o the differetials of the carrier distributio at both edges. Followig differetial equatio of the carrier desity ca be also formulated i the N-Base regio. kt d (1) N-Buffer P-Emitter Figure 9. O-state carrier distributio The differetials ca be obtaied as follows. d x ( 1 ) kt x 1 x (13) d x ( ) (14) kt where ad are the hole ijectio efficiecy at the Aode side ad the electro ijectio efficiecy at the Cathode side, resectively. ( x 1 ) (15) ( x ) (16) The voltage dro i the N-Base ca be calculated based o the stored carrier cocetratio.

10 V N base kt x 1 d x q xx1 q x x1 1 (17) From these equatios, the o-state N-Base carrier distributio ca be calculated by ad. I the other words, by keeig ad as costats, same carrier distributio ad voltage dro are obtaied eve if the structure is scaled. The scalig ricile is based o this idea. Refereces [1] More-tha-Moore White Paer, ITR, 1. [] M. Kitagawa, I. Omura,. Hasegawa, T. Ioue ad A. Nakagawa, A 45V ijectio ehaced isulated gate biolar trasistor (IEGT) oeratig i a mode similar to a thyristor, IEDM Techical Digest, , [3] M. Harada, T. Miato, H. Takahashi, H. Nishihara, K. Ioue ad I. Takata, 6V Trech IGBT i Comariso with Plaar IGBT A Evaluatio of the Limit of IGBT Performace-, Proc. of 6th iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , [4] T. Takeda, M. Kuwahara,. Kamata, T. Tsuoda, K. Imamura ad. Nakao, 1V Trech-gate NPT-IGBT (IEGT) with Excellet Low O-tate Voltage, Proc. of 1th iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , [5] T. Laska, F. Pfirsch, F. Hirler,. Niedermeyr, C. chaffer, ad T. chmidt, 1V-Trech- IGBT tudy with quare hort Circuit OA, Proc. of 1th iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , [6] R. ittig ad F. Heike, Moolithic bidirectioal switch. I. Device cocet, olid- tate Electroics 44(), ,. [7] R. ittig ad F. Heike, Moolithic bidirectioal switch. II. imulatio of device characteristics, olid-tate Electroics 44(), ,. [8] T. Laska, M. Muzer, F. Pfirsch, C. chaeffer, ad T. chmidt, The Field to IGBT (F IGBT) A New Power Device Cocet with a Great Imrovemet Potetial, Proc. of 1th Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), ,. [9] M. Taaka,. Teramae, Y. Takahashi, T. Takeda, M. Yamaguchi, T. Ogura. T. Tsuoda ad. Nakao, 6V Trech-gate NPT-IGBT with Excellet Low O-tate Voltage, Proc. of 1th Iteratioal ymosium o Power emicoductor Devices & IC s(ipd),. 79-8,. [1] T. Matsudai, H. Nozaki,. Umekawa, M. Taaka, M. Kobayashi, H. Hattori ad A. Nakagawa, Advaced 6um Thi 6V Puch-Through IGBT Cocet for Extremely Low Forward Voltage ad Low Tur-off Loss, Proc. of 13th Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , 1. [11] K. Hamada, T. Kushida, A. Kawahashi ad M. Ishiko, A 6V A Low Loss High Curret Desity Trech IGBT for Hybrid Vehicle, Proc. of 13th Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , 1. [1] M. Baus, M. Z. Ali, O. Wikler, B. ageberg, M. C. Lemme ad H. Kurz, Moolithic bidirectioal switch (MB) - a ovel MO-based ower device, Proc. of 35th Euroea olid-tate Device Research Coferece (EDERC), , 5. [13] A. Nakagawa, Theoretical Ivestigatio of ilico Limit Characteristics of IGBT, Proc. of the 18th Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), essio 1-, 6. [14] M. Baus, B. N. zafraek, t. Chmielus, M. C. Lemme, B. Hadam, B. ageberg, R. ittig ad H. Kurz, Fabricatio of Moolithic Bidirectioal witch (MB) devices with MO-cotrolled emitter structures, Proc. of the 18th Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), essio 6-8, 6. [15] M. Momose, K. Kumada, H. Wakimoto, Y. Oozawa, A. Nakamori, K. ekigawa, M. Wataabe, T. Yamazaki ad N. Fujishima, A 6V uer Low Loss IGBT with Advaced Micro-P tructure for the ext Geeratio IPM, Proc. of the d Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , 1. [16] M. Takei,. Fujikake, H. Nakazawa, T. Naito, T. Kawashima, K. himoyama ad H. Kuribayashi, DB (Dielectric Barrier) IGBT with Extreme Ijectio Ehacemet, Proc. of the d Iteratioal ymosium o Power emicoductor Devices & IC s(ipd), , 1.

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