3. Modeling of MOSFET for analog design. Kanazawa University Microelectronics Research Lab. Akio Kitagawa

Transcription

1 3. Modelig of MOSFET for aalog desig Kaazawa Uiversity Microelectroics Research Lab. Akio Kitagawa

2 SPCE model of MOSFET Model Feature Level 1 Basic physical model(l > 10um Level 3 Basic semi-empirical fittig model (L > 1um, Short-chael effect BSM3v3 Berkeley Short-chael GFET Model, L > 130m BSM4 L < 90m, High frequecy EKV Ez-Krummeacher-Vittoz, High precisio, Sub-threshold regio HiSM Hiroshima-Uiv. STARC GFET Model, L < 90m, High frequecy BSM4: model_ame NMOS/PMOS Level=54 + vto=0.5 + kp=33e-6 model # (The assigmet of model depeds o the + circuit simulator.

3 Model umber Model HSPCE, SmartSpice Berkeley SPCE Level BSM3 49/ BSM BSMSO EPFL-EKV 55 1 HiSMHV1. 73 LTspice NOTE1: terchage betwee Spectre ad SPCE is possible by usig a format idicator for Spectre ad SPCE simulator lag = spice // after here, SPCE format simulator lag = spectre // after here, Spectre format 3

4 (1 DC characteristics of log chael MOSFET 4

5 Dimesioal parameter of MOSFET poly (G cotact S p-active -active B S Field Oxide FOX p+ p-well -sub x j + G L eff D D D + L cotact FOX Cotact W p-well G t m t ox poly FOX FOX p-well -sub W eff The desig parameter of MOSFET is L ad W. L: Gate legth t W: Gate width oxf L eff : Effective chael legth W eff : Effective chael width x j : Juctio depth t ox : Gate oxide thickess t oxf : Field oxide thickess t m : poly-si thickess 5

6 L ad W of MOSFET Aalog circuit: Several times larger L tha miimum L The productio tolerace ad mismatch are improved by usig larger L. The chael oise i MOSFET is suppressed by usig larger L*W. The operatig frequecy rage is decreased by usig larger L. (Disadvatage Very large W/L is required for curret drive stregth of MOSFET. (Disadvatage Logic circuits: Miimum L The DC trasfer characteristic of the logic gate desiged oly i W/L. The small L achieves a small circuit area. The small L achieves a shot delay time. 6

7 Carrier trasport mechaism i MOSFET Weak iversio (Sub-threshold regio Strog iversio (Liear ad Saturatio regio Electro Eergy electro Expoetial -V Diffusio electro S(+ Chael (p D(+ S(+ Parabolic or liear -V Drift Chael (p D(+ Distace from source electrode Distace from source electrode 7

8 V - Characteristic Weak iversio Strog iversio Liear (Triode (1st order VVgs G D S ds Vds V -ch MOSFET Sub-threshold (expoetial Saturatio (d order V V 8

9 V - Characteristic V V V Liear (d order V V V Saturatio (costat VVgs G D S ds Vds V -ch MOSFET V V V Δ OV =V -V V V Sub-threshold V 9

10 Model equatio i liear regio Gradual Chael Approximatio W L {( V C OX {( V V V V V 1 V } 1 V } 1st order for V d order for V : C V OX : : Electro mobility [m /Vs] GOX capacitace per area [F/m ] Threshold V SB = 0 [V] 10

11 Boudary betwee liear ad saturatio regio d dv {( V V V } 0 V V V V V V Liear V V V Saturatio V V V 11

12 Model equatio i saturatio regio Gradual Chael Approximatio + Boudary equatio V V {( V V ( V V V // Boudary betwee liear ad saturatio regio ( V V 1 ( V V } d order for V No depedece o V 1

13 p-ch ad -ch MOSFET The -ch MOSFET ad p-ch MOSFET have a complemetary characteristics. -ch V = V V -ch V Tp V V p-ch V p-ch V = V V Tp : We assume directio flowig ito a drai plus. 13

14 Chael legth modulatio parameter V V V (Saturatig Chael legth = L eff ΔL (ΔL is proportioal to V 0.5 The drai curret icreases gradually after saturatio, because the chael legth is decreasig. ( V V Above-metioed {1 ( V 0V V V Source OV V } Gate p V Drai ΔL V Chael legth parameter (Lambda Pich-off Short L Log L V 14

15 Substrate bias effect Vds VVgs VbsV BS V V FB 1 B Si 0 q N A(B VBS C OX mpurity cocetratio i chael Substrate bias The V shifts upwards for V BS < 0. Some desiger is applyig this effect to cotrol the threshold voltage of MOSFET, but the MOSFET caot operate for V BS > 0. 15

16 Example of simulatio result o V shift V (V V BS (V V 16

17 Substrate bias i the circuit operatio The short-circuit with S ad B of each trasistor prevets substrate bias effect. However, the p-well has to be divided, because the well potetial of M1 ad M is differet. M V BS = 0 V BS < 0 M1 V BS = 0 V BS = 0 No substrate bias Normal coectio 17

18 Sub-threshold Characteristic Very small curret is observed for V V ( 対数 expoetial 1/ Slope S factor V log ( 10 S V 18

19 Model equatio i sub-threshold regio V V W L 0 q ( V V exp{ m k T B } m 1 C C D OX Expoetial for V depeds o the chael width ad temperature. C OX : GOX capacitace per area C D : Capacitace of MOS depletio layer per area 19

20 Model equatio of -ch MOSFET V V V < V -V V > V -V V > V 1 {( V V V} V (Liear ( V ( V V V {1 ( V OV } (Saturatio V < V (V > 0.1V W L 0 q ( V V exp{ mk T B } (Sub-threshold W L C OX 0 C SiO OX 1 t OX m C OX : GOX capacitace per area (F/m 1 C C D OX :Field effect mobility of electro (m /Vsec V > 0 (Ehacemet mode VVgs G D S ds Vds V 0

21 Model equatio of p-ch MOSFET V V V > V -VTp V < V -VTp V < VTp 1 p{( V VTp V} V (Liear p p ( V ( V V V Tp Tp {1 ( V OV } (Saturatio V > VTp (V < 0.1V C p OX W L p p 0 C SiO p 1 t OX OX m C OX : GOX capacitace per area (F/m 1 C C D OX W L p p 0 q ( V V exp{ mk T :Field effect mobility of hole (m /Vsec B Tp } (Sub-threshold V Tp < 0 (Ehacemet mode VVgs G S D Vds V ds 1

22 Gate overdrive voltage Δ OV Saturatio coditio: V > V V T = ΔOV OV V V T C OX W ( L (W/L = cost. = cost. Δ OV V (W/L (W/L Dsat Δ OV V V Δ OV V

23 ( DC characteristics of short chael MOSFET 3

24 fluece of scalig dow to L < 0.3μm Short chael effect The threshold voltage V T is decreased with decreasig L. The three-dimesioal distributio of the electric field i the MOSFET depeds o a aspect ratio of cross sectio. The -V curve shows the liear characteristic i the saturatio regio ad the boudary of liear ad saturatio regio is obscured. The stregth of electric field i the chael is very high ad the electro veracity i the chael is saturated. The leak curret of the sub-threshold regio is icreased. The V cotributes the geeratio of the chael, ad the tuelig curret is icreased with icreasig the electric field of drai edge. The simulatio model cosiderig to the short chael effect have to be used. 4

25 L-depedece of V T fluctuatio of L The fluctuatio of V T is sesitive to the fluctuatio of L of the short chael MOSFET. ΔV T V T Depletio layer + p + L The amout of the charge cotrolled by V is decreased with decreasig L. The impurity cocetratio i chael is equivaletly decreased ad V T is lowered. 5

26 Saturatio of the drift velocity Low electric field: Proportioal to the stregth of the electric field High electric field: Saturated for the stregth of the electric field Drift Velocity (cm/s 10 7 Electro v E Hole Electric Field (V/cm v sat ( V W C L V OX v E v v sat (low E (high E 6

27 Degradatio of S factor 0.35 m 0.5 m Drai Curret (A Decreasig Threshold Voltage creasig Sub-threshold (Cut-off Curret Gate Voltage V (V 7

28 Characteristics of Short chael MOSFET Pich-off voltage Log Chael MOSFET ( V V {1 ( V OV } V d order characteristic for V Short Chael MOSFET W v sat C OX ( V V {1 ( V OV } v sat : Saturatio velocity of the carrier velocity-saturatio voltage V V 1st order characteristic for V V 8

29 (3 Capacitace-Voltage (C-V characteristics 9

30 Parasitic capacitace i MOSFET Overlap Capacitace betwee G-D ad G-S (costat B C OV C GB S G D L Capacitace betwee G-B (depedig o the bias voltage Cross sectio p+ + + p C PN L OV L D p juctio capacitace of D ad S layer (depedig o the bias voltage 30

31 Bias depedece of p juctio capacitace (C PN -1 p-type Potetial V Depletio layer type The ioized door ad acceptor works as a electric double layer capacitor. Forward bias Zero bias Reverse bias V B -V PN V B V B +V PN Positio x The width of depletio layer depeds o the bias voltage. 31

32 Bias depedece of p juctio capacitace (C PN - Model equatio Measured curve C PN Model equatio of C-V characteristic C PN S 0 Si d CPN (0V VPN 1 V B Juctio area Depletio layer width V B : Built-i Potetial ~0.6~0.9V Reverse bias V PN 0 ~0.6V Forward bias NOTE: This equatio is obtaied accordig to depletio layer capacitace, ad caot be applicable to estimate the forward bias capacitace, because the ijected miority carrier play a roll of a electric double layer capacitor (usually large value i the high-level ijectio coditio. 3

33 Bias depedece of MOS (C MOS -1 Electro eergy lieup of the strog iversio for p-substrate MOS for V GB > V Electro eergy qv OX d OX Depletio layer q φ S V GB = V OX +φ S C OX C S V GB qv GB Gate electrode SiO p-type Si Chael Depletio layer C OX : GOX capacitace per area C S : Depletio layer capacitace per area V GB V OX ox COX S si CS Equivalet circuit V GB V OX OX COX S C C S S V GB 33

34 Bias depedece of MOS (C MOS - the weak iversio for p-substrate MOS for V GB < V Depletio layer ad GOX capacitace per area C S OX 0 Si xd 0 t OX SiO C Total capacitace 1 CMOS 1 1 C C OX S Width of depletio layer xd S C 0 SiS qn OX A COX C S V GB 34

35 Bias depedece of MOS (C MOS -3 C-V characteristic of MOS capacitor C C MOS CMOS C OX 1 C OX 1 C S 1 ( V GB C C OX The depletio layer width caot grow aymore with icreasig V GB i the strog iversio coditio, ad Cs is fixed at Cs(V. C MOS 1 C OX 1 C S 1 ( V 0 V V GB 35

36 terelectrode capacitace of MOSFET B C OX S G D C ov C gs = C ov + (V C OX C gd = C ov The variable α(v depeds o the bias coditio. α(v ~ /3 i the strog iversio coditio (liear regio ad saturatio regio. p+ C j ( V + + p ~3 C j 1 (0 V B C ds = C j 36

37 Model of iterelectrode C GD D C DB capacitace G C S C GB C SB B Capacitace idepedet o bias CGDO: G-D overlap capacitace CO: G-S overlap capacitace CGBO: G-B overlap capacitace Label Sub-threshold regio Liear regio Saturatio regio C GD CGDO*W 0.5*C OX *W*L CGDO*W C DB C j *W*L D C j *W*L D C j *W*L D C GB C OX *W*L eff CGBO*L CGBO*L C CO*W 0.5*C OX *W*L /3*C OX *W*L C SB C j *W*L S C j *W*L S C j *W*L S 37

38 (4 AC characteristics 38

39 Biasig for MOSFET operatio Aalog circuit operates with biasig The DC bias is applied to perform The MOSFETs are operated i the saturatio regio ad sometimes i the liear regio ad sub-threshold regio if eeded. The small-sigal parameters are depeds o the bias curret i the saturatio regio. The bias curret is desiged with the circuit parameter V ad W/L. Digital circuit does ot requires the idea of biasig Logic value '1' Liear(p-ch, Sub-threshold(-ch Logic value '0' Liear(-ch, Sub-threshold(p-ch '1' '0' trasitio = Saturatio regio(p-ch ad -ch 39

40 Trascoductace g m -1 The trascoductace g m expresses ability for amplificatio of the MOSFET. Slope = g m V V y 1 g m V NOTE: Small-sigal parameters of p-ch ad -ch MOSFET are give by the same expressio, because the small-sigal parameters coected to the slope of the DC characteristics. Bias V V Bias V = V T + Δ OV 40

41 Trascoductace g m - Bias curret depedece of g m V < V (Sub-threshold regio g m W L W L 0 0 q ( V V exp{ mk T q m k B B } q ( V V exp{ T m k T V > V (Saturatio regio B } liear regio V ds =V gs -V t0 saturatio regio V gs q mkbt V Velocity saturatio MOSFET Log Chael (E sat L >> V -V Short Chael (E sat L < V -V ( V V v WC ( V V g m ( V V V V g m v sat sat WC OX OX 41

42 Trascoductace g m -3 Circuit performace depedig o OV Gai/power ratio g OV g m m ( V V OV V OV OV Small Δ OV is better. Sesitivity for V T fluctuatio V OV OV V V OV Large Δ OV is better. 4

43 Bias curret depedece of g m The previous equatios are simplified assumig m =1. The parameter m is derived from the depedece of C d o V. gm ds q mkt m 1 Cd Cox W Cox L gm/ds gm ds Vgs V T m ds gm gm sat ( 一定 log (gm/ds q ds gm m kt gm gm ds m gm ds gm ds sat log gm termediate 遷移領域 iversio Weak 弱反転領域 iversio Strog 強反転領域 iversio Velocity 速度飽和領域 saturatio log ds 43

44 Optimizatio of Δ OV Δ OV depeds o W/L, ad. g m ad the productio tolerace depeds o Δ OV. Therefore, there is a reasoable rage i a value of Δ OV. The value of V is usually chose amog the rage of OV = 0.15V~0.30V Typically OV = 0.V VT V The rage of OV ~0.V V = V T + Δ OV 44

45 Output coductace g ds g ds i saturatio regio y g ds ( V V V {1 ( V ( V V (V > V -V OV } V =V -V liear regio saturatio regio Slope(liear = g ds Slope(saturatio = g ds V g ds i liear regio y {( V g ds V V V {( V 1 V V } V } (V < V -V 45

46 G y parameters of MOSFET D G S Small-sigal equivalet circuit Cgd Cgs gm vgs gds Cds D i i gs ds y y 11 1 y y y1 y 11 1 y y 1 v v j C g m gs ds gs g 0 ds G Cgs gm vgs gds D S Small-sigal equivalet circuit (C gs icludes C gb g g m ds Simplified equivalet circuit (C gs >> C gd i a saturatio regio S 46

47 h parameters of MOSFET v 1 i 1 gm v1 i D Cgs gds v Cgd G gds Small-sigal equivalet circuit v i 1 h h 11 1 h h h h h h 1 i v 1 1 j C gm j C gs gs g 0 ds whe f T Cgs Trasitio Frequecy f gm C gs S f T, h1 1 ( 0dB where g m depeds o W/L ad (log chael h 1 i i1 v 0 gm j C gs i i 1 j C g m v 1 gs v 1 ( v 0 47

48 Trasitio Frequecy f T The frequecy for the curret gai h 1 = 1 Log chael MOS C g f m T ( V d dv OX C V gs T W L depedig o the bias curret d B dv BE g B m f Short chael MOS g m T _ peak BE v SAT d dv C OX W ( V v gs SAT C OX V W vsatcoxw vsatcoxw vsat C C WL L qv kt BE S ( e 1 q B kt dc d B dv dv BE d d C B q kt T OX idepedet o the bias [Ref.] g m of bipolar juctio trasistor (BJT B h fe q kt C 48

49 RF ad mixed sigal techology tred 1000 Peak Trasitio Frequecy (GHz Bipolar (priority=speed CMOS (priority=low Stadby Power Bipolar (Normal CMOS (priority=precisio Bipoar (priority=high voltage, for RF power amp

50 (5 heret oise 50

51 Quatificatio of the oise PSD: Power Spectrum Desity of oise PSD v oise ( f (V /Hz RMS oise voltage i the bad from f L to f H f f L H v ( f df oise RMS oise power i the bad from f L to f H (V 1 f H R f L v oise ( f df (W 51

52 Source of iheret oise 1. Thermal oise (Johso oise Radom movemet of carrier i all coductive material White oise idepedet o the bias. Flicker oise Radom ioizatio of deep level trap i semicoductors 1/f oise(1/f, where =0.8~1.3 depedet o the bias iversely proportioal to L*W of MOSFET 3. Shot oise (modeled after BSM4 The oise model is implemeted i the device model of the circuit simulators, but a measured parameter may ot be provided by semicoductor maufacture. Statistical fluctuatio of thermal emissio ad tuelig through the potetial barrier i semicoductors White oise proportioal to voltage observed i the short chael MOSFET (t ox < 0m 5

53 Thermal oise of resistor = i oise = 4 4 (A /Hz (V /Hz 53

54 Thermal oise of RC circuit = / 1 1/ 1 NOTE: The RMS of thermal oise v out is limited by the size of the capacitor, ad idepedet of the size of the resistor., Large C suppresses the thermal oise geerated by the resistor, but the time costat of the circuit is icreased. 54

55 Thermal oise of MOSFET PSD of the thermal oise depeds o the coductace. D G i oise iput-referred oise Chael resistace derived with GCA i oise S 4k T 3 B g m PSD of thermal oise i MOSFET (Saturatio regio = 1 (Log Chael > 0.5m (Short Chael < 0.5m v i oise 8kBT oise gm 3gm Normally this equatio is used. 55

56 Limitatio of the gate width PSD of the gate resistace oise v oise 4k T R 4k B G B T R W L PSD of the chael resistace oise v 8k T B oise 3gm W/L is limited accordig to the thermal oise coditio: Gate resistace oise < Chael resistace R W L 3 1 g m g m 56

57 Flicker oise of MOSFET PSD of the Flicker oise depeds o the L*W. Desiged depedig o the process v oise K F C OX 4 5 K F W L ( V 0.8 ~1.3 ( V 1 f F F (-ch (p-ch e Neutral e - oized chael regio Gate poly Gate oxide Semicoductor ds G S D time Quatized Flicker oise of Ultra-arrow-W MOSFET Substrate 57

58 PSD of domiat oise i MOSFET The 1/f oise is a itrisic oise i semicoductors. The thermal oise occurs aywhere i coductor. log( voise Effective oise voltage = v oise f The badwidth of the circuit f should be limited to a sigal bad. PSD 1/f oise Δf ~1MHz Thermal oise log(f 58

59 SNR ad NF Noise stregth mixed i the sigal SNR: Sigal to Noise Ratio Noise voltage SNR( db 0log10 Noise power SNR( db 10log10 V V P P NOTE: The absolute oise stregth is ofte give by the iput-referred oise power (dbm. sigal oise sigal oise Noise stregth geerated i the circuit i s Noise Figure (NF NF( db SNR ( db SNR SNR1(dB gs 1 10log 10 1 G G P oise( output P oise( iput SNR(dB ( db NF depeds o the output coductace g s of sigal source. NF is ormally measured for 1/g s = 50(. 59

60 (6 Productio tolerace 60

61 Fluctuatio of circuit characteristics The circuit characteristics is sesitive to β ad V T of MOSFET Fluctuatio of VT (0.~10mV i a chip because of the fluctuatio of impurity cocetratio Fluctuatio of β (0.1~5% i a chip because of the fluctuatio of field effect mobility ( V VT Stadard deviatio of V T (mv 5 1 V T tox LW 0.0( m LW L*W (m V To suppress the fluctuatio of V T V T 1 crease OV = 0.15~0.3 crease L = ~5 x L mi 61

62 Circuit desig for the productio tolerace Δ / (% V V T V T TOLERANCE 1 V T V Δ OV OV is critical for the productio tolerace. 6

63 Corer Aalysis p-ch MOSFET sf ss typ ff fs Process corers arise from 3- sigma process variatio f: fast s: slow -ch MOSFET NOTE: The term of corer aalysis ofte meas PVT(process, supply voltage ad temperature variatio aalysis too. 63

64 (7 Desig parameters 64

65 Parameters of log chael MOSFET for circuit desig Measuremet of V T ad C OX Measuremet of Δ OV = 0.15 ~ 0.3V 1 ( V T OV d dv gds ( V T OV ( V T OV C OX W L V T V T + Δ OV V ( V T OV OV (Δ OV V = Δ OV +V T Saturatio coditio : V = V T + Δ OV, V = Δ OV NOTE: C OX is equivalet to Kp of the SPCE parameter. Δ OV V 65

66 (8 Scalig of aalog circuits 66

67 Effects of scalig o amplifiers Peak trasitio frequecy: Voltage gai: Gai, if ov = cost. GBP (Gai badwidth product: SNR (Sigal to oise ratio: Power cosumptio: GBP, if g m = cost. SNR(Power 1, if C = cost., if g m = cost. Δ Δ NOTE: The aalytical approach of the amplifier is discussed i later chapters., if GBP ad SNR = cost. 67

68 OV Summary of MOSFET V V T characteristic Gate overdrive voltage for bias desig C OX W ( L Trascoductace ad output coductace for small-sigal desig Calculate the suitable value of D /(W/L g g m ds Note: The device parameters i aalog circuit are specified by the drai curret. 68