Why analog microelectronics?

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Dwain Stanley
5 years ago
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1 hy aalo microelectroics? iital is taki over? Yes, but electrical sials are fudametally aalo! Aalo desi has prove fudametal for hihquality desi of complex systems Mixed-mode systems Natural sials are aalo oud i microphoe Photocells i cameras emperature sesors All real world systems require iterfaci to aalo 1 imitatios of aalo desi upply voltae limitatios ower limit: oise Upper limit: headroom < supply Aimi for active reio 1

2 Upper sial limit Active reio requiremets weak iversio: U stro iversio: 6m at roomtemperature 4-5 U G t( p) Available headroom 1m 8m Upper sial limit from rail voltae max supply eak iversio lower saturatio voltae 3 Upper sial limit Active reio requiremets weak iversio: U stro iversio: 6m at roomtemperature 4-5 U G t( p) Available headroom 1m 8m Upper sial limit from rail voltae max supply eak iversio lower saturatio voltae 4

3 ower sial limit Noise vs. Frequecy eak iversio shot oise tro iversio thermal oise ower sial limit Noise Frequecy depedat hermal oise Flicker oise (F) lo R N Flicker costat / hermal hot lo f 5 imitatios Ratio betwee larest ad smallest sial ial-to-oise ratio max amplitude NR oise amplitude PP 4kR assumi oly thermal oise N NR improves with the square of sial amplitude. Maximize sial swi 6 3

oads esi parameters Explori passive devices apacitors Resistors 7 MO techoloy ayered structure Plaar Plates

4 MO techoloy Basic elemet i microelectroics iital microelectroics MO device used as switch rude ad simple uderstadi Aalo microelectroics MO device used as computatioal elemet urret/voltae relatioship of differet termials imitatios oads esi parameters Explori passive devices apacitors Resistors 7 MO techoloy ayered structure Plaar Plates capacitace ires resistace No pure device Always added parasitics Passive» Resistace» apacitace Active» iodes» Bipolars Mismatch 8 4

5 Aalo microelectroics Masteri devices ad parasitics Explore cotiuous time behavior Example: amplifier Output voltae A time larer tha iput voltae etermie fuctioal limits put voltae rae Output voltae rae Maximum error Frequecy rae Explore physics Available i MO microelectroics eveloped for diital A out i 9 MO trasistor Most importat elemet 3-4 termial device epletio reio Pricipal of operatio Neative ate voltae Accumulated chael capacitor Positive ate potetial chael betwee source ad drai versio Gate voltae for maki a iverted chael hreshold voltae t tp - MO - pmo th 1 5

6 MO trasistor ource referred potetials ource termial: he oe closest to bulk potetial ubstrate voltae for MO Primary characteristics G Gate-source voltae rai-source voltae drai curret source curret ecodary characteristics G ate-drai voltae B bulk-source voltae B bulk curret G ate curret ate ource ad drai completely symmetric G G G G B drai B B B source B, for 11 pmo trasistor ource referred potetials ource termial: he oe closest to bulk potetial ell voltae for pmo Primary characteristics G Gate-source voltae rai-source voltae drai curret source curret ecodary characteristics G ate-drai voltae B bulk-source voltae B bulk curret G ate curret ate ource ad drai completely symmetric G G G G B source drai B B B B, for 1 6

7 MO trasistor efiitios hreshold voltae Reduced with feature size upply voltae t - MO threshold voltae ypical.7 tp - pmo threshold voltae ypical -.9 Effective ate voltae hael chare desity K relative permittivity of silicodiide ( 3.9) t thi ide thickess ε permittivity of free space F m he ates voltae, for which the cocetratio of electros uder the ate is equal to the cocetratio of holes i the substrate far from the ate. Q ( p) G K t t( p) G t( p) 13 MO trasistor Gate capacitace Q s ( p) G t( p) iear chael curret mpose drai-source voltae differece ( ) Resistive, curret icrease with voltae differece Q μ. 6 m s - mobility G t Q chare pr. uit area Oly for close to zero 14 7

8 MO trasistor Pich-off sat G t hael curret idepedet of drai-source voltae Active reio MO-trasistor saturated Ofte desirable i aalo circuits 15 MO trasistor tro iversio behavior First order apprimatio Active reio riode reio G t G G t t 16 8

9 MO trasistor rai curret vs. ate voltae Above threshold ubthreshold G t adece simulatio of AM.35μm NMO trasistor hreshold voltae 17 MO trasistor deviatios hael shortei hael leth modulatio coiciet iear reio aturatio reio k ds Ks qn A 1 k ds G t 18 9

10 MO trasistor deviatios Body ect Back-ate ect, substrate ect urret chae as B is differet from zero Modeled as chae i threshold voltae t t B F t zero biased threshold voltae F qn K A - Fermi potetial F 19 Geeral purpose aalytical model Models preseted i book Aimed for stro iversio Above threshold Uusable i moderate ad weak iversio ubthreshold EK model (ot i book) Ez-Krummeacher-ittoz model Hadles moderate ad weak iversio otiuous trasitio imple Few parameters (BM parameters >65) mportat for uderstadi micropower desi 1

11 MO trasistor models Active reio ow frequecy model oltae cotrolled curret source v m s rascoductace m G t G G Relatio to drai curret G t m m G t proportioal to m 1 MO trasistor models Active reio (cot.) Body ect s ored for B B Output impedace t t B m B F 1 r ds ds Assumi is small 11

MOAPs Gate capacitace s 3 Frii capacitaces Overlap ov s ov 3 ov ource-bulk capacitace (+chael cap whe preset) ' sb A A s ch j 1 B A source area A ch chael area j uit depletio capacitace at build i

12 MOAPs Gate capacitace s 3 Frii capacitaces Overlap ov s ov 3 ov ource-bulk capacitace (+chael cap whe preset) ' sb A A s ch j 1 B A source area A ch chael area j uit depletio capacitace at build i juctio potetial 3 MOAPs cot d rai-bulk capacitace ' j sb A 1 B Gate-drai overlap Miller capacitace d idewall capacitaces jsw ssw P 1 sw P ov Bulk capacitaces B jsw 1 B P () source (drai) perimeter j-sw uit sidewall capacitace at sb ' sb ssw db ' db dsw 4 1

MO trasistor model riode reio Gai ive as

13 MO trasistor model riode reio Gai ive as slope Output coductace G t 1 r ds ds G t is small ad sometimes dropped ds G t 5 hael iversio tro iversio elocity aturatio hreshold curret Moderate iversio eak iversio hreshold voltae NMO AM.35μm process 6 13

Naoelectroics 9m techoloy ( Microelectroics) Miimum trasistor

aturatio eak versio tro/moderate versio elocity aturatio AMO NO

!!!! elocity saturatio i advaced techoloy squeeze stro iversio

t G t elocity saturatio hort ad small devices rascoductace does

14 Naoelectroics 9m techoloy ( Microelectroics) Miimum trasistor simulated with AENE hree differet threshold voltaes elocity aturatio eak versio tro/moderate versio elocity aturatio AMO NO RONG NERON EF!!!!! elocity saturatio i advaced techoloy squeeze stro iversio operatio reio 7 elocity saturatio Active reio tro iversio m G G t G t elocity saturatio hort ad small devices rascoductace does ot icrease with smaller! Maximum frequecy v sat m v sat 7 1 cm s v sat Reduced from square to liear G t 1 3 vsat f G t 8 14

Microelectroics 9 m Miimum trasistor rai curret rascoductace liear elocity saturatio lo 9 he EK MO model 3 parameters (simplest versio) Zero biased threshold voltae

15 Microelectroics 9 m Miimum trasistor rai curret rascoductace liear elocity saturatio lo 9 he EK MO model 3 parameters (simplest versio) Zero biased threshold voltae Gai factor lope factor pecific curret U hael curret F R i F i R 1 U i k q F( R) s(d) F R 6m at room temprature d(s) All potetials referred to bulk l 1 exp U ( ) 3 15

16 16 31 EK MO model eak iversio f tro iversio f R F U i ) ( ) ( exp ) ( ) ( ) ( ) ( R F A cotiuous smoothi fuctio proposed by Ouey (swiss math-uy) for for 1 l / x e x x f e y x x 3 MO saturatio eak iversio expressios rascoductace G G G U U U R U U U R F e e e e e e 4-5 U ) ( G G G G U U U U U 1 exp, exp ive will exp let, exp m

17 MO saturatio tro iversio ( ) rascoductace m ( ) ( ) ( ) ( ) 33 Body ect drai MO-trasistor 4-termial device Back-ate ds b ds s b exp U sb exp s sb U sb sb ate exp s source ( 1) U bulk sb Body ect atural part of model (slope factor) deotes ate iciecy 34 17

18 echoloy implicatios Fier pitch - submicro ower supply voltae Reduced headroom ess power Aalo circuit desi Ofte mixed with diital imited NR Added oise eak iversio uavoidable Eve for diital circuits No stro iversio left! 35 Example: 47 ab trasistors atasheet M147.pdf Exact specificatios ot available Estimated parameters MO: U t =.6 =1.6 μ =.67 ε =8.854e-1 K =3.9 =1 =35 t =35e-1 (hih voltae idicated thick diide) 36 18

19 Measured MO 47 MO trasistor drai-curret ate-voltae Active reio ds =5 hreshold voltae iear Y-axis oarithmic Y-axis 37 Keypoits he source termial of MO lowest voltae he source termial of pmo hihest voltae MO trasistors are close to liear for ds << (triode reio) MO trasistors with ds > have square-law curret vs. voltae mall sial r ds proportioal to /i ds For hih ai, trasistors should be lo ad biased with low rasistors are operatio with expoetial curret vs voltae relatioship for low ate voltaes. urret is flowi eve for ds = For lare trasistor o ito velocity saturatio with liear curretvoltae relatio rascoductace is hihest i weak iversio (liear), deradi to square root i stro iversio, fadi to 1 i velocity saturatio 38 19

20 ayout hapter : self-study or assumed kow Keypoits: A trasistors are differet! Eve with exactly the same layout, ext to each other o the same die ystematics process variatio Radom productio variatios crease with reduced device area Assume % radom variatios i moder processes for small devices Other ects emperature, ai 39

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