High Speed, Low Power Current Comparators with Hysteresis

Transcription

1 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Hih Speed, Low Power urret oparators with Hysteresis Neeraj. hasta hirubhai Abai stitute of iforatio & ouicatio Techoloy, Gadhiaar, Gujarat ABSTRAT This paper, presets a ovel idea for aalo curret copariso which copares iput sial curret ad erece currets with hih speed, low power ad well cotrolled hysteresis. Proposed circuit is based o curret irror ad voltae latchi techiques which produces rail to rail output voltae as a result of curret copariso. The sae desi ca be exteded to a siple curret coparator without hysteresis (or very less hysteresis), where coparator ives hih accuracy (less tha 50A) ad speed at the cost of oderate power cosuptio. The coparators are desied optially ad studied at 180 MOS process techoloy for a supply voltae of 3. EYWORS urret Mode, urret oparator, Hysteresis. 1. NTROUTON Nodal voltaes ad brach currets represets the iforatio carried by ay electric etwork. The forer erred to voltae doai circuits whereas the latter are kow as curret doai circuits. recet years; as supply voltae ad device threshold voltae reductio reatly affected the perforace of voltae doai circuits, curret ode circuits are becoi desier s iterest. urret doai circuits show ay uique ad attractive properties over their voltae ode copleets icludi hiher speed, hiher badwidth, reduced distortio, low supply voltae requireets ad lesser sesitivity to switchi oise. Several curret ode copariso approaches are proposed [5]-[14]. The first MOS cotiuous tie curret coparator was proposed i [5]. t cosists of two cascode curret irrors but ca t operate at hih speeds ad frequecies due to hih output ipedace. To overcoe this proble a ew circuit has bee proposed [] which uses iverter stae i feedback with source-follower stae. But the circuit shows dead bad reio for low values of currets, where iput ipedace is quite hih ad thus liits speed of operatio. The iput ad output ipedaces are further cotrolled by voltae-curret feedback cocept [1], [14]; where a resistive feedback is applied to a voltae aplifier, thus reduci ipedaces ad iprovi speed perforace. urret irror cocept aai used i [15]; where it uses iproved Wilso curret irror for curret copariso, but circuit suffers fro hiher power cosuptio ad delay itroduced by ai circuitry. O : /vlsic

2 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Fi. 1: Existi urret oparators (A) H. Traff s[] (B) R. el s[10] () L. he s[14] (). asesuwa s[15]. OMPARATORS WTH HYSTERESS Z. Wa proposes curret coparator with hysteresis [6] show i fi. t uses three curret sources aely 1, ad hy. 1 ad are iput currets to be copared whereas aout of hysteresis eerated decided by curret hy. Fi. : Z. Wa s oparator (with hysteresis) [6] 86

3 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 This circuit suffers fro soe ajor operatioal probles such as; fuctioality depeds o the diital levels eerated at ode A ad ode B, ad does ot provide ay assistace at the ties of trasitios as both of trasistors M 1 ad M will be i o state. Speed perforace is low; also desi eeds odificatio for zero ad eative values of currets. 3. RUT ESRPTON Here a ew copariso schee is proposed which cosists of three staes: the iput preaplifier, a positive feedback latch stae ad a output iverter. The preaplifier stae allow the iput currets to flow throuh it ad develop correspodi voltae at iput odes which results i ters of curret output by curret irrori cocept. t also isolates the iput of coparator fro switchi oise ( kickback oise) coi fro positive feedback stae. The latch stae deteries which of the iput sial is larer by positive feedback actio. t is also called as decisio aki stae. The iverter stae aplifies the iforatio provided by decisio stae ad outputs a MOS copatible voltae sial (0 or ). Fi. 3: Proposed urret oparator Worki: osider the case whe is costat ad i chae fro low to hih. A costat will keep ode B at costat voltae ad allow M 6 to supply a costat drai curret ( ) to latch circuit. O the other had chae i i will ake ode A voltae varyi ad so the ate voltae of M 5. As i icreases, A icreases ad thus reduces the drai curret ( 1 ). This decrease i 1 will reduce curret throuh M ad so the voltae at ode ( ). This chae will affect the curret throuh M ad as is costat, curret throuh M 10 will icrease. As drai curret of M 10 is icreasi, ( s ) of M 10 will icrease ad so voltae at ode ( ), positive feedback actio ives produce ore reductio i drai curret of M ad hece i. ariatios at ode are applied to iverter circuitry which results i MOS copatible rail to rail output voltae. The circuit uses positive feedback fro the cross-ate coectio of M 8 ad M to icrease the ai of latch circuitry (As circuit is syetric = 10 & 8 = ). But if s of all the latch trasistors are ot equal, will lead circuit to show hysteresis property. This we ca easily aalyze by sall sial aalysis of latch circuitry. 8

4 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February Fi. 4: Positive Feedback Latch ircuit [] The expressios for ode voltae A ad B are as (where = 10 & 8 = ): = 1 A Ad, = 1 B Both the equatio shows that circuits will lead to hysteresis property (if s of trasistors M ad M are ot equal). The lare sial () aalysis expressios for ode voltae at A ad B would be as: + = 1 t A Ad, + = 1 t B Here we have expressios for A ad B i lare ad sall sial aalysis, ad ca see that i positive feedback cofiuratio ( < ) circuit will show hysteresis. Fro the discussio above we ca see that for proposed desi: ( ) ( ) + = i p p th..(a) Ad, ( ) ( ) + = i p p th..(b) Here both the equatios show that proposed circuit will produce hysteresis i output voltae with respect to applied iput currets ad hysteresis produced depeds o drai curret of M ( ). The exact calculatio of hysteresis eerated is explaied i ext sectio.

5 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February ALULATON OF HYSTERESS As we are usi positive feedback latch circuit, at the tie trasitios oe of the cross coupled trasistor will o i triode reio ad so the aout of hysteresis itroduced will also deped o the drai voltaes of M 8 ad M ( ad respectively). Whe curret chaes fro low to hih values at the tie of switchi trasistor M 8 will be i triode keepi all other trasistors i saturatio. So the ratio of drai currets of M 5 ad M 6 ca be ive by: 5 6 = ( ) + ( ) t ( ) + ( ) t t t = P As 5 ad 6 are irrored by M 3 ad M 4 respectively, so 5 6 = 3 4 = P Appli L at iput odes A ad B, we ca easily see that i = + P 1 put curret i equatio (3.36), ive the value of curret at the tie of trasitio ad it ca be erred as trasitio curret ( t1 ). Sae ca be doe for reversed case; whe curret chaes fro hih to low values, this tie trasistor M will o i triode reio ad iput sial curret at the tie of switchi ca be ive by ( t ): Where P ' ca be ive by, i = + P ' 1 P ' = ( ) + ( ) t So we have trasitio currets expressios as, ( t ) + ( t ) t = + t1 = + 1 P a ' ( P ) = b t = 1 Equatios derived above ca be ipleeted raphically i hysteresis curve as: 8

6 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Fi. 5: Hysteresis urve ( v/s i ) The hysteresis curret ca be ive by hy = t1 t hy = P ' P Equatio shows the expressio of hysteresis produced by circuit; where we see that it is well cotrolled as drai curret of M ( ) is always costat (see fi.3 M ad M 4 are diode coected ad o curret chai eleet is available). eepi equatios (A) ad (B) i id; we see that whe all the trasistors are i saturatio, aout of hysteresis produced depeds o the Ratio of s. f we set this ratio ear to 1; so that ter approxiately et cacelled with, ad thus aout of hysteresis 1 itroduced ca early be set to zero. This we ca uderstad i other way aroud that if we desi this circuit i such a way that s of all the latch trasistors be early equal ( or ) hysteresis produced ca be reduced to zero. As we have already discussed that hysteresis itroduced directly relates with depth of positive feedback (differece of s), the this will be the coditio whe circuit will have a sliht positive feedback ad so very less hysteresis. Uder such stipulatios circuit ca also be used as a siple curret coparator. 5. SMULATON RESULTS For siulatio, stadard BSM 0.18µ MOS techoloy paraeters have bee used with 3 power supply. Proposed circuit was desied optially for speed, power, accuracy ad hysteresis. 0

7 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 oparator with hysteresis: The desi proposed produces hysteresis i output voltae with respect to the chae i directio of iput curret. trasfer characteristics observed with icreasi ad decreasi values of iput currets are show i Fi. 6 & respectively. Fi. 6: Hysteresis for creasi value of i ( = 0µA) Fi. : Hysteresis for ecreasi value of i ( = 0µA) Here i fiures, we see that switchi of output occurs at 0.µA (Fi. 6) ad -0.65µA (Fi. ) depedi o the directio of chae i curret. So total aout of hysteresis produced: hy = 0.µ A + 0.µ A = 1. 4µ A ircuit produces averae propaatio delay of 0.s ad 4.8s for +/- 100µA ad +/- 1µA iput square-wave curret pulses respectively, at the power cosuptio of 1.8W. Trasistor diesios used are as: 1

8 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Table 1: esi Paraeters: oparator with Hysteresis W (Width) L (Leth) M1, M 0.18µ 0.µ M3, M4 0.54µ 0.µ M5, M6 1.08µ 0.18µ M8, M 0.36µ 0.18µ M, M10 0.µ 0.18µ verter: 0.54µ 0.18µ PMOS verter: NMOS 0.18µ 0.18µ oparator without hysteresis: The sae desi could be exteded to coparator without (or very less) hysteresis i output voltae with the chae i directio of iput curret. trasfer characteristics obtaied for exteded cocept with icreasi ad decreasi values of iput currets are show i Fi. 8 & respectively. Fi. 8: Hysteresis for creasi value of i ( = 0A)

9 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Fi. : Hysteresis for ecreasi value of i ( = 0A) Here, we see that for this desi switchi of output does t uch affected by the directio of chae i curret as the trasitio poits are at A (Fi. 8) ad -A (Fi. ) with risi ad falli values of iput curret, respectively. This is just because of very less positive feedback. Total aout of hysteresis produced: hy = A + A = 18A ircuit produces averae propaatio delay of 0.s ad 1.6s for +/- 100µA ad +/- 1µA iput square-wave curret pulses respectively, at the power cosuptio of.3w. Trasistor diesios used are as: Table : esi Paraeters: oparator without Hysteresis W (Width) L (Leth) M1, M 0.18µ 0.µ M3, M4 0.18µ 0.µ M5, M6 1.1µ 0.18µ M8, M 0.34µ 0.18µ M, M10 0.1µ 0.18µ verter: 0.54µ 0.18µ PMOS verter: NMOS 0.18µ 0.18µ To copare the perforace of proposed coparator (without hysteresis case) with existi low power coparators i.e. Traff s [], R. el s [10], L. he s [14] ad. asesuwa s [15], LTSPE siulatios of all coparators are perfored usi stadard BSM 0.18µ MOS techoloy paraeters with 3 power supply. 3

10 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Fi. 10: Averae elay (s): Respose to +/- 1µA urret Step Fi. 11: Averae elay (s): Respose to +/- 100µA urret Step 6. ONLUSON A ew curret ode coparator with hysteresis is preseted. esi have ovel structure ad able to achieve crucial paraeter of hysteresis cotrol. t is havi aaloous fuctioality ad far better perforace over the existi oe i ters of speed ad hysteresis cotrol. The sae desi ca be exteded to a siple curret coparator, which copares iput sial ad erece currets with hih accuracy (less the 50A), hih speed ad coparable power cosuptio with all existi low power coparators. 4

11 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 ANOWLEGEMENT sicerely thak Prof. heta Parikh for his valuable uidace i the study of oparators. REFERENES [1]. A. Freitas ad. W. urret, MOS curret coparator circuit, Electro. Lett., vol. 1, o. 1, pp. 65-6, Auust 183. [] Z. Wa ad W. Guebuhl, MOS curret Schitt trier with fully adjustable hysteresis, Electro. Lett., vol. 5, o. 6, pp. 3-38, March 18. [3] H. Traff, Novel approach to hih speed MOS curret coparators, Electro. Lett., vol. 8, o. 3, pp , Jauary 1. [4] A.T.. Ta ad. Touazou, Hih Perforace MOS curret coparator, Electro. Lett., vol. 30, o. 1, pp. 5-6, Jauary 14. [5] M. Bracey ad W.R. White, esi cosideratios for curret doai reeerative coparators, EEE teratioal oferece o Advaced A- ad -A oversio Techiques ad their Applicatios, July 6-8, 14. [6] R. Feradez, G. ebrao, R. astro ad A. azquez, A Misatch-sesitive Hih-Accuracy Hih-speed otiuous-tie urret oparator i Low oltae MOS, EEE Proc. Aalo ad Mixed Sial esi, pp , Septeber 1. [] L. Ravezzi,. Stoppa ad G.-F. alla Betta,"Siple hih-speed MOS curret coparator," Electroics Letters, vol.33, o., pp , 3 Oct 1. [8] B.M. Mi ad S.W. M, Hih perforace MOS curret coparator usi resistive feedback etwork, Electroics Letters, o1.34, N0., pp.04-06, 18. [] L. Luh, J. hoa Jr. ad J. raper, A Hih-speed Hih-Resolutio MOS urret oparator, EEE Proc. Electroics, ircuits ad Systes, vol. 1, pp , Auust 1. [10] L. he, B. Shi ad. Lu, A Hih Speed/Power ratio cotiuous tie MOS curret oparator, EEE Proc. Electroics, ircuits ad Systes, vol., pp , eceber 000. [11]. asesuwa ad S. hucharoesi, Hih Speed Low put pedace MOS urret oparator, EEE Tras. Fudaetals, vol. E88-A, o. 6, pp , Jue 005. [1]. A. Johs ad. Marti, Aalo iterated circuit desi. Joh Wiley & Sos, 1. [13] R. J. Baker, MOS: ircuit desi, layout ad siulatio, d ed. Joh Wiley & Sos, 00. [14] B. Razavi, esi of aalo MOS iterated circuits. dia: Tata McGraw Hill, 00. [15] F. Yua, MOS curret-ode circuits for data couicatios. Sprier,

12 teratioal Joural of LS desi & ouicatio Systes (LSS) ol.3, No.1, February 01 Authors Neeraj. hasta received his B. E. eree i Electroics & ouicatio fro Uiversity of Rajastha, Jaipur, dia i 00, ad the M. Tech deree i foratio & ouicatio Techoloy with specializatio LS fro hirubhai Abai istitute of foratio & ouicatio Techoloy (A-T), Gadhiaar, dia i 010. His curret research iterests are i aalo & ixed sial desi with low power & hih speed ephasis & LS Testi. 6