COMBINED SKEWED CMOS RING OSCILLATOR

Transcription

1 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 OMBINED SKEWED MOS RING OSIATOR Sadegh Biabaifard, S. Mehdi Hosseii argai ad Shahrouz Asadi 3, Microelectroic ab, Shahid Beheshti Uiversity, G., Tehra 3 Faculty of Electrical Egieerig, Shahid Beheshti Uiversity, G., Tehra ABSTRAT A combied skeed rig oscillator by differet type of delay stages is preseted. This paper aims to drive a high stable ad relatively high frequecy but still use a full trasistor circuit for rig oscillator ith combied delay stages ad skeed coectios. First e propose to types of commo iverters the calculate their delay time ad aalysis their depedece of delay time to variatio of poer supply voltage. The simulatio results verify that delay time of these to MOS iverters sho opposite behaviour versus poer supply chagig. So a combied structure ca obtai more appropriate frequecy stability versus poer supply oise. Also i order to icrease oscillatio frequecy e have used the egative skeed delay coectios. The simulatio results usig HSPIE for 0.8 m MOS shos a good agreemet ith aalysis results. I additio i this paper the mathematical justificatio for improved fuctioig of this combied skeed rig oscillator has bee proved. This justificatio shos appropriate agreemet ith the simulatio results. From mathematical poit of vie the proposed rig oscillator has better frequecy stability i compariso ith other types of rig oscillators. I fact, the oscillatio frequecy sesitivity to supply voltage oise is reduced cosiderably. KEYWORDS MOS, rig oscillator, frequecy stability, delay time. INTRODUTION Oscillators are the essetial part of ay digital ad aalog systems [, ]. Ad rig oscillator is a circuit usually uses trasistors ith usig passive elemets [4]. The mai reaso of the tedecy to desig full trasistor MOS circuits is the ability of easy itegratio ith absece of passive elemets hich reduces the die area [-0]. The most sigificat feature of a rig oscillator is loer cost due to loer die area ad desig simplicity [, 4, 5]. Hoever the highest possible oscillatio frequecy is loer for rig oscillators tha oscillator, egative skeed delay coectios ca improve the speed of rig type oscillators. Several desigs for rig oscillator have bee reported i literature. I [], a frequecy stable oscillator is desiged based o the opposite directio of delay time chagig, hich icrease frequecy stability but oscillatio frequecy reduce due to usig curret starved iverter. I [6] a method to ehace frequecy operatio of rig oscillators by egative skeed delay coectios preseted. Overall, most of the reported rig oscillators caot improve both frequecy stability ad oscillatio frequecy. I this paper a ovel desig as combied skeed rig oscillator is preseted to improve frequecy stability a oscillatio frequecy simultaeously. Usually a sigle eded rig oscillator ca be implemet usig odd umber of delay stages (Fig.. osiderig oscillatio criterio the loop gai must be equal or bigger tha uity ad also the DOI : 0.480/ecij.05.40

2 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 loop gai must be egative hich odd umber of iverters ca satisfy these coditios. By assumig that all stages are similar e ca extract oscillatio frequecy from (. g mr A ( jω A ( jω AN ( jω + jωr ( ω ( ω ( ω A j. A j.. A j N ( ( ( A jω θ ta ωr K π R Fig.. A typical rig oscillator by odd umber of iverters [] Fig.. geeral liear model of a rig oscillator [] The above equatio ca leads us to estimate oscillatio frequecy i iitial stage of oscillatio but the stable oscillatio frequecy ca be obtai from large sigal aalysis ot from small sigal mode i fig., sice the start oscillatio frequecy is differet ith stable oscillatio frequecy. A stage is a iverter ad has t d secods delay. Sice the similarity betee stages is assumed, oscillatio frequecy ca be obtaied as (. f 0 Nt d ( I ( e assume that N is a odd umber ad illustrates the umber of delay stages. I fact the startig frequecy of oscillatio is determied by Barkhause criteria ad stable oscillatio frequecy specified by iverters delay time []. Accordig to ( oscillatio frequecy strogly depeds o delay time of delay stages. Also koig that the umber stages i a fixed structure is costat the the most sigificat parameters for oscillatio frequecy calculatio is delay time. To cofiguratios for five stage covetioal rig oscillator are sho i fig.3 ad fig.4. Accordig to fig.4 e have a optio to chage the oscillatio frequecy by adjustig ctrl, so by usig curret starved iverter, voltage cotrolled oscillator ca be desiged.

3 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 Fig.3. Five stage basic rig oscillator Fig.4. Five stage urret Starved rig O I this paper e ve calculated the delay time of basic ad urret Starved iverters ad based o the equatios a combied skeed rig O ill be preseted.. DEAY TIME OF INERTERS Geeral coditios of rig oscillators ere discussed i previous part. I this sectio delay time calculatios are preseted sice this parameter is the oly parameter hich ca determie the oscillatio frequecy. By assumig to types of iverters, basic type iverter ad curret starved iverter (Fig.5.By applyig a ideal pulse to both of these iverters, e obtai the put sigal depicted i Fig.6. Details of calculatios are brought i the appedix A. + t PH PH delay PH t t 0 PH t 5 t 3 ( α PHbasic c W ( th mos α β + l W c ( β th mos γ PHbasic W ( pc th pmos (3 3

4 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 β + l W pc ( β thpmos γ + PHS ( α c W GS th mos ( + γ PHS c W ( th mos ( p SG th pmos ( l p th pmos α β l β β γ β (4 Fig.5. Basic iverter (a ad urret Starved iverter (b Fig.6. Iput ad put of iverters 4

5 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 I the other ord: t Basic & t urretstarved As ca be see e ca coclude that delay time of these to iverters sho differet behaviour versus poer supply chagig. Accordig to (3 ad (4 delay time of basic iverter depeds o poer supply chagig i opposite directio hich delay time of curret starved iverter depeds o poer supply chagig. By cosiderig this fact it is obvious that combied rig oscillator depicted i fig.7 ca provide more stable oscillatio frequecy versus poer supply variatio. The hole loop delay i this type of oscillator ca be itroduce as sum of all delay times. I this case first ad fifth stages are basic type iverters ad other stages are curret starved iverters. By summig these delay times the total delay time is less sesitive to poer supply variatio i compariso ith basic type iverter delay time or curret starved iverter delay time. t d t + t + t + t + t d d d 3 d 4 d 5 (5 Fig.7. ombied rig O The, if all iverters are the same type,, ill have the same variatio. Meaig that all become smaller or bigger. I the other ords chagig oscillatio frequecy is ievitable. But i combied structure to types of iverters sho opposite behaviours to poer supply chagig hich cosiderably reduces the depedece of hole circuit to poer supply oise. Hoever combied rig O has the loer oscillatio frequecy compared ith simple rig oscillators. By usig NSD stages e ca icrease oscillatio frequecy of combied rig O. 3. NEGATIE SKEWED DEAY SHEME I covetioal iverters both PMOS ad NMOS have the same iput sigals. NSD is a techique that reduces delay of iverters. Fig.8 shos the cocept of NSD. I fact i NSD iverter iput sigal to PMOS arrives earlier tha to the NMOS ad put chagig become faster as illustrated i fig.8.[6]. By usig NSD stage to desig a rig oscillator e eed to modify the coectios as sho fig.9. Also for combied rig O the circuit of fig.0 is suggested. The miimum umber of stages i 5

6 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 skeed rig oscillator is five because he the umber of stage is tree, the skeed rig oscillator yields a PMOS diode- coected load. By usig NSD coectio for combied rig oscillator e ca compesate decreased oscillatio frequecy by chagig cofiguratio. Fig. 8. NSD iverter Fig. 9. Skeed rig oscillator Fig. 0. Proposed ombied Skeed rig O 6

7 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue SIMUATION RESUTS I order to validate the previous discussio, five structures i fig.3, fig.4, fig.7, fig.9 ad fig.0 have bee simulated ith HSPIE usig TSM 80 m techology. The omial supply voltage ad ctrl have bee selected equal to.8 ad.5 respectively. Also a factor as frequecy deviatio is defied i [] to compare operatioal performace of simulated circuits. This factor is described i (6. ( + ( f ( f f f f ( 6 I this defiitio f ( + is the oscillatio frequecy he supply voltage is + []. Fig. shos frequecy deviatio factor for five rig oscillator that obtaied from simulatio. Ad table. presets a compariso betee these five type rig oscillators. The simulatio results verify the aalysis ad mathematical justificatios sice simple combied structure ad combied structure ith NDS coectios sho cosiderable reductio i frequecy deviatio factor. I additio usig NDS coectio icreases the oscillatio frequecy for combied rig oscillator from 960MHz to 3.3GHz. The proposed combied skeed rig oscillator is a O due to usig curret starved iverter. Table. reports the importat parameters for simulated oscillators. Accordig to this table the proposed rig oscillator ca ork i higher frequecies ith loer frequecy deviatio i compared ith simple structures. Fig.. Frequecy deviatio factor of five rig oscillators. 7

8 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 Tab.. Simulatio results for five type rig oscillators 5. ONUSION Rig oscillators are oe of the basic blocks of itegrated circuits. This paper presets to types of MOS iverters ith detailed delay time calculatios ad the suggests combied structure for implemetig a efficiet O regardig frequecy deviatio. Oscillatio frequecy of combied rig O is lo i respect to simple oe. For icreasig oscillatio frequecy e used NSD stages i combied structure that sigificatly icreased oscillatio frequecy. The results of simulatio by HSPIE for 0.8m MOS approve the aalysis results. Accordig to simulatio results the proposed O ca ork i higher frequecies ith less frequecy deviatio. A.. Appedix A α th mos β γ th pmos I order to calculate delay time of Basic type iverter (Fig.5 (a e ca rite: for t < t < t mos saturatio 0 W ( d I D i I th mos dt for < < th mos α 0 < α < th m os t dt d I t0 α D 8

9 t t0 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 dt t t 0 ( α th mos ( α c W th mos ( t < t < t mos iear I W ( d D i th mos ( A W d ( dt i th mos for < th t t β dt d I t t dt α D β W ( th mos α α β t l ( A W ( β th mos t ( ( PH t t t t + t t ( ( 0 0 yields A + A PH PH ( α c W th mos ( d α β + l W c ( β th mos or PH t t t t + t t PH ( ( γ pc W th pmos ( β + l W pc ( β thpmos The A A A A t Basic γ 3 4 A Where, A, A 3, A 4, are costat value as follo: A ( α W c 9

10 A A A Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 α β l W c β 3 4 γ W pc γ β l W pc β to calculate delay time of urret Starved iverter (Fig.5(b e ca rite equally. t 0 < t < t [ ],, i th M 3 saturatio, M saturatio M 4 cut off for < < th mos I W ( D GS th mos dt t t0 ( GS th mos α dt d I D ( GS th mos d Ko that cte t dt t0 ( GS th mos ( α α d t t 0 ( B ( GS th mos for t < t < t M 3 liear, M saturatio I ( D 3 GS 3 th mos DS 3 DS 3 I ( D GS th mos 0

11 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 I I D 3 d dt for < th mos t β dt d I t α D 3 t t dt β ( α GS 3 th mos DS 3 DS 3 ad t t DS 3 DS GS 3 i dt β ( th mos α t t l ( B α β ( th mos β PH t t t t + t t ( ( + or ( ( 0 0 yields B + B PH PH ( α c W GS th mos ( ( th mos α β l β PH t t t t + t t PH ( ( γ W pc SG th pmos ( d d + ( l p th pmos The β γ β B t urretstarved B + + B + follo: B 4 3 ( α c W GS th mos ( B here B, B, B 3, B 4, are costat value as

12 B B B Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 α β l β 3 γ W pc SG th pmos 4 p Or e ca rite: ( β γ l β B + B 3 > B + B 4 Sice 0 < < GS, SG th, p GS, SG th, p ( α ( α > ( GS th ( α α β > l ( GS th β γ β γ > l p ( SG th pmos p β The B > B & B > B 4 B > B & B > B So B + B 3 > B + B 4 I summary t Basic t urretstarved

13 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 REFERENES [] G. G. Jovaovi c, M. Stojˇcev, Z. Stamekovic. A MOS oltage otrolled Rig Oscillator ith Improved Frequecy Stability. Scietific Publicatio of the State Uiversity of NOI PAZAR ser. A: APP. MATH. INFORM. AND MEH. vol., 00. [] B.Razavi. RF Microelectroics. Pretice Hall PTR, 997. [3] B. Razavi. Desig of Aalog MOS Itegrated ircuits. MacGra-Hill,00 [4] G. Jovaovi c, M. Stojˇcev. urret starved delay elemet ith symmetric load. Iteratioal Joural of Electroics, ol. 93, 3, 006. [5] Yao WANG, Jiaxi IU, iagbo XIE, Guagju WEN. A Ultra-o-Poer Oscillator ith Temperature ad Process ompesatio for UHF RFID Traspoder. RADIOENGINEERING, O., NO., JUNE 03, [6] Aimad El Mourabita, Guo-Neg ub, Patrick Pittetb, A e method to ehace frequecy operatio of MOS rig oscillators, Iteratioal Joural of Electroics, ol. 99, Issue 3, 0, [7] Wo-tae eea, Jaemi Shima, Jichai Jeogb, Desig of a three-stage rig-type voltage-cotrolled oscillator ith a ide tuig rage by cotrollig the curret level i a embedded delay cell. Microelectroics Joural, olume 44, Issue, December 03, [8] Seugji Kim ; I-Youg ee ; Seok-Kyu Ha, A o-noise Four-Stage oltage-otrolled Rig Oscillator i Deep-Submicrometer MOS Techology. IEEE Trasactios o ircuits ad Systems. 03, ol.60, [9] S. Dockig, M. Sachdev. A Aalytical Equatio for the Oscillatio Frequecy of High-Frequecy Rig Oscillators. IEEE Joural of Solid State ircuits, vol.39, 3, 004, [0] Yalci Alper Eke ad Joh P. Uyemura, "A 5.9-GHz voltage-cotrolled rig oscillator i 0.8- m MOS" IEEE J. Solid-State ircuits, vol. 39 o., Ja [] Ramazai A, Biabai S, Hadidi G, MOS rig oscillator ith combied delay stages. It J Electro ommu (AEÜ (04. [] Akbari, M., Biabaifard, S., Asadi, S., & Yagoub, M.. (04. Desig ad aalysis of D gai ad trascoductace boosted recyclig folded cascode OTA. AEU-Iteratioal Joural of Electroics ad ommuicatios, 68(, [3] argai, H., Mehdi, S., Shahsavari, S., Biabaifard, S., & Jalali, A. (04. A e frequecy compesatio techique for three stages OTA by differetial feedback path. Iteratioal Joural of Numerical Modellig: Electroic Netorks, Devices ad Fields. [4] Shahsavari, S., Biabaifard, S., argai, S. M. H., & Hashemipour, O. (05. DII based frequecy compesatio method for three stage amplifiers. AEU-Iteratioal Joural of Electroics ad ommuicatios, 69(, [5] Shahsavari, S., Biabaifard, S., argai, S., & Hashemipour, O. (04, May. A e frequecy compesatio method based o differetial curret coveyor. IElectrical Egieerig (IEE, 04 d Iraia oferece o (pp IEEE. [6] Akbari, M., Biabaifard, S., Asadi, S., & Yagoub, M.. (05. High performace folded cascode OTA usig positive feedback ad recyclig structure. Aalog Itegrated ircuits ad Sigal Processig, 8(, 7-7. [7] Biabaifard, S., Aghaee, T., & Asadi, S. Adesig GUIDE FOR OMPARATOR-BASED SWITHED-APAITOR INTEGRATOR. [8] Biabaifard, S., argai, S. M. H., & Asadi, S. DEAY TIME ANAYSIS OF OMBINED MOS RING OSIATOR. [9] argai, S., Shahsavari, S., Biabaifard, S., & Jalali, A. (04, May. A e SM compesatio strategy for three stage amplifiers based o differetial feedback path. I Electrical Egieerig (IEE, 04 d Iraia oferece o (pp IEEE. [0] Akbari, M., Biabaifard, S., & Hashemipour, O. (04, May. Desig of ultra-lo-poer MOS amplifiers based o flicker oise reductio. I Electrical Egieerig (IEE, 04 d Iraia oferece o (pp IEEE. 3

14 Electrical & omputer Egieerig: A Iteratioal Joural (EIJ olume 4, Number, Jue 05 AUTHORS Sadegh Biabaifard as bor i Tehra, Ira i 989. He received the B.Sc. degree i Electroics Egieerig from Imam Reza Iteratioal Uiversity, Mashhad, Ira i 0ad M.Sc. degree i Aalog Electroics from Shahid Beheshti Uiversity, G.., Tehra, Ira, i 04. His research iterests are RFI desig, aalog ad mixed mode itegrated circuits desig for Ultra-o-Poer Ultra-o-oltage applicatios, OTA, curret coveyer ad data coverter. S. Mehdi Hosseii argai as bor i Toekabo, Ira i 989. He received the B.S. degree i otrol Egieerig from K.N.Toosi Uiversity of Techology, Tehra, Ira i 0 ad M.S. degree i Aalog Electroic from Shahid Beheshti Uiversity (Natioal Uiversity of Ira G.., Tehra, Ira, i 04. His research iterests are aalog ad mixed mode circuit theory, itegrated circuit desig for Ultra-o-Poer Ultra-o-oltage applicatios. His is curretly ith Electrical Egieerig Departmet ad Microelectroic Research aboratory i Shahid Beheshti Uiversity, G., Tehra, Ira. Shahrooz Asadi received the B.Sc. degree i Electrical Egieerig ad the M.Sc. degree i Electroics both from Amirkabir Uiversity, Tehra, Ira, i 003 ad 007, respectively ad the Ph.D. degree i Electroics i the School of Iformatio Techology ad Egieerig (SITE, Uiversity of Ottaa, Ottaa, ON, aada. He joied shahid Beheshti Uiversity i 0 here he is a assistat professor. His research iterests iclude liear ad oliear time-domai modelig of millimeter-ave trasistors, RF desig of active ad passive devices, desig ad optimizatio of solid state devices ad multicoductor trasmissio lies ad prited circuit board. 4