Efficient Reverse Converter Design for Five Moduli

Transcription

1 Joural of Computatios & Modellig, vol., o., 0, ISSN: (prit), (olie) Iteratioal Scietific ress, 0 Efficiet Reverse Coverter Desig for Five Moduli Set,,,, MohammadReza Taheri, Elham Khai, Mohammad Esmaeildoust 3 ad Keiva Navi 3 Abstract I this paper, ew desig of reverse coverter for the five moduli set,,,, whe has eve values is preseted. The proposed reverse coverter is desiged i two levels architecture. I first level subset,,,, is calculated by employig New Chiese Remider Theorem-I (New CRT-I) ad calculatio of subset ) ( ), ( i secod level is based o Mied Radi Coversio (MRC). The proposed reverse coverter for the module set Microelectroic Laboratory of Shahid Beheshti Uiversity, GC, Tehra, Ira, mrc-ecef@sbu.ac.ir Departmet of Computer Egieerig, Sciece ad Research Brach, Islamic Azad Uiversity, Tehra, Ira, e.khai@srbiau.ac.ir 3 Faculty of Electrical ad Computer Egieerig, Shahid Beheshti Uiversity, GC, Tehra, Ira, {m_doust, avi}@sbu.ac.ir Article Ifo: Received : December 5, 0. Revised : Jauary 30, 0 ublished olie : April 0, 0

2 94 Efficiet Reverse Coverter Desig for Five Moduli Set,,,, has achieved oticeable improvemet i terms of speed compared to reverse coverter previously preseted for the mοdouli set literature.,,,, ad other five moduli sets i Keywords: Residue umber system, reverse coverter, ew Chiese remider theorem-i, mied radi coversio Itroductio Arithmetic operatio is oe of the mai parts of the digital systems. With growth of applicatio, eeds for speed up the arithmetic operatio is sesible. Residue umber system (RNS) has bee cosidered as a alterative for biary system by researchers i past years. I residue umber system, operatio like additio, subtractio ad multiplicatio ca be replaced by parallel eecutio of small circuits []. Although RNS is ot suitable for geeral purpose processors, its realizatio i special applicatio such as image processig [-3], digital sigal processig [4], FIR filter [5-6] ad cryptography [7-8] resulted i more speed ad less power cosumptio over biary systems. Biary to residue (forward) coversio, arithmetic operatio ad residue to biary (reverse) coversio are the three mai parts of the RNS systems. RNS system is maily cosists of module set. The RNS module must be pair wise relatively prime. The dyamic rage of a RNS system is defied i terms of the product of the module, ad it deotes the iterval of itegers eclusively represeted i RNS []. Efficiecy of forward coversio, arithmetic operatio ad reverse coversio is related to careful selectio of module set. Amog these

3 M.R. Taheri, E. Khai, M. Esmaeildoust ad K. Navi 95 three parts, reverse coverter has more comple architecture ad its compleity will growth deped o the umber of module. Therefore efficiet desig of reverse coverter is eeded i order to gai the beefit of the RNS. Module set,, [9] is the most famous module set but the provided dyamic rages by this module set is ot suitable for moder applicatio. Therefore four module sets like,,,,,, set,,,, [0] are reported. For more parallelism five module ad with arithmetic friedly module is reported i []. Iefficiet multiplicative iverses are oe of the mai disadvatages of this module set. This leads to very comple hardware architecture of the reverse coverter with large delay. I order to achieve fast ad simple hardware implemetatio of reverse coverter i five module RNS system ad achieve tradeoff betwee arithmetic operatio ad reverse coversio, the module sets,,,, [] ad,,,, [3] are preseted. I this work differet reverse coverter architecture for the module set,,,, compared to [3] will be preseted. The proposed reverse coverter has achieved oticeable improvemet i terms of delay of the reverse coverter compared to [3]. This paper is orgaized as follows. The related RNS backgroud is preseted i sectio. The proposed architecture of the reverse coverter is discussed i sectio 3. Sectio 4 presets the performace compariso of the proposed architecture with other five module reverse coverters ad fially sectio 5 cocludes the paper.

4 96 Efficiet Reverse Coverter Desig for Five Moduli Set RNS Backgroud RNS is represeted by set of N iteger umber,,..., that are pair N wise relatively prime. The dyamic rage (DR) is the product of the module ad every iteger umber betwee 0 ad (DR-) ca be uiquely represeted as X,,, N i= X mod i. The additio, subtractio ad multiplicatio operatios o residues performed i parallel without carry propagatio. Therefore large umbers ca be preseted by set of smaller umbers that ad results i speed up the operatio. Coversio of residue umbers to its equivalet i biary form could be achieved by Chiese Remider Theorem (CRT), Mi Radi Coversio (MRC) ad New CRT-I []. These theorems are described as follows: By usig Chiese Remider Theorem equivalet of weighted biary umber calculated from residue is as N X L M i i i i i M () Where M = N, M i M i ad L i M i i is the multiplicative iverse of M i i modulus i. Mi Radi Coversio calculates equivalet of weighted biary umber by N X v... v v v v N i i 3 () v ( v ) v 3 (( 3 v ) v ) I geeral

5 M.R. Taheri, E. Khai, M. Esmaeildoust ad K. Navi 97 v N ((( N v ) v ) v N ) N N N N N i deotes the multiplicative iverse of i i modulus j. j New CRT-I computes the weighted umber X as k( ) k ( 3 ) X + k ( ) N 3 N N N 3 N (3) k k 3 N 3 N k N N N 3 Reverse Coverter Desig For efficiet implemetatio of reverse coverter for the module set,,,, two levels desig are employed. I first level subset,,, are calculated by usig New CRT-I. Secod level stads for calculatig the weighted umber from the subset based o MRC. ) ( ), (

6 98 Efficiet Reverse Coverter Desig for Five Moduli Set 3. First level desig As metioed before, first level calculate the weighted umber from the subset,,, ad cosiderig =, =, 3= /, 4 = / by usig New CRT-I. The required multiplicative iverses based o New CRT-I prescribed i Eq. (3) are as follows. K K K (4) ( ) K ( )( ) K (5) / / ( )( )( ) K (6) 3 / 3 For the calculatio of weighted umber Z from its residues by usig New CRT-I we have K( ) K( 3 ) Z K33( 4 3) 3 4 By replacig the calculated multiplicative iverse i Eq. (7), results i ( ) ( ) ( 3 ) Z ( ) / ( )( / )( ) Eq. (8) ca be rewritte as (7) (8) Z ( ) z z z (9) z ( ) ( ) 3 z ( )( )( ) / / 4 3 z ( ) 3

7 M.R. Taheri, E. Khai, M. Esmaeildoust ad K. Navi 99 Cosiderig...,,0,...,,0, 3 3, /... 3,0 ad 4 4, /... 4,0 for z we have z ( ) ( ) (0) 3 z ( ) ( , /... 3, ,...,0) 3 / z ( ) ( , /... 3, ,...,0) 3 / () () z z ,0 3, / 3,0 3, / 3, / / (, ,...,,..., ) ,0 3, / 3,0 3, / 3, / /,0...,...,,...,0...) (3) (4) z z z z (5) 3 z ,0 3, / 3,0 3, / 3, / / z......,0,, z3,...,0... For z we have / / z ( )( )( , /... 4, , /... 3,0) 3 / 3 / (6)

8 00 Efficiet Reverse Coverter Desig for Five Moduli Set z / ( )( , /... 4,0 4, /... 4,0) ( , /... 3, , /... 3,0) / 3 / (7) / ( 4, /... 4,0 4, /... 4,0 4, /... 4,0 4, /... 4,0 z 3, /... 3, , /... 3, , / / , /... 3, / /... ) 3, / 3,0 (8) , 4,0 4, / 4,0 4, / 4,0 4, / 4,0 4, / 4, z , 3,0 3, / 3,0 3, / 3, / 3, / / 3, /... 3,0... 3, /... 3,0... / / (9) For simplicity Eq. (9) ca be rewritte as z z z z (0) 3 z , 4,0 4, / 4,0 4, / 4,0 4, / 4,0 4, / 4, z , 3,0 3, / 3,0 3, / 3, / 3, / / For z 3, we have z3 3, /... 3,0... 3, /... 3,0... / / z ,,0,,0 () z ,,0,,,0 ()

9 M.R. Taheri, E. Khai, M. Esmaeildoust ad K. Navi 0 Therefore z z z z (3) z ,,0 z... 3, z... 33,,0 After calculatio of z, z ad z 3, Z i Eq. (9) ca be cosidered as Z Y (4) ( ) Y z z z z z z z z Hardware implemetatio of Y is show i Figure. After calculatio of Y, we have Z Y (5) ( ) By cocateatio of with (+) bit i biary form at the ed of + Y, Eq.(5) ca be rewritte as Z Y Y (6)

10 0 Efficiet Reverse Coverter Desig for Five Moduli Set X X X 3 X 4 OU Z 3 Z 3 Z 33 Z Z Z Z Z Z 3 bit CSA with EAC bit CSA with EAC bit CSA with EAC bit CSA with EAC bit CSA with EAC bit CSA with EAC bit CSA with EAC MA( ) Y X OU YX Figure : Hardware implemetatio of Z 3. Secod level of the desig After calculatio of Z, the subset {( )( ), } is achieved. I order to calculate the weighted umber X, by usig MRC ad cosiderig achieved from the previous level ad 5 we have 34 ( )( ) X v v (7) 345

11 M.R. Taheri, E. Khai, M. Esmaeildoust ad K. Navi 03 v Z v ( Z ) The required multiplicative iverse i Eq.(7) is recalculated as K ( )( ) K (8) 34 By replacig Eq.(6) ad Eq.(7) i Eq.(8), we have By replacig Eq.(6) i Eq.(30), we get X Y Y ( )( ) v (9) v 5 Z (30) v 5 Y Y (3) v Y... Y (3) 5, 5,0,,0 0 v... k k (33) 5, 5,0 k... k Y... Y,,0 0 Hardware Implemetatio of v is show i Figure. By replacig v i Eq.(9), we have X Y Y ( )( ) v (34) X vy Y v v v (35) X v Y( v Y ) v... v (36)

12 04 Efficiet Reverse Coverter Desig for Five Moduli Set 5 k k bit CSA bit CA v Figure : Hardware implemetatio of v For reducig the umber of levels of CSA i Eq.(36) i hardware implemetatio it ca be rewritte as X v Y( v Y ) v v X hh h3 h4 h vy h vy h v v h Hardware implemetatio for calculatio of X is show i Figure 3. 4 Compariso This sectio presets the compariso of the proposed reverse coverter for the module set { + -, +, / -, / +, } with other five module set reverse coverters reported i [], [] ad [3]. As show i Table, the proposed coverter has (0+0)t, FA t FA deotes the delay of oe bit full adder. The reverse coverter proposed i [3] has the delay of (+6)t FA. Therefore the

13 M.R. Taheri, E. Khai, M. Esmaeildoust ad K. Navi 05 proposed coverter for the module set { + -, +, / -, / +, } with differet levels of the desig compared to [3] achieved i more speed i reverse coversio. Figure 3: Hardware implemetatio of X Table : Delay ad area compariso of five moduli sets reverse coverters Coverter Hardware requiremets Uit gate area Coversio delay Uit gate delay [] ((5 +43+m * )/6 (5 +43+m * )7/6 +6-)A FA (6+)A NOT (8+L * +7 )t FA 7+4L * +8 (0+5)A FA +(7-5)A XNOR [] +(7-5)A OR +(-3)A XOR 4+5 (3+)t FA +3t NOT 5+7 +(-3)A AND +(8+)A NOT [3] (.5+6)A FA +(4.5-)A XNOR +(4.5-)A OR.5+37 (+6)t FA +3t NOT (.5-)A XOR +(.5-)A AND +(7+)A NOT roposed (0 +/+)A FA +(-)A XNOR +(-)A OR +(+3)A XOR +(+3)A AND +(9/)A NOT (0+ 9)t FA *m = -4, 9- ad 5-8 for =6k-,6k ad 6k +, respectively, ad L is the umber of the levels of a CSA tree with ((/) +) iputs.

14 06 Efficiet Reverse Coverter Desig for Five Moduli Set Compariso with other five module sets are show i Table. It ca be see that the proposed reverse coverter for the module set { + -, +, / -, / +, } has achieved to fastest implemetatio compared to other five module reverse coverters. I order to achieve fair compariso, uit gate delay ad area are calculated which is show i Table. I uit gate delay model, FA gates are cosidered with area of seve gates ad delay of four gates. Each two iput mootoic gates cosidered with oe area ad delay ad XOR/XNOR gates are cosidered with two gates area ad delay []. Uit gate delay compariso cofirms faster desig of the reverse coverter for the module set { + -, +, / -, / +, } is achieved. 5 Coclusio set I this paper, reverse coverter with two levels desig for the five module,,,, is preseted. The proposed coverter uses New CRT-I ad MRC for first ad secod level, respectively. Noticeable improvemet i speed of reverse coversio has achieved compared to other five module sets reverse coverters. Refereces [] K. Navi, A.S. Molahosseii ad M. Esmaeildoust, How to Teach Residue Number System to Computer Scietists ad Egieers, IEEE Trasactios o Educatio, 54(), (0),

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16 08 Efficiet Reverse Coverter Desig for Five Moduli Set [] A.S. Molahosseii, C. Dadkhah, K. Navi, A New Five-Moduli Set for Efficiet Hardware Implemetatio of the Reverse Coverter, IEICE Electroics Epress, 6(4), (009), [3] Mohammad Esmaeildoust, Keiva Navi ad MohammadReza Taheri, High speed reverse coverter for ew five-moduli set {, + -, / -, / +, +}, IEICE Electro Epress, 7(3), (00), 8-5.