A One-Step Modulo 2 n +1 Adder Based on Double-lsb Representation of Residues

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1 The CSI Joural o Computer Sciece ad Egieerig Vol. 4, No. &4, 6 Pages 1-16 Regular Paper A Oe-Step Modulo +1 Adder Based o Double-lsb Represetatio of Residues Ghassem Jaberipur Departmet of Electrical ad Computer Egieerig, Shahid Beheshti Uiversity, Tehra, Ira Abstract Efficiet modulo ±1 adders are desirable for computer arithmetic uits based o residue umber systems (RNS) with the popular moduli set { 1,, +1}. Regular -bit ripple-carry adders or their fast equivalets are suitable for modulo additio. But for the other two moduli a correctig icremet/decremet step besides the primary -bit additio is ormally required. Several desig efforts have tried to reduce the latecy of the correctig step to a small delay ot depedig o the word legth, leadig to oe-step modular additio schemes. These iclude the use of alterative ecodig of residues (e.g., dimiished-1 represetatio of modulo +1 umbers), customized (vs. geeric) adders (e.g., specialized parallel prefix adders), or compoud adders. I this paper we ivestigate alterative modulo +1 additio schemes, focus o geeric oe-step adder desigs, ad use the double-lsb represetatio of modulo +1 umbers. I a geeric modular adder, the cetral abstract -bit adder may be replaced by ay cocrete adder architecture meetig the desiger s prescribed measures i time, area ad power cosumptio. Keywords: Residue umber system, Modulo +1 additio, Double-lsb represetatio, Dimiished-1 umber represetatio, Parallel prefix adders, Geeric adders. 1. Itroductio Residue umber systems (RNS) ad the related arithmetic uits are popular i may digital sigal processig applicatios where most computatios are restricted to multiplicatio, additio ad subtractio [1]. Applicatio areas, besides geeral RNS arithmetic, as oted i [] iclude: Fast umber theoretic trasforms Discrete Fourier trasform Digital filters A residue umber system Ψ is characterized by k iteger moduli m k 1 m 1, m. A iteger value x (α x β) is uiquely represeted by (x k 1 x 1, x ), where x i = x mod m i ( i k 1), ad [α, β] is the dyamic rage of Ψ, whose cardiality is M Ψ = β α. To maximize M Ψ, the moduli are chose to be pair-wise prime, such that M Ψ = m k 1 m 1 m. To compute x y, where is a arithmetic operator (e.g., + or ), oe simply performs modular o each of the k residues of x ad y i parallel as i Equatio (1), where subscript m i ( i k 1) stads for modulo m i operatio, x = (x k 1, x 1, x ), ad y = (y k 1, y 1, y ). x y = (( x y ),...( x y ),( x y ) ) (1) k 1 k 1 mk m1 m RNS additio, as also the basis for subtractio ad multiplicatio, is composed of addig the two residues per each of the moduli followed by a mod operatio. Therefore the latecy of RNS additio would at best be i the order of log (max (m k 1 m 1, m )), which is cosiderably less tha that of same operatio o full-words x ad y, provided that the differece betwee miimum ad maximum moduli is miimal. For higher speed, however, the moduli with simpler mod operatio are preferred.

2 Gh. Jaberipur: A Oe-step Modulo +1 Adder Based o Double-lsb Represetatio of Residues (Regular Paper) 11 The first choice is leadig to fastest mod operatio, which is actually performed by igorig the carry-out sigal of the residue adder ad keepig the sum. Next popular choices have primarily bee ±1 [3, 4, 5, ad 6]. The three moduli are pair-wise prime ad the required dyamic rage ca be met by choosig the proper value for. Ulike the case, the mod operatio for moduli ±1 may ivolve substative overhead i terms of hardware ad latecy, but yet much less tha similar operatio for other moduli. Previous research o modulo ±1 adders has show that modulo +1 adder is more complex tha that of the cojugate modulo [7]. Therefore, ay performace gai i modulo +1 adder will ehace the efficiecy of the popular {, ±1} RNS. I this paper we focus o modulo +1 additio. Besides the geeral RNS applicatios, listed above, Efstathiou et. al. [8] categorize alterative applicatios of modulo +1 additio as: Cryptography Pseudoradom umber geeratio Covolutio computatio Zimmerma [3] offers a thorough aalysis of differet possible modulo ±1 arithmetic implemetatios that had bee appeared i the literature, where modulo +1 additio is either performed i two additio cycles or with two parallel adders. Two parallel-prefix modulo +1 additio schemes have bee proposed i [6 ad 7]. The adder architecture i both cotributios is based o ed-aroud carry icremet after the mai additio cycle. However the ed-aroud carry icremet operatio is fused i the fial carry computatio logic. The latter desig, although successful i usig a sigle -bit adder, is ot a geeric desig i a sese to allow for replacig its specialized parallel prefix adder, with aother adder architecture meetig particular desig measures i time, area, or power cosumptio. Neither have we ecoutered, i the ope literature, ay modulo +1 geeric additio scheme with a sigle abstract -bit adder, replaceable by ay desired fuctioally equivalet cocrete -bit adder. The rest of this paper is orgaized as follows. We review the covetioal umber represetatios for modulo +1 umbers ad the related adder desigs i Sectio. I Sectio 3, we propose a oe-step geeric modulo +1 additio scheme based o double-lsb [9] represetatio of modulo +1 residues [1]. Coversio to/from biary is discussed i Sectio 4, ad fially we draw our coclusios i Sectio 5.. Geeral Module +1 Additio A geeral block diagram, for modulo +1 adders, is depicted i Figure 1. The mai fuctio is doe by the middle block, amely a abstract -bit-log adder, where a -bit-log operatio is formally defied, for the purpose of referece i this paper, as: Defiitio 1 (-bit-log operatio): A -bit uary or biary operatio, performig o oe or two -bit operads ad producig the result with a icostat latecy with respect to, but at most liearly depedig o, is called a -bitlog operatio. Also we defie a oe-step modulo +1 adder as: Defiitio (Oe-step modulo +1 adder): Ay modulo +1 adder, whose critical delay path passes through oly oe -bit-log biary operatio (see Def. 1) is called a oestep modulo +1 adder. If the top ad bottom blocks of Figure 1 perform i costat time the adder is, by Def., a oe-step adder. Figure 1. Geeral block-diagram of modulo +1 adder Examples of -bit-log operatios iclude: -bit ripple-carry adders -bit carry-accelerate adders (e.g., carry look-ahead [] icludig parallel prefix [7], carry-select [8], or carry-skip [11] adders) -bit icremet/decremet adders -bit zero detectors The preprocessig ad postprocessig blocks of Figure 1, depedig o the uderlied algorithm used for implemetig modulo +1 adders, may vary i performace ad complexity. For example, a straight forward algorithm may be described as follows: Algorithm 1 (Modulo Additio): Iputs: A = a a 1 a 1 a, B = b b 1 b 1 b ( A, B ). Output: S = ( A + B ) ( S ). I. Compute W = A + B (W = w +1 w W', W' = w 1 w 1 w, w +1 = a b ). II. If w +1 = 1 the S = 1 else if w = the S = W' else if W' = the S = else S = W' 1. Step II of Algorithm 1 is justified as: w +1 = 1 (i.e., A = B = a = b = 1): S = ( A + B) = A + B () = 1 w +1 = w = (i.e., A+B < ): S = ( A + B) = W w +1 = ad w = 1 (i.e., A+B < +1 ): W' = A + B =, otherwise S = ( A + B) = A + B 1 = W 1

3 The CSI Joural o Computer Sciece ad Egieerig, Vol. 4, No. &4, 6 1 I the above algorithm, Step I ivolves a -bit-log additio ad Step II, i the worst case, goes through a -bitlog decremet operatio (i.e., to compute W' 1). Moreover checkig for W' =, is geerally a -bit-log operatio. It is aturally desirable to fid algorithms that compute the required modulo additio by oly oe -bit-log operatio. Parallel computatio of W ad W 1 is a alterative solutio, but with high pealty i area ad power cosumptio due to a extra active -bit-log adder. As aother solutio use of dimiished-1 represetatio has bee proposed i [1] with further elaboratio i [3]. Yet it requires either two -bit-log additio operatios i sequece or two -bit-log adders that operate i parallel. For ease of referece, we provide Algorithms for the latter method. Algorithm (Modulo +1 Dimiished-1 Additio): Iputs: Dimiished-1 represetatios of A ad B (i.e., (z a, A') ad (z b, B') with A' = A 1, B' = B 1, z a = z b = 1 for A, B >, ad z a = z b =, for A = B =, where A' = a 1 a 1 a, ad B' = b 1 b 1 b ). Output: Dimiished-1 represetatio of S = ( A + B ) (i.e., (z s, S'), with S = ( A + B ) 1 ad z s = 1 for S >, ad z s = for S = ). I. Derive z s = z a OR z b. II. If z s = 1 the compute W = A + B (W = w w 1 w 1 w ) else exit (S = ). III. If w = 1 the S' = w 1 w 1 w else S' = W. IV. If S' = the z s =. Step II of Algorithm is justified as: z s = 1: S' = S 1 = A + B 1= A' + B' 1 = A' + B' z s = : z a = z b = A = B = S = Step III is justified as: z s =w =1:W S = ( A + B ) = ( A + B ) = ( W ) = w 1 w 1 w +1 z s = 1, w = : W S = ( A + B ) = A + B =W=w 1 w There is a -bit-log additio operatio, a -bit-log icremet, ad a -bit-log zero detectio i Algorithm (see Step II, III, ad IV, respectively). The icremet operatio has bee successfully fused i Step II through a special parallel prefix additio scheme [6]. As a further iterestig iovatio [7] provides a ovel modulo +1 additio scheme (described, i our otatio, by Algorithm 3, below), based o Equatio (), where W = A + B + 1 ad o special provisio for detectio of zero results is eeded. + 1 ( W) + 1 if W S = ( A+ B) = + () 1 + (( W) 1 + ) + 1 otherwise Algorithm 3 (Modulo Parallel-Prefix Additio): Iputs: A = a a 1 a 1 a, B = b b 1 b 1 b ( A, B ). Output: S = ( A + B ) ( S ). I. Compute W = A+B+ 1 (W = w +1 w w 1 w 1 w ) by: a. Simplified carry-save additio of A, B, ad 1. b. Parallel prefix additio of carry ad sum vectors resulted from a. II. S = s s 1 s 1 s = w +1 + w w 1 w 1 w + w +1. The fuctio of Algorithm 3 is illustrated i Figure, ad Step II is justified as: w +1 = 1: +1 W w =, ad A + B S = ( A + B) = A + B 1= W +1 = w 1 w 1 w + w +1 =, w = 1: W < +1 1 A + B < S = ( A + B) = A+B = W = w 1 w 1 w w +1 =, w = : W = 1 A = B = S = = 1 w 1 w 1 w The cases of A + B =, ad A = B =, lead to W = +1 ad W + = 1 + = +1, respectively. Both cases result i S =. The -bit-log additio of Step I.b ca be implemeted by a variety of carry acceleratio methods [11]. I particular carry look-ahead adders [] ad parallel prefix adders [7] ca be used to fuse the fial icremet ito positioal carry computatio of the mai additio for derivatio of W. The trick, as show i a a 1... a 1 a b b 1... b 1 b a b 1 b 1 a a1 b a 1 b a b a 1 + b 1 a + b a 1 + b 1 a + b w +1 w w 1 w w 1 w Figure. Derivatio of W i Algorithm 3

4 Gh. Jaberipur: A Oe-step Modulo +1 Adder Based o Double-lsb Represetatio of Residues (Regular Paper) 13 Equatio-set (3), is to postpoe the computatio ivolvig c i (i.e., carry ito the lsb positio) to the last stage of positioal carry derivatios, thus avoidig a ew carry look-ahead computatio for eforcig the ed-aroud carry. c i = G i 1 + P i 1 c i = G i 1, c +1 = G, c i = G i 1 + P i 1 G + a b = G i 1 + ( a b P i 1) c i is the carry ito positio i (c = c i = ), G ad P variables represet c i -idepedet geerate ad propagate expressios based o positioal geerate ad propagate sigals (i.e., g i ad p i ), ad c i is the fial carry ito positio i used for derivatio of s i = pi c. Expressios for G i i ad P i variables (icludig G ) deped o all the g j ad p j-1 sigals ( j i). These are computable i parallel by fudametal carry look-ahead operator cells [13] or parallel prefix trees through the recurrece equatio-set (4). G (3) Double fudametal carry look-ahead operator cells i some tree odes Differet fudametal carry look-ahead operator cells i the last row (pale circles) Aother disadvatage is the o-geeric behavior of the desig i Figure 3, where it is ot possible to replace the mai -bit-log adder by other adder architectures (e.g., whe due to ecoomizig area ad power cosumptio, desigers prefer to do Step I.b by a ripple-carry adder). G i = g i 1 + p i 1 G i, P i = p i 1 P i 1, g i = ai bi (a i 1 + b i 1 ), p i = ai bi + (a i 1 + b i 1 ) (4) Direct computatios of s i = pi c ad s i = p c obviates the eed for computatios of w i = p i c i ad s = w +1 + w. The fused ed-aroud carry is w = G + a b +1, where G ad a b caot both be equal to 1. Therefore the overall delay for sum bits s i, based o the same aalysis as i [7], cosists of the followig delay compoets, leadig to (7 + log ) uit gate delays: a. The XOR operatio i the origial carry-save additio: uit gates b. g i ad p i computatios: 1 uit gate c. G ad P derivatios: log uit gates (Parallel prefix logic assumed) d. c computatio: uit gates i e. The XOR operatio for the fial sum geeratio: uit gates The overall latecy of the similar implemetatio i [7] is estimated to be (9 + log ) uit gate delays. Our better estimate is due to usig a modified equatio for c i computatio (see equatio (3) above), which ufortuately has the disadvatage of large fa-out o a b. The best previous result for fastest modulo additio, as oted i Sectio above, has bee reported i [7] with the latecy of (6 + log ) uit gates, where the proposed architecture (see Figure 3, copied from [7], below) is based o a complex parallel prefix tree with the followig VLSI-ufriedly properties: A sigle global feed-forward lie global ad half-way backward lies Differet p ad g cells (idicated by bright, light gray, gray, ad dark squares) Figure 3. Modulo parallel prefix adder with backward lies, from [7] All the previously published algorithms for modulo additio, icludig the oes described i our otatio by Algorithms ad 3 above, essetially require a -bitlog additio operatio followed by a -bit-log icremet operatio, uless special carry acceleratio techique offered i [7] or parallel adders to compute sum ad icremeted sum are used. I the ext sectio, however, we preset our ovel modulo +1 represetatio, which is suitable for oestep ripple-carry (or ay carry-accelerate) implemetatio of modulo adders. 3. Double-lsb Modulo Additio The followig ew oe-step modulo +1 additio algorithm is based o double-lsb [9 ad 14] represetatio of modulo umbers [1]. A -biary-positio double-lsb represetatio is basically the same as a -bit usiged biary represetatio, except for a extra bit i positio zero. The extra lsb ehaces the rage of represeted umbers to exactly [, ] ad leads to the possibility of storig the edaroud carry istead of a post-icremet operatio. The two equally weighted lsbs are distiguished by primed ad oprimed versios of the same variable.

5 The CSI Joural o Computer Sciece ad Egieerig, Vol. 4, No. &4, 6 14 Algorithm 4 (Additio of Double-lsb Modulo umbers): Iputs: A = a 1 a 1 a a', B = b 1 b 1 b b' ( A, B ). Output: S = ( A + B ) = s 1 s 1 s s' ( S ). I. Compute W = A + B 1. II. If W the S = W (s' = ) else S = W (s' = 1). The above algorithm, i a abstract sese, is the same as Algorithm 3 of the previous sectio. But the double-lsb represetatio of the operads ad the followig implemetatio of A + B 1 exhibit a cosiderably differet implemetatio approach. The basic idea, as depicted i Figure 4 is to compute W as follows: If z = a + a + b + b = 1 the W = A + B z. If a + a' + b + b' = 1 (i.e., z = ad at least oe of the lsbs is 1) the we igore a 1-valued lsb, to accout for 1 i Step I above, ad represet the sum of other three bits as t 1 u i Figure 4. Therefore W = A + B z 1. The latter observatio suggests the computig of A + B z, i both cases of z = 1 or z =, with the uderstadig that i the secod case (i.e., z = ), the decremet operatio is take care of by leavig out a 1-valued lsb. I Figure 4, z is represeted as +1 z+( +1 1)z. Table 1 shows how a 1-valued bit is left out, where sum of the three remaied bits are derived as t 1 + u (Equatioset (5), below) ad due to a = a' = b = b' =, for z = 1, three etries are missig. t 1 = a b a' + a b b' + a' b' a b + a' b' a b, u = a b a b (5) a 1... a 1 a b 1... b 1 b b' z z z z z z c +1 z z 1 1 a' a b z a 1 b 1 z u t t 1 t t 1 w w 1 w w 1 w s 1 s s 1 s Figure 4. Double-lsb modulo +1 additio s' Table 1. Derivatio of three remaied bits i positio z a b Leftout 1? Other possibly sigificat bits t 1 u Yes a' or b' a 1 Yes a' ad b' a' b' a 1 Yes a' ad b' a' b' a 1 1 Yes b = 1, a' ad a' b' +b' a 1 No Noe Table. Derivatio of fial sum S z c +1 w s +1 s s 1 s s w 1...w 1 1 w 1...w w 1...w w 1...w There is actually o eed to compute c +1 z, i positio +1 of Figure 4, for c +1 ad z may directly cotribute to the derivatio of the fial sum S as is outlied i Table ad Equatio-set (6), where the absece of three other potetial etries are due to the costrait A+B 1< +1. s i = w i (c +1 + z ), for i <, s = w (6) A parallel prefix implemetatio of Algorithm 4 is depicted i Figure 4, where the delay compoets as listed below sum up to the same latecy as the totally parallel prefix (TPP) implemetatio of Algorithm 3 i [7] (i.e., 6 + log, assumig equal latecy for full adders i Figure 5 ad modified half-adders of Figure 3): a. Computatio of t 1 (Equatio (5)), ad delay of the CSA adder: uit gates. b. g i ad p i computatios: 1 uit gate c. G ad P derivatios: log uit gates (Parallel prefix logic assumed) d. The XOR operatio for the iterim sum geeratio: uit gates e. The AND delay for fial sum geeratio: 1 uit gate However our parallel prefix tree is without global backward lies, ad ehaced VLSI regularity is clearly a additioal advatage i our desig. 4. Coversio to/from Biary Coversio of a biary iteger I to double-lsb modulo +1 represetatio, follows the covetioal process of biary to modulo +1 residue coversio up to reducig I to a +1- bit biary iteger [11]. The the process is cotiued, by subtractig the msb (which weighs ) from the rest of represetatio (i.e., the rightmost bits), ad savig the outgoig borrow as the secod lsb. The latter is 1 if ad oly if

6 Gh. Jaberipur: A Oe-step Modulo +1 Adder Based o Double-lsb Represetatio of Residues (Regular Paper) 15 the origial +1-bit umber had bee equal to. The secod part of the coversio process is less complex tha covetioal biary to modulo +1 coversio which, besides subtractio of msb, ivolves a -bit zero detectio compressor may be used for reductio of each colum istead of a full adder. The additioal delay is equal to that of oe XOR gate. This is practically egligible i compariso with the log -bit additio required after reductio. Figure 5. Regular VLSI-friedly parallel prefix modulo +1 adder for the case of as the residue. For the reverse coversio, the secod lsb does ot itroduce cosiderable iefficiecy. Residue to biary coverters, ormally implemet the Chiese remaider theorem [1] usig carry save adders (CSA) for the required multi-operad biary additio. With a careful desig of the CSA tree, cotributio of the secod lsb to the overall coversio delay may oly add oe level of CSA. For example, for the popular moduli set { ±1, }, Equatio-set (11) adapted from [15] coverts (X, Y, Z) to I, where X = (I), Y = (I), ad Z = (I) : 1 1 I I X I - ( X Z Y Z ) = +, = -( + ) + ()( + ) (11) - 1 The equatio for I', after some maipulatio, turs to Equatio (1), where X (Z ) is oe s complemet of X (Z). I = X + Z + Y + Z + Y + Z (1) 1 1 ( ) ( )) 1 Assumig X = x 1...x, Y = y 1...y, ad Z = z 1...z, implemetatio of (1) may be illustrated as i Figure 6. It is easily see that the secod lsb (i.e., z ) deepes the multioperad additio tree by oly oe level. Therefore, a (4; ) Weights: 1 1 { x - 1 x - x z - 1 z CStree 1 y y 1 y 1 y y z z 1 z 1 z z 1 5. Coclusio Figure 6. Multi operad additio tree We used double-lsb represetatio for modulo +1 umbers, ad preseted a modulo +1 additio scheme, where the ed-aroud carry may be stored as the secod lsb istead of a udesired -bit-log icremet operatio. With the double-lsb represetatio, our algorithm is the first, i the ope literature, that allows for a oe-step -bit carry-ripple implemetatio of modulo +1 additio. However, there is a preprocessig phase cosistig of a costat-time carry-save additio. This desig is a geeric oe i a sese that the mai -bitlog adder may be replaced by ay adder architecture that fits the desiger s goals for area, time, ad power requiremets. The carry-save ad carry-ripple adder

7 The CSI Joural o Computer Sciece ad Egieerig, Vol. 4, No. &4, 6 16 combiatio, leads to less area cosumptio tha that of the parallel additio paradigm with -bit selector logic. Moreover, less power dissipatio is expected due to less switchig activity of carry-save adder. Furthermore we showed that a covetioal parallel prefix implemetatio of the double-lsb additio algorithm leads to the same latecy as the best reported delay-optimized modulo +1 adder [7]. Nevertheless, our desig is more VLSI-friedly with respect to regularity ad lack of backward itercoectio lies, except for oe due to storig the ed-aroud carry. Fially we showed that doubl-lsb represetatio does ot itroduce ay iefficiecy for biary to residue coversio ad causes egligible additioal delay i the reverse coversio for the moduli set { 1,, +1}. Give that efficiet modulo multipliers have bee desiged (e.g., [16]), further research is ogoig for modulo +1 multiplier desig based o double-lsb represetatio, ad similar ucovetioal represetatios for other moduli are beig explored. Ackowledgemet This research was fuded by Shahid Beheshti Uiversity uder cotract # 6/17/111. Refereces [1] Soderstrad, M. A., W. K. Jekis, G. A. Jullie, ad F. J. Taylor, Residue Number System Arithmetic: Moder Applicatios i Digital Sigal Processig, IEEE Press, New York, [] Hiasat, A. A., High-Speed ad Reduced Area Modular Adder Structures for RNS, IEEE Tras. Computers, pp ,. [3] Zimmerma, R., Efficiet VLSI Implemetatio of Modulo 1 Additio ad Multiplicatio, Proc. 14 th IEEE Symp. Computer Arithmetic, pp , Apr [4] Kalamboukas, L., D. Nikolos, C. Efstathiou, H. T. Vergos, ad J. Kalamatiaos, High-Speed Parallel-Prefix Modulo 1 Adders, IEEE Tras. Computers, Vol. 49, No. 7, pp , July. [5] Efstathiou, C., H. T. Vergos, ad D. Nikolos, O the Desig of Modulo ±1 Adders, Proc. 8 th IEEE It l Cof. Electroics, Circuits & Systems, pp , 1. [6] Vergos, H. T., C. Efstathiou, ad D. Nikolos, Dimiished-Oe Modulo +1 Adder Desig, IEEE Tras. Computers, Vol. 51, pp ,. [9] Parhami, B., ad S. Johasso, A Number Represetatio Scheme with Carry-Free Roudig for Floatig-Poit Sigal Processig Applicatios, Proc. of the Iteratioal Cof. o Sigal & Image Processig (SIP 98), Las Vegas, NV, pp. 9-9, October 8-31, [1] Timarchi, S., ad K. Navi, A Novel Modulo +1 Adder Scheme, 1 th iteratioal CSI Computer Coferece, Shahid Beheshti Uiversity, Tehra, Ira, pp , Feb. 7. [11] Parhami, B., Computer Arithmetic: Algorithms ad Hardware Desigs, New York: Oxford Ui. Press,. [1] Agrawal, D. P. ad T. R. N. Rao, Modulo ( +1) arithmetic logic. IEEE J. o Electroic Circuits ad Syst., Vol., pp , Nov [13] Kogge, P. M., ad H. S. Stoe, A Parallel Algorithm for the Efficiet Solutio of a Geeral Class of Recurrece Equatios, IEEE Tras.Computers, Vol., No. 8, pp , Aug [14] B. Parhami, Double-Least-Sigificat-Bits 's- Complemet Number Represetatio Scheme with Bitwise Complemetatio ad Symmetric Rage, IET Circuits, Devices & Systems, to appear i 8. [15] Wag, Z., G. A. Jullie, ad W. C. Miller, A Improved Residue-to-Biary Coverter, IEEE Tras. Circuits Syst. I: Fudametal theory ad applicatios, Vol. 47, No. 9, pp , September. [16] Efstathiou, C. et. al., Efficiet Dimiished-1 Modulo Multipliers, IEEE Tras. o Computers, Vol. 54, No. pp , 5. Ghassem Jaberipur received his B.S i Electrical Egieerig ad PhD i Computer Egieerig from Sharif Uiversity of Techology i 1974 ad 4, respectively, his M.S i Egieerig (majorig i computer hardware) from UCLA i 1976, ad his M.S i Computer Sciece from Uiversity of Wiscosi i Madiso i Sice 1979, he has bee with the departmet of Electrical ad Computer Egieerig of Shahid Beheshti Uiversity (Tehra, Ira). His mai activities iclude teachig udergraduate courses i theory ad implemetatio of programmig laguages, ad graduate courses i compiler costructio ad computer arithmetic. His mai research iterest is i computer arithmetic. Dr. Jaberipur is also affiliated with the School of Computer Sciece, IPM (Tehra, Ira). Jaberipur@SBU.ic.ir [7] Efstathiou, C., H. T. Vergos, ad D. Nikolos, Fast Parallel-Prefix +1 Adder, IEEE Tras. o Computers, Vol. 53, No. 9, pp , September 4. [8] Efstathiou, C., H. T. Vergos, ad D. Nikolos, Modulo 1 adder desig usig select-prefix blocks, IEEE Tras. Computer, Vol. 5, pp , 3.