DISTRIBUTED ARITHMETIC BASED BUTTERFLY ELEMENT FOR FFT PROCESSOR IN 45NM TECHNOLOGY

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1 VOL. 8, O., JAUARY 3 ISS ARP Joural of Egieerig ad Applied Scieces 6-3 Asia Research Publishig etwor (ARP). All rights reserved. DISTRIBUTED ARITHMETIC BASED BUTTERFLY ELEMET FOR FFT PROCESSOR I 45M TECHOLOGY P. Augusta Sophy, R. Sriivasa ad J. Raja 3 AP/VIT Cheai & Research Scholar, Aa Uiversity, Cheai, Idia SS College of Egieerig, Cheai, Idia 3 Aa Uiversity of Techology, Trichy, Idia sophygua@gmail.com ABSTRACT Fast Fourier Trasform (FFT) is oe of the importat sigal processig algorithms because of its applicatios i digital filterig, commuicatio, image processig, spectral aalysis ad estimatio etc. Butterfly computatio is the basic operatio i the FFT algorithm. I this wor, a ovel approach is thought of ad used i implemetig the butterfly elemet. Distributed Arithmetic Algorithm (DAA) is used to do the butterfly computatio istead of usig covetioal multipliers ad adders. This has resulted i a more efficiet butterfly elemet both i terms of area ad power. This paper describes the desig of such a area efficiet butterfly module. Sigle precisio floatig poit represetatio is used for the data. This desig leads to a lot of area savig ad power savig. This butterfly ca be used as the basic buildig bloc of a low power recofigurable FFT processor. This fids its applicatio i OFDM based systems ad also i software defied radios. Keywords: Fast Fourier Trasform (FFT), butterfly elemet (BF), Discrete Fourier Trasform (DFT), Distributed Arithmetic Algorithm (DAA), twiddle factor. ITRODUCTIO A Fast Fourier Trasform Fast Fourier Trasform (FFT) is oe of the most commoly used sigal processig algorithms i commuicatio ad multimedia systems. It is called as the algorithm for the whole family as it helps i spectral aalysis, spectral estimatio, iterpolatio, decimatio, covolutio, correlatio, filterig, etc. FFT is also used i may applicatios lie oise detectio ad cacellatio, speech ecryptio, samplig rate coversios, applicatios utilizig the FFT filters, audio sigal processig ad image processig. So it is the major part of the base bad processig. More over FFT ad IFFT are also used as demodulatio ad modulatio erels i the OFDM systems. OFDM is a special case of Frequecy Divisio Multiplexig, which is also used i the Software Radio (SDR). OFDM is a combiatio of modulatio ad multiplexig. OFDM ca be easily geerated usig a IFFT module ad demodulated usig a FFT module. FFT is a efficiet method of computig the discrete Fourier trasform (DFT) for a set of data. The Discrete Fourier Trasform (DFT) operates o samples of a time domai sigal ad is defied by the followig equatio. X ( ) = x( e jπ / where X() represets the DFT frequecy output at the -th spectral poit, ragig from to -. The quatity represets the umber of sample poits i the DFT data frame. The quatity x( represets the -th time sample, where also rages from to -. I geeral, x( ca be real or complex. () The correspodig Iverse Discrete Fourier Trasform (IDFT) of the sequece X() gives a sequece x( defied oly o the iterval from to - as follows: x( = / = X ( ) e j π / The DFT equatio ca be re-writte as: = X ( ) x( W The quatity W is defied as: jπ / W = e This quatity is called twiddle factor. It is the sie ad cosie basis fuctios writte i polar form. Examiatio of equatio () reveals that the computatio of poit DFT requires (-) complex multiplicatios ad (-) complex additios. The FFT algorithm was developed by Cooley ad Turey i the year 965,by taig advatage of the symmetry ad periodicity properties of the twiddle factors. W W r / r = W = W r r Out of the two FFT algorithms, DIT (decimatio i time) ad DIF (decimatio i frequecy), DIF is mostly used i the implemetatios of FFT. I the DIF algorithm, the iputs are give i the atural order ad the output () (3)

2 VOL. 8, O., JAUARY 3 ISS ARP Joural of Egieerig ad Applied Scieces 6-3 Asia Research Publishig etwor (ARP). All rights reserved. frequecy poits are obtaied i the bit reversed maer i.e the output frequecy poits are foud to be regrouped or subdivided. This radix- DIF FFT algorithm starts by dividig the samples ito two groups, the first half ad the last half. The divisio goes till the DFT computatio is doe betwee oly two samples. This -poit DFT bloc is called as the butterfly operatio. The sigal flow graph of FFT is costructed with / umber of butterflies i each stage ad there are log umber of stages. Figure-: Sigal flow graph of a 8 poit DIF FFT. The sigal flow graph of a 8 poit DIF FFT algorithm is show i Figure-. The Basic butterfly operatio of the DIF algorithm is show i Figure-. Figure-: Basic butterfly operatio of DIF algorithm For ay DIF butterfly, there are two iputs x ad y (two iput samples). The outputs X ad Y are give by: X = x y Y = ( x y) W The iputs x, y, W ad as well as the outputs X ad Y are complex values. As the butterfly operatio is the basic computatio i FFT algorithm, desigig a highly efficiet butterfly elemet would lead to a lot of savig i silico area ad/or i power. The objective of this wor is to desig ad implemet a area ad power efficiet butterfly elemet, which could be used i buildig a recofigurable FFT/IFFT. Here we have preseted a ew desig for the butterfly elemet, based o the distributed arithmetic algorithm (DAA). DA ca be used for the computatio of sum of products. The DFT equatio give i equatio () is i the sum of products form to which DA algorithm ca be applied. It ca be oted that, i this wor, the DAA is ot applied for the computatio of the poit DFT as a whole, but used for a sigle Butterfly which is a poit DFT. This desig shows savig i the silico area. Applyig DAA to a poit DFT as sum of product restricts the expasio of the desig to ay value of. This maes the desig rigid ad the modularity is lost. Usig the DAA approach to a sigle butterfly maes the desig modular ad it becomes easy to expad the desig to ay value of. By usig this butterfly elemet, we ca build a efficiet recofigurable FFT processor. More over, i this project, IEEE sigle precisio 3 bit floatig poit otatio is used for represetig the samples. This ehaces the suitability of the desig for idustrial applicatios. This paper presets this ovel DAA based butterfly desig. Sectio explais the geeral DA algorithm. Sectio 3 presets the DA algorithm applied for the floatig poit butterfly elemet. Sectio 4 presets the hardware desig. Sectio 5 presets the sythesis results obtaied from Syopsys Desig compiler. DISTRIBUTED ARITHMETIC ALGORITHM - A OVERVIEW There are umerous sigal processig applicatios i which DA algorithm is used. They are listed out i jourals as early as 989, where as DAA is as old as 974. DAA is easily used for implemetig DSP algorithms, because most of the sigal processig algorithms are i the form of sum of products or ier product of two vectors. DA is basically, a bit-serial computatio that forms a ier product of a pair of vectors i a sigle direct step. I computatios of sum of products, if oe of the vector operads is ow, distributed arithmetic ca be used. It uses loo up tables ad adders istead of multipliers. So there is a cosiderable reductio i the power cosumptio also, wheever we employ this DAA. A frequetly argued disadvatage is its apparet slowess because of its bit serial ature. This disadvatage is ot real if the umber of samples i each vector commesurate with the umber of bits i each vector elemet. i.e., the time required to iput eight, 8-bit words oe at a time i a parallel fashio is exactly the same as the time required to iput all eight words serially.

3 VOL. 8, O., JAUARY 3 ISS ARP Joural of Egieerig ad Applied Scieces 6-3 Asia Research Publishig etwor (ARP). All rights reserved. As a example, tae the computatio of the followig sum of products. y ) = K = o ( A X (4) Let A be the ow vector ad X be the iput data represeted i s complemet biary umber, scaled such that X < the X may be expressed as: DAA APPLIED TO A FLOATIG POIT BUTTERFLY MODULE I this wor, DAA is applied to do the butterfly computatio (Staley A. White) ad ot for computig the whole DFT. The sigal flow graph of the DIF butterfly that has bee implemeted is show i Figure-3. X B b= b = X X b (5) where X b is a biary variable or ad- X idicates the sig bit Substitutig equatio (5) i equatio (4) Figure-3: Sigal flow graph of a DIF butterfly. Here the iputs x, y ad W are complex ad the outputs X ad Y are also complex. i.e. B y( = AK [ X X = b= Ad ow this ca be expaded as AK X = = b B b= b y( = X b ] b A K (6) x = x _ real y = y _ real X = X _ real Y = Y _ real jx _ img jy _ img jx _ img jy _ img the above equatio is rearraged as follows: y( = [ xa xa x3a3 LLLL xa ] [ xa xa x3a3 LLL x A ] [ x A x A x A LLL x A ] M M M ( B ) [ x A x A x A LLL x A ] ( B ) ( B ) 3 3 3( B ) 3 ( B ) Each term withi the bracets deotes a biary AD operatio ivolvig a bit of a iput variable ad all bits of the coefficiet (Staley A. White, 989). The plus sigs deote arithmetic sum operatios. The expoetial factors deote the scaled cotributios of the braceted partial sum, to the total sum. A loo-up-table which stores all the possible sums of the coefficiets is costructed. The loo up table will be addressed by the th bit from all iput samples. Thus the arithmetic operatios have ow bee reduced to additio, subtractio, biary scalig ad accumulatio. (7) W = W _ real jw _ img Ad each ad every, real ad imagiary part of the data is represeted by a 3 bit IEEE sigle precisio, floatig poit umber. The outputs X ad Y are as give below. X = x y = ( x _ real y _ real) j( x _ img y _ img) (8) Y = ( x y) W Let ( x _ real y _ real) = G ad ( x _ img y _ img) = G The Y = ( G jg ) ( W _ real jw _ img) = ( GW _ real GW _ img) j( G W _ img G W _ real) (9)

4 VOL. 8, O., JAUARY 3 ISS ARP Joural of Egieerig ad Applied Scieces 6-3 Asia Research Publishig etwor (ARP). All rights reserved. Y _ real = ( GW _ real G W _ img) () Y _ img = ( GW _ img GW _ real) () From the above equatios, it is obvious that, six floatig poit adders ad four floatig poit multipliers are required to implemet a butterfly elemet i the covetioal way. But i this wor, we have suggested a techique usig distributed arithmetic, to obtai the real part ad imagiary part of the output Y. Thus equatios () ad () are realized usig DAA, istead of usig floatig poit multipliers ad adders. Here the W vector (twiddle factor) is a ow value. The umbers are represeted i sigle precisio floatig poit otatio. A 3 bit umber X i sigle precisio floatig S E poit is represeted as X = ( ). M Where S = Sig bit ( bit) E = Biased expoet (8 bits) M = Matissa (3 bits) Ad its value V is give by the expressio 3 S E V = ( ) M () I the equatios (9), () ad (), the values of the W_real ad W_img are tae as a 3 bit word ad the values of G ad G are goig to be treated bit wise as required i the distributed arithmetic algorithm techique. Therefore Y ( _ = ( ) real = ( GW _ real G W _ img) S S ) E 3 E 3 M W _ real = M W _ img (3) where M ad M are the 4 bit matissa of G ad G icludig the first hidde msb bit. If E = E the the same value ca be tae as the commo expoet value. If E E the, the expoet is made equal to the higher expoet value of the two ad thereby shiftig its matissa to the left by the required umber of positios. The Y _ real = E ( ) ( ) S S 3 3 M M W _ real W _ img (4) Assumig that both the sig bits are zero i.e. G ad G are positive values, ad the equatio (4) ca be expaded as: 3 [ M M M... M ] W real E 3 _ (5) Y _ real= 3 [ ] M M M... M W_ img Here M is the most sigificat bit ad M 3 is the least sigificat bit of the matissa part of G. ow the equatio ca be rearraged as per the distributed arithmetic techique as follows. E Y _ real= E Y _ img= ( M ) W_ real MW _ img ( M W_ real MW _ img) ( M 3W _ real M3W _ img) ( M ) W_ img MW _ real ( M W_ img MW _ real) ( M 3W _ img M3W _ real) 3 (6) (7) ow i equatio (6), each term i the braces is a biary AD operatio ivolvig a bit of the matissa of G ad the real or imagiary part of the twiddle factor. So its value ca be oe of the four combiatioal values of the real ad imagiary parts of the twiddle factor as show below. The expoetial factors deote shiftig or scalig of the value iside the braces. The sig idicates arithmetic additio ad here it s a floatig poit additio. The value iside the braces ca be calculated from the followig loo up table as the value of twiddle factor is already ow. Table-. LUT for S = S =. M M LUT Value - W_img W_real W_real - W_img The LUT for while the sig bits of both G ad G are is give i table. If the sig bits chage the the value of the LUT gets a sig chage accordigly. So together with the sig bits of G ad G, a 6 value LUT is 3

5 VOL. 8, O., JAUARY 3 ISS ARP Joural of Egieerig ad Applied Scieces 6-3 Asia Research Publishig etwor (ARP). All rights reserved. used. The real part of output Y is calculated by usig a scaled accumulator which accumulates the values from the LUT for each bit of the matissa. The same algorithm ca be followed to compute the imagiary part of output Y. Aother LUT of size 6 is used ad the similar DAA module is used. HARDWARE IMPLEMETATIO OF THE DAA BUTTERFLY EXPERIMETAL RESULTS The RTL modelig of the above desig is doe with Verilog HDL ad the formal verificatio is doe. The area reports of the butterfly module implemeted i the covetioal method usig 6 floatig poit adders ad 4 floatig poit multipliers is compared with butterfly implemeted usig DAA techique which requires oly 4 floatig poit adders ad two DAA uits. The desig is sythesized usig Syopsys Desig Complier with 45 m techology ode ad the et list is geerated. Also the area report is obtaied ad this desig is foud to be area efficiet. Table-3 shows the compariso betwee the covetioal Butterfly ad DAA Butterfly. Table-3. Area report i 45m techology. Parameter Covetioal BF DAA BF o. of stadard cells 7 5 Combiatioal 9446 sq sq. micro area micro Total area sq. micro sq. micro Figure-4. Architecture of a DAA butterfly. Equatios (6) ad (7) are implemeted usig the bloc diagram show i Figure-4. This is the geeral architecture of a bit serial DA. The iputs x ad y are added ad subtracted i the floatig poit adders. The real ad imagiary parts of output X are obtaied immediately, whereas for calculatig the output Y the address geerator blocs, LUTs ad scaled accumulators are used. These blocs elimiate the eed for multipliers. Thus it reduces the area requiremet ad also cosumes less power. The top level bloc diagram of our desig is viewed as i Figure-5. Here X ad X are the iputs, ad O ad O are the outputs. There are more cotrol iputs for loadig, readig LUT, shiftig, resettig etc. COCLUSIOS I this paper we have preseted a ovel desig for the butterfly elemet. The efforts are to mae the basic butterfly module more efficiet i terms of area, power ad also speed, as butterfly is the basic buildig bloc of FFT ad IFFT cores. The desig ca be used for recofigurable FFT processor also. This butterfly elemet is desiged for floatig poit umbers. Usually the DAA algorithm ad also the butterfly/fft processors are desiged for data represeted i the s complemet form. This floatig poit DAA BF is foud to be area efficiet as expected ad also shows reductio i the critical path. So it ca be used for desigig high speed, recofigurable FFT processors. I the ear future a recofigurable FFT/IFFT floatig poit processor will be desiged usig this ovel area efficiet butterfly elemet. REFERECES L. Wahammar DSP Itegrated Circuits. Academic Press. K. K. Parhi VLSI Digital Sigal Processig Systems: Desig ad Implemetatio. Joh Wiley ad Sos. A. V. Oppehei ad R. W. Schaffer. 98. Discrete - time Sigal Processig. Pretice Hall. Figure-5. Top view of DAA BF. Staley A White Applicatios of Distributed Arithmetic to Digital Sigal Processig: A Tutorial Overview. IEEE, ASSP Magazie, July. 4

6 VOL. 8, O., JAUARY 3 ISS ARP Joural of Egieerig ad Applied Scieces 6-3 Asia Research Publishig etwor (ARP). All rights reserved. Staley A White. A Simple Butterfly Arithmetic Uit. IEEE Trasactios o Circuits ad Systems. Vol. Cas8, o.4, April 8. Sasaloi T, Pérez-Pascual A ad Valls. J. Digit-serial Distributed Arithmetic Butterflies for FPGA. Christophe Bobda, Ali Ahmadiia ad J urge Teich. Geeratio of Distributed Arithmetic Desigs for Recofigurable Applicatios. Waye P Burleso ad Louis L Scharf. 99. A VLSI Desig Methodology for Distributed Arithmetic. Joural of VLSI Sigal Processig. Amit Siha ad Mahesh Mehedale Improvig Area Efficiecy of FIR filters implemeted usig Distributed Arithmetic. IEEE. 5

Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review

Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review pplicatios of Distriuted rithmetic to Digital Sigal Processig: Tutorial Review Ref: Staley. White, pplicatios of Distriuted rithmetic to Digital Sigal Processig: Tutorial Review, IEEE SSP Magazie, July,