Optimal area and impedance allocation for maximizing yield and enhancing performance in dual string DACs

Transcription

1 Graduate Theses ad Dissertatios Graduate College 009 Optimal area ad impedace allocatio for maximizig yield ad ehacig performace i dual strig DACs Thu Thi Ah Duog Iowa State Uiversity Follow this ad additioal works at: Part of the Electrical ad Computer Egieerig Commos ecommeded Citatio Duog, Thu Thi Ah, "Optimal area ad impedace allocatio for maximizig yield ad ehacig performace i dual strig DACs" (009). Graduate Theses ad Dissertatios This Thesis is brought to you for free ad ope access by the Graduate College at Iowa State Uiversity Digital epository. It has bee accepted for iclusio i Graduate Theses ad Dissertatios by a authorized admiistrator of Iowa State Uiversity Digital epository. For more iformatio, please cotact digirep@iastate.edu.

2 Optimal area ad impedace allocatio for maximizig yield ad ehacig performace i dual strig DACs by Thu Thi-Ah Duog A thesis submitted to the graduate faculty i partial fulfillmet of the requiremets for the degree of MASTE OF SCIENCE Major: Electrical Egieerig Program of Study Committee: adall L. Geiger, Major Professor Che Degag Tie Nguye Iowa State Uiversity Ames, Iowa 009 Copyright Thu Thi-Ah Duog, 009. All rights reserved.

3 ii TABLE OF CONTENTS LIST OF FIGUES LIST OF TABLES ABSTACT iv v vii CHAPTE. INTODUCTION CHAPTE. ALLOCATING AEAS AND IMPEDANCES 4. The INL variace of two resistors i parallel 4. The INL variace of dual ladders Strig DAC.. Normalized variace of the equivalet tap resistace.. Variace of the INL 5.3 The INL variace of Iterpolatio DAC with buffer.4 The INL variace of Iterpolatio esistor Strig DAC with buffer resistors 7.4. The ormalized variace of resistaces 9.4. The variace of INL 9 CHAPTE 3. SIMULATION ESULTS Simulatio results of dual-ladder Strig bit dual-ladder -strig DAC with 4-bit MSB ladder Simulatio results for differet values of ad Iterpretatio of σ INL m for Iterpolatio with buffer Simulatio results for = Simulatio results for differet value of ad 44 INL m 3.3 Iterpretatio of σ for Iterpolatio with buffer resistors Simulatio results for = Simulatio results for differet values of 49 CHAPTE 4. ASSESSMENT OF PIO WOKS AND VALIDATION OF ANALYTICAL ESULTS 5 4. Assessmet of Published esults 5 4. Validatio of INL variace formulatio 54 CHAPTE 5. CONCLUSIONS 57 APPENDIX A. APPENDIX B. σ max NOM OF DUAL LADDE DACS FO X=Z 59 σ max NOM OF DUAL LADDE DACS FO X=-Z 63 APPENDIX C. OF DUAL LADDE DACS WITH BUFFE ESISTOS 67 BIBLIOGAPHY 76

4 iii ACKNOWLEDGEMENTS 78

5 iv LIST OF FIGUES Figure. Parrallel esistors 4 Figure. A locus of critical poits 9 Figure 3. A Dual esistor Strig Ladder Figure 4. egio of Operatio for Dual-Strig DAC i the x - z plae 0 σ for a give z Figure 5. The miimum of NOM ( INL max ) Figure 6. ( ) σ w.r.t. x NOM INL max Figure 7. The Iterpolatio DAC with buffers 3 Figure 8. Dual esistor Strig with Buffer esistors 8 Figure 9. INL profiles of the dual ladder DAC for x = Figure 0. INL profiles of the dual ladder DAC for x = Figure. INL profiles of the dual ladder DAC for x = Figure 3. Effect of selectio of impedace ad area 40 Figure 4. w.r.t the voltage positio tap =0, =4 4 Figure 5. w.r.t x for =4, = 6 43 Figure 6. w.r.t. x for = 3, 4, 5 44 Figure 7. The stadard deviatio profile for z=0. 47 Figure 8. The stadard deviatio profile for z= Figure 9. Characterizatio of desig reported i [Pelgrom, M. J. M. (990)] i the x-z plae 53 Figure 0. The stadard deviatio profiles for Pelgrom case 55 Figure. The stadard deviatio profiles for the case x=0.793, z= Figure. The stadard deviatio profiles for x=0.7, z=

6 v LIST OF TABLES Table. Normalized Variace with Differet Impedaces Ad Areas 0 Table. Simulatio results of σ 38 max NOM σ NOM INL m of the dual ladder DAC as varies 4 Table 4. The miimum of Stadard deviatio of INL ad x to obtai the miimum value of the stadard deviatio of the INL 45 Table 3. The optimum ( ) Table 5. The optimum values of for =0, =4 49 Table 6. The average values of 50 Table 7. σ for =4 59 Table 8. Table 9. Table 0. Table. Table. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 0. Table. Table. Table 3. Table 4. max NOM σ for =5 59 max NOM σ for =6 59 max NOM σ for =7 60 max NOM σ for =8 60 max NOM σ for =9 60 max NOM σ for =0 6 max NOM σ for = 6 max NOM σ for = 6 max NOM σ for =4 63 max NOM σ for =5 63 max NOM σ for =6 63 max NOM σ for =7 64 max NOM σ for =8 64 max NOM σ for =9 64 max NOM σ for =0 65 max NOM σ for = 65 max NOM σ for = 66 max NOM Table 5. The miimum for = 4, = 67 Table 6. The miimum for = 5, = 68 Table 7. The miimum for = 6, = 68 Table 8. The miimum for = 6, =3 69 Table 9. The miimum for = 7, = 69 Table 30. The miimum for = 7, =3 70

7 vi Table 3. The miimum for = 8, = 70 Table 3. The miimum for = 8, =3 7 Table 33. The miimum for = 8, =4 7 Table 34. The miimum for = 9, = 7 Table 35. The miimum for = 9, =3 7 Table 36. The miimum for = 9, =4 73 Table 37. The miimum for = 0, = 73 Table 38. The miimum for = 0, =3 74 Table 39. The miimum for = 0, =4 74 Table 40. The miimum for = 0, =5 75

8 vii ABSTACT The relatioships betwee yield, area, ad impedace distributio i 3 differet types of dual-strig DACs are developed. Optimal area allocatio ad impedace distributio strategies for maximizig yield ad ehacig performace are itroduced. Simulatio results show that a factor of or more reductio i area for a give yield is possible if typical area/impedace allocatios are replaced with a optimal area/impedace allocatio.

9 CHAPTE. INTODUCTION Dual-ladder resistor strig digital aalog coverters (DACs), which icorporate fie strig least sigificat bit (LSB) ladders i parallel betwee two successive coarse ladder taps are widely used i idustry [Boylsto, L. E. et al. (00), Pelgrom, M. J. M. (990), Maloberti, F. et al. (996), ivoir,. et al. (997)]. Whe properly desiged, the dual-ladder structures iherit most of the advatages of a strig DAC such as mootoicity, speed, ad versatility [Boylsto, L. E. et al.]. The major advatage of the dual-ladder DACs with a reduced umber of resistors i the coarse ladder comes at the layout stage where layout complexity ca be reduced sice a commo cetroid layout of the coarse strig resistors will effectively cacel liear gradiet effects [Maloberti, F. et al. (996)] for the etire DAC. It is well kow that layout cotributes a very importat part to the liearity performace of the DAC. Differet layout approaches provide differet itegral No- Liearity (INL) performace. Covetioal wisdom suggests that the value of the coarse strig resistors should be small ad the area for the coarse strig resistors should be large for a properly desiged dual-ladder DAC [Plassche,. va de (003)]. Although the area allocatio i the dual-ladder DAC used i [Pelgrom, M. J. M. (990)] was ot give, a die photograph shows that the total area for the fie resistor strig was approximately 7 times that for the coarse strig while the ratio of the total series fie resistace to the total series coarse resistaces was about 38. Other research results are based upo the assumptio that the uity fie resistor values are a power of times the uit coarse resistor values [Maloberti, F. et al. (996)]. Surprisigly, authors discussig these heuristic approaches to allocatio of area ad impedace values betwee the coarse ad fie resistors i the strigs are silet about

10 the issue of optimality. A optimal strategy for maximizig INL yield i dual-strig DACs requires allocatio of silico area ad impedaces of the coarse ladder ad the fie ladder strigs to miimize the effects radom local variatios i the sheet resistace o the INL performace. Ufortuately, there is a little research suggestig how areas ad impedaces related to the liear performace of the dual ladder DAC whe mismatch of resistors is cosidered. As a result, may egieers allocate excessive area to achieve a required yield or obtai a poor yield to meet a fixed area target without realizig that the excessive area or the yield loss is ofte due to o-optimal allocatio of area ad impedace betwee the strig ladders. Although INL yield ca be improved by icreasig area i either the coarse or fie ladder, it this is doe i a o-optimal way, it will result i a icrease i die costs ad icreases i parasitic capacitors which will reduce the speed ad thus limit the high frequecy performace of the circuit. As with ay strig DAC, the liearity performace of the dual-strig architecture is maily limited by the presece of process ad gradiet effects ad the radom mismatch of the resistors i the ladders. If the areas of the resistors are ot too large, the gradiet will be early liear (first-order). The effects of first-order gradiets o ratio matchig ca be caceled or miimized by appropriate placemet, segmetatio ad the use of commocetroid layout methods [Hastigs, A. (000)]. If gradiet effects are cacelled, the radom mismatch of the resistors i the ladders becomes the domai cotributor to the oliearity performace of this architecture. This mismatch is usually domiated by the local radom variatios i the sheet resistace throughout the body of the resistors. The resultat radom variatios i the idividual resistors are usually modeled as a Gaussia radom variable. It is well-kow that

11 3 maximizig the resistor area is effective for miimizig the effects of local radom variatios o the overall mismatch of the resistors [Pelgrom, M. J. M. (990)]. Thus, desigers routiely mark tradeoffs betwee area ad matchig accuracy. I this work, liearity performace tradeoffs betwee area i the coarse strig ad area i the fie strig ad betwee the resistace values i the coarse strig ad the resistace values i the fie strig are discussed. The issue of optimal area ad impedace allocatio strategies for miimizig the INL is addressed.

12 4 CHAPTE. ALLOCATING AEAS AND IMPEDANCES I this chapter, three differet types of dual ladder strigs are discussed. The cocept of how area ad impedace allocatio affects the performace of resistor strigs ca be more easily described by cosiderig first a much simpler circuit comprised of two resistors i parallel. This is the topic of the followig sectio.. The INL variace of two resistors i parallel Figure. Parrallel esistors A simple circuit comprised of two parallel resistors is discussed i this sectio. This circuit is useful for providig isight ito the tradeoffs betwee area, impedace values ad performace of resistor circuits that are plagued by local radom variatios i the sheet resistace. The ormalized variace of the equivalet resistace of the two parallel resistors will be characterized i detailed. The results will provide isight ito the aalysis ad optimizatio of the itegral oliearity (INL) of the dual ladder resistor strig that is discussed i the ext sectio. Cosider the two resistors show i the Figure where the resistace values ad active layout areas are,, A ad A. The equivalet resistace of the parallel

13 5 combiatio is =. For otatioal coveiece, the variables u ad v are defied by + the expressios A = () u A TOT v = () where A TOT is the total area of two resistors. It is apparet that (u,v) are restricted to the ope uit square i the u-v plae. If it is assumed that oly liear gradiet affects are preset i the layout of the two resistors ad if a commo cetroid layout method is used, liear gradiet effects i are cacelled ad each of the resistors ca be decomposed ito the sum of the omial resistace N ad a compoet due to the local radom variatio i the sheet resistace. Mathematically, for each resistor, this relatioship ca be repressed as i = in + iwhere in is the omial value of the resistace at the geometric cetroid of the layout ad i is the radom compoet of i. The radom compoets of ad are geerally assumed to be ucorrelated. For useful resistors i matchig-critical applicatios, it ca be assumed the i is small compared to in. With this otatio, the equivalet resistace ca be expressed as = ( N + )( N + ) ( ) N N (3) By factorig out the omial value of resistors, (3) ca be rewritte as:

14 6 = + + NN N N N + N + + N + N ( ) (4) It is apparet from (4) that is a radom variable that is oliearly depedet upo the radom variables ad. Because of this oliear relatioship, the probability desity fuctio of becomes uweildly makig it difficult to get much isight ito the radom ature of. We will ow focus o liearizig the radom parts of so that the statistical properties of ca be determied. Sice the radom part of the resistors is assumed to be small compared to the omial part, the term i the deomiator ivolvig the radom compoets ca be expaded i a Taylors series ad trucated after first-order terms to obtai the expressio + + ( ) N + N N N N + N N + N N N (5) If secod-order terms are eglected, (5) ca be rewritte as N N + + ( ) N + N N N N + N N + N (6) It ca be observed from (6) that the expressio for has bee liearized i terms of the radom variables ad. It follows that the ormalized radom compoet of the resistace ca be expressed as N N N = + ( + ) ( + ) N N N N N N (7)

15 7 Equatio (7) is ow i the form of a weighted sum of ucorrelated radom variables. It follows from (7) that the variace of the ormalized local radom compoet ca be expressed by N + N σ N + N N + N σ = σ (8) N N N It is well kow that the ormalized variace of a resistor is iversely proportioal to the layout area of the resistor [Hastigs, A. (000), Lae, W. ad Wrixo, G. (989), Li, Y. ad Geiger,. (00)]. The proportioality costat is charaterized by the process parameter A ρ N. This proportioality ca be expressed as A ρn i A in i σ = (9) as Thus, it follows from (A), (A) ad (6) that the ormalized variace ca be writte A ρn () ( ) ( ) σ = v + v (0) A TOT u - u N This variace of the ormalized resistace ca be miimized by equatig the partial derivatives with respect to both u ad ν to zero. It follows from (7) that the partial derivative of the variace of the ormalized resistace with respect of u is give by the expressio σ A N ρn ( u v)( u+ v uv) = u ATOT u ( -u) ()

16 8 Correspodigly, the partial derivative of the variace of the ormalized resistace with respect to v ca be expressed as σ AρN v u N = v ATOT u-u ( ) () It thus follows from () ad () by settig the partial derivatives to 0 that that a miimum will be obtaied if u ad v satisfy the relatioship u = v (3) This result ca be summarized i the followig theorem. Theorem : For a fixed total area of two resistors deoted as ad, the variace of the radom compoet of the ormalized resistace of the parallel coectio of the two resistors assumes a miimum value if ad oly if the ratio of the area of to the total resistor area is equal to the ratio of the resistace of the parallel combiatio of the two resistors to the resistace of. The locus of poits i the u-v plae that provides miimum variace is a straight lie as show i Figure.

17 9 Figure. A locus of critical poits Substitutig u = v ito (0), if follows that the miimum variace or the ormalized resistace is give by A ρn A TOT N MIN σ = (4) The miimum variace is depedet upo both the process parameter ad area. To establish a appreciatio for the pealty icurred if o-optimal area partitioig or ooptimal resistace partitioig is used, the ormalized variace is defied as σ σ A N TOT σ σ A ρn N N NOM N MIN = = (5) Deviatios i the ormalized variace of the ormalized resistace from the optimal value for differet resistace ratios ad differet area ratios are summarized i Table.

18 0 Table. Normalized Variace with Differet Impedaces Ad Areas / ( + ) A / (A + A ) If (u,v) is o the optimal straight lie, the ormalized value is equal to as idicated by the correspodig diagoal etries i this table. But it ca be observed that if either the area partitioig or the resistace partitioig or both differ sigificatly from their optimal values, the pealty i variace is dramatic as ca be observed by the etries i the upper left ad the lower right parts of this table. The above aalysis shows that, for the same values of resistace ad area of the circuit, as log as the ratio of the layout area of oe resistor to the total area of the circuit is equal to the ratio of the equivalet resistace to its resistace, the variace of the equivalet radom resistace is miimum. Correspodigly, if the layout area of oe resistor is very big or very small ad the resistace values are ot sized favorably, the variace will be very large. As expected, the value selected for the total resistace is arbitrary provided the resistace partitioig ad area partitioig is doe i a optimal way.

19 . The INL variace of dual ladders Strig DAC A A V m eqi Figure 3. A Dual esistor Strig Ladder I this sectio, the performace of a dual ladder resistor strig DAC is characterized. Specifically, the effects of area ad resistace partitioig betwee the coarse ad fie strigs o the variace of the itegral oliearity (INL) are ivestigated. The widely-used dual-strig ladder structure is show i Figure 3. The coarse ladder is comprised of coarse resistors each of resistace value ad area A. A fie strig is coected i parallel with each coarse-strig resistor. Each fie strig provides tap voltages as show i Figure 3. Each resistor i the fie strig ideally has a resistace of

20 ad a area of A. If the tap voltages are selected with switches ad if this selectio is doe i such a way that ay oe of the tap voltages ca be selected with a Boolea iput variable, the dual-strig ladder forms a -bit DAC where = +. For otatioal coveiece, the switches ad the Boolea iput variables are ot show i Figure 3 but throughout this thesis o attempt will be made to distiguish betwee the dual-strig ladder ad the correspodig DAC that is derived from this ladder. Sice emphasis will be focused exclusively o the effects of the dual-strig ladder o the performace of the DAC, the switches ad the Boolea logic eeded to form the DAC from the dual-strig ladder will be assumed to be ideal throughout this thesis. With this uderstadig, the total area of the DAC is ( ) A = A + A (6) TOT Itergral oliearity (INL) error is used to measure the static accuracy of the coverter. For a -bit DAC, the INL m of the tap voltage m ( 0 m < ) is the differece betwee the voltage at the tap m ad the idea voltage VEF m i LSB. The INL is the maximum of INL m for 0 m <. The variace of the INL m o each of tap voltages is derived ad the allocatio of areas ad resistor values o both ladders is obtaied that provides the miimum value of the maximum error i the INL profile... Normalized variace of the equivalet tap resistace As was the case for the two resistor etwork, it is coveiet to ormalize the impedaces ad the areas i the dual-strig ladder. The ormalizatio factors x ad z are

21 3 defied to represet the ratio of the coarse ladder area to the total area of DAC ad the ratio of the total equivalet resistace of the DAC to the total resistace o the coarse ladder x A = ATOT (7) z = (8) TOT where A is the area of a sigle coarse resistor ad ( //( ) TOT =. The resistace i a coarse ladder tap i is defied to be the parallel combiatio of the coarse resistor i positio i ad the fie resistors parallelig this coarse resistor. Thus, the equivalet resistace i coarse ladder tap i ca be expressed as = i j= eq,i + i j=,ij,ij (9) If a commo cetroid layout is used, the gradiet compoet of this equivalet resistor ca be igored ad resistor ca be decomposed ito the sum of the omial resistace ad the compoet due to the local radom variatios. It thus follows that

22 4,ij,i j= + + N N N N eq,i = N + N +,ij j= + N + N (0) where the subscript N is used to deote the omial part of a resistor ad the subscript is used to deote the radom part of the resistor. It is apparet that the radom variable eqi is itself oliearly depedet upo a large umber of separate radom variables. Followig the approach used i the two resistor case discussed i the previous sectio, we will ow liearize the radom compoet of eqi. With this goal i mid, the deomiator of (0) ca first be expaded i a Taylors series. Sice the radom compoets of all radom variables i (0) are small compared to their omial compoets, after multiplyig out the resultat product terms i the umerator ad trucatig the resultat expressio after the first-order terms, we obtai:,ij,ij N N,i j=,i j= eq,i N + N N N N + N N + N () resistace is It follows that the ratio of the equivalet resistace to the ormalized equivalet

23 5,ij eq,i,i N j= N + + eqn,i N,i N + N N N + N () Sice the radom variables i () are ucorrelated, it follows that the ormalized variace of the equivalet resistace i ay coarse ladder tap ca be expressed by σ σ σ N N = + eq N + N N + N ( ) N eqn N (3) It follows from (4), (5) that (3) ca be writte as σ = + A ρn N A TOT N A TOT eq A TOT N + N A N + N ATOT - A eqn (4).. Variace of the INL Up to this poit emphasis has bee focused o the statistical characterizatio of the resistors i the DAC. I this sectio emphasis will be directed to the statistical characterizatio of the INL. The statistical characterizatio of the INL of the dual-strig DAC itself is very challegig sice it is a order statistic of radom variables. Emphasis i this sectio will focus o the much easier but still tedious task of characterizig the idividual INL m variables. The output voltage at the tap m = p + q (5) for 0 p < ad 0 q <, of the fie strig ladder ca be expressed as

24 6 V V = + p EF j= m eq,i eq,p+ i= eq,i i= j= Neglectig the process ad gradiet compoets of the resistors, each resistor ca be decomposed ito the sum of a ormial resistace ad the local radom resistace. It thus follows from (6) that the tap voltage ca be expressed as : q j j (6) j j= q N + p q N eq,i EF j= V eq,p+ m eqn eqn p eqn eqn eq,i j i= j= eqn + N + eqn N V = p q (7) where N ad N are as defied previously ad eqn = N //( N ). As was the case i the previous sectio, the expressio for V m is a highly oliear fuctio of the radom resistive variables. But, sice i practical applicatios the radom compoet of each resistor will be small compared to its omial part, this oliear fuctio ca be liearized. As part of the liearizatio, each factor of the deomiators ca be expaded i a Taylors series ad trucated after the first-order terms to obtai: p q eq,i eq,i j j eq,i V EF i= i= eq,p+ j= j= i= V m = p + - +q peqn eqn eqn q N N eqn (8)

25 7 By expadig equatio (8) ad eglectig higher-order terms ivolvig the radom variables, it follow that q p eq,i j eq,i j eq,i V EF i= - i= eq,p+ j= - j= - i= V m = p+q+ - p +q + - q - q (9) eqn eqn eqn N N eqn The INL profile i LSB (V LSB =V EF / ) is the differece betweee V m ad the ideal tap voltage VEF m i LSB. I the equatio (9), the first two items of the sum are equal to m. Therefore, the INL m ca be writte as a liear weighted sum of ucorrelated radom variables as: p eq i ( ) + ( ), eq, p+ INLm = p q q p q ( ) ( ) i= eqn eqn q eq, i i, i, + p q + q q i= p+ eqn i= N i= q+ N (30) expressed as: Sice the radom variables i (30) are ucorrelated, the variace of INL m ca be σ ( ) ( ) = p q p+ p + q ( p ) INL σ m eq eqn ( q p q ) σ q( q ) q ( q) N (3) It follows from (6) ad (7) that σ ca be expressed as: N A ρn AρN σ = = A A ( x) (3) N From (4),(3), ad (3), it follows that TOT

26 8 σ INL m ( ) A ρn z -z = + -p -q p+ p +q ( -p-) ATOT x -x ( ) ( ) ( ) - - A - - ρn ( ) ( ) ( ) ( ) + q-p -q + q -q +q -q ATOT -x (33) elative size ad impedace iformatio is carried i the two variables x ad z. For coveiece, the ormalized variace of INL m is defied as: σ A ( INL ) = σ (34) m A TOT NOM m INL ρn The fuctio (33) ca be miimized by differetiatig (33) with respect to x ad z ad NOM INL m settig the patial derivative to zero. Thus differetiatig σ ( ) with respect to z, we obtai ( ) ( ) ( ) ( ) ( ) σ A ρn (,)= ( ) z x INLm x z p q p q p q p q p z ATOT x x σ INLm z Settig ( x, z) = 0, it follows that x = z. Notice this solutio is idepedet of m ad idepedet of A ρn /A TOT. Therefore, for a give x, the ormalized variace of the local radom compoet i the dual-strig DAC is miimum if the ratio of the total impedace to the coarse ladder impedace is equal to the ratio of the layout coarse area to the total area of the circuit. This is summarized i the followig theorem. (35) Theorem : For a give x ad for all m, the variace of INL m for a dual strig DAC is miimized whe z = x where x = A C /A TOT ad z = TOT / C. Although for a give value of x, a local miimum of the variace of INL m i the variable z ca be obtaied, there is o local miimum i the ope uit square i the (x,z)

27 9 plae. But, it ca also be show that if x = z, the the variace decreases with x. Ad, i the latter case, the decrease i variace as x approaches 0 is very small. These observatios ca be summarized i the followig theorems. Theorem 3: For all m, the variace of INL m for a dual strig DAC does ot assume a local miimum i { (x,z) 0 < x <, 0 < z < }, where x = A C /A TOT ad z = TOT / C. Theorem 4: For all m, the variace of INL m for a dual strig DAC decreases mootoically as x approaches 0 o the x = z locus where x = A C /A TOT ad z = TOT / C. Theorem 5: The derivatives of the variace of INL MAX for a dual strig DAC alog the x=z lie i the x-z plae is small for 0 < z < ε, where 0 < ε «where x = A C /A TOT ad z = TOT / C. Although Theorem 5 states that the variace chages very slowly alog the x=z lie i the x-z plae, it should be emphasized that this Theorem does ot state that the variace chages very slowly ear the origi of the x-z plae ad, i fact, it ca chage sigificatly ear the orgi at poits that are ot o the x=z lie. The ope uit square i the x-z plae is show i Figure 4 alog with the x = z lie which represets the optimal value of z for a give value of x. It thus follows that if a desig has paramaters (x,z) that are close to the x = z lie, the variace of INL MAX should be ear optimal. A tight lower boud o the variace occurs o the boudary of the uit square at the poit (0,0). As Theorem 5 idicates, whe operatig o the x = z lie ear the orgi, the

28 0 variace of INL MAX should be ear the tight lower boud. It will be show i Chapter 3 that whe operatig with paramaters that deviate sigificatly from the x = z lie, the variace of the INL MAX may be sigificatly larger tha optimal. Figure 4. egio of Operatio for Dual-Strig DAC i the x - z plae As a example, the miimum INL as a fuctio of z, for a 0-bit dual ladder strig DAC with 4 bits allocated to the coarse strig is ploted i Figure 5 for differet values of x. From this plot it is apparet that the local miimum is rather shallow for x aroud 0.5 but becomes much steeper for extreme values of x approachig 0 or. It is apparet that if a o-optimal allocatio of area or impedace is used, the pealty i the variace, ad correspodigly the yield, ca be quite large. It is also show the smaller values of x are, the smaller variace is obtaied although the differeces i the miimum INL do ot chage dramatically as x is chaged. If there is o coarse ladder, which would correspod to x=z=0, σ(inl) will assume its miimum value. But we ca ot elimiate the coarse ladder because without the coarse ladder, the gradiet effects would eed to be maaged by the fie strig

29 resistors ad commo cetroid layouts that cacel the gradiet effects would be difficult to realize if the resolutio of the DAC was very large. ( ) INL max σ NOM 0 0 z Figure 5. The miimum of ( ) σ for a give z NOM INL max A plot of the ormalized variace for differet values of x alog the x=z locus is show i Figure 5. From Figure 5 it ca be set that the miimum ormalized stadard deviatio is 5 but the miimum is very shallow o the x = z locus with a icrease above the miimum of oly 3% for x = z = 0.5 ad of oly 48% eve whe x=z=0.95. Thus, the beefits of havig extreme values of x ad z provided x = z are ot substatial. But, for a give z, whe x deviates from z, the pealty i the variace ad correspodigly the yield is sigificat. This ca be see i Figure 6 where the maximum variace is plotted versus x for z fixed at 0.5.

30 σ NOM ( ) INL max 4 x=0.95 x=0.0 x=0. x= z Figure 6. ( ) σ w.r.t. x NOM INL max.3 The INL variace of Iterpolatio DAC with buffer I this sectio, a differet dual-ladder DAC is cosidered. This structure uses buffers to coect the fie strig to the coarse ladder thus dramatically reducig the total umber of resistors eeded by the fie strig. This approach also elimiates the loadig of the coarse strig by the fie strig at dc. This structure is show i Figure 7. As i the previous sectio, emphasis will be placed o characterizig ad miimizig the variace of the INL m i this sectio. For the buffered structure of Figure 7, the coarse ladder cosists of coarse resistors of resistace value ad area A. The fie strig is comprised of resistors, each with a resistace of ad a area A. For each coectio of the itropolator to the coarse strig, the iterpolator provides to the output tap voltages.

31 3 V EF + - F V out F F F + - Figure 7. The Iterpolatio DAC with buffers As for the dual ladder structure i the previous sectio, the total umber of tap voltages is, where = +. The variace of the INL m o each of tap voltages will be derived ad the allocatio of area ad resistace o both ladders to obtai the miimum value of the maximum error i the INL profile will be obtaied. Let x be the ratio of the coarse ladder area to the total area of DAC, x A = ATOT (36)

32 4 where A TOT = A + A. The output voltage at the tap m = p + q, 0 p < ad 0 q <, of the fie strig ladder is expressed as: V = j V p EF j = + + i=,i j i= j= m,i,p q (37) Neglectig the process ad gradiet compoet of the resistor, it follows that V m q j q + p N q N, i V EF, p+ = p + N + + N (38) p N N, i j + + N N N N where the subscripts ad N refer to the radom part ad the omial part of the resistaces. This fuctio is highly oliear i the radom compoets of the resistaces but sice the radom compoets are assumed small compared to the omial part of the resistors, this fuctio ca be liearized. To liearize this fuctio, first each factor of the deomiator ca be expaded i Taylors series ad trucated after the first-order terms to obtai: q p,i,i j j,i EF V i= i=,p+ j= j= i= pn N N qn N N V m = p q (39)

33 5 Expadig equatio (39) ad eglectig the higher-order terms, we obtai the followig equatio: p q V = p q p q q q m, i, i j j i, VEF i= i= p, + j= j= i= N N N N N N (40) The INL profile i LSB (V LSB =V EF / ) is the differece betweee V m ad the ideal tap voltage mv EF / i LSB. I equatio (40), two first items i the brackets are equal to the order of the tap m. Thus, the INL m ca be writte as: p,i ( ) + ( ),p+ INL m = p q q p q (4) ( ) ( ) i= N N q,i,i,i + p q + q q i= p+ N i= N i= q+ N Equatio (4) is ow the weighted sum of ucorrelated radom variables ad thus, the variace of INL m ca be expressed as: σ ( ) ( ) = p q p+ p + q ( p ) INL σ m N (4) + ( q p q ) + σ q( q ) + q ( q ) N By subsitutig N ρ A σ = N, A A σ ρn = = A ad x= A ρ N A AT A ATOT N, (4) ca be writte as σ ( ) ( ) A = p q p+ p + q ( p ) ρn INL m ATOT x ( q p q ) q( q ) q ( q) x (43)

34 6 This variace is depedet upo the total area, A TOT, ad the process parameter A ρn. By ormalizig the variace by A ρn /A TOT, the effects of x ad m o the INL m ca be practically depicted. With this ormalizatio, (43) simplifies to σ ( ) ( ) ( INL )= p q p + p + q ( p ) x NOM m ( q p q ) q( q ) q ( q) x (44) To fid the optimum of area allocatio, the derivative of (44) with respect to x is NOM INL m take ad set to zero. Thus, differetiatig σ ( ) with respect to x, we obtai: σ NOM ( ) ( ) p q p+ p + q ( p ) ( INL ) m = x x ( q p q ) q( q ) q ( q (45) + + ) x + ( x) σ ( ) Settig NOM INL m = 0, it follows that x b ± bb x = (46) b b for b + = ( p q ) p + ( q p q ) ( p + q ) ( p ) (47) b ( q ) + q ( q) = q (48)

35 7.4 The INL variace of Iterpolatio esistor Strig DAC with buffer resistors A third variat of the dual strig DAC is show i Figure 8. Covetioal wisdom teaches that this structure elimiates the eed for the buffers of the previous structure ad uses extra replacemet resistors to prevet havig the iterpolatig fie-strig resistor load a coarse strig resistor. Although the omial value of the replacemet resistor is ideally equal to that of the fie iterpolatio strig, the area ca usually be made much smaller. I this sectio, the DAC of Figure 8 the variace of INL of this DAC will be characterized. The coarse ladder is cosists of coarse resistors of resistace value ad area A. A fie strig is coected i parallel with oly oe coarse resistor at ay time ad determies tap voltages. Each replacemet resistor 3, havig a omial resistace of ad a area of A 3, is coected i parallel with a resistor of the coarse ladder if the fie strig iterpolator is ot coected to a give coarse ladder resistor. Thus, there is always - replacemet resistors alog with the fie-strig iterpolatio circuit coected i parallel with each of the coarse strig resistors.

36 S 3 S S 8 V EF S S3 S 3 V out Figure 8. Dual esistor Strig with Buffer esistors As was the case for the two previous dual-strig resistor arrays, the total umber of tap voltages is, where = +. The variace of the INL m o each of tap voltages will be derived ad the allocatio of areas ad resistace values o both ladders will be give that provides a miimum value of the maximum error i the INL profile.

37 9.4. The ormalized variace of resistaces I cotrast to the previous two circuits where the switch impedace did ot affect the static performace of the DAC, i this structure, the switch impedace is i series with either the replacemet resistor or the fie-strig iterpolatio resistor ad, as such, cotributes to the resistaces i the ladder. To keep the aalysis maageable, it will be assumed that the switches are all ideal ad have 0Ω o impedace. For coveiece, defie eq = // ( ) ad eq3 = // 3. Sice ideally 3 =, it follows that eq = eq3. Thus, the omial value of these resistors are equal to each other, eqn = eq3n = eqn. As i the Sectio., from (4), the ormalized variace of the equivalet resistace eq is give by the expressio σ eqn A N ρ eqn AρN = + eq N A N A eqn (49) Similarly, the ormalized variace of the equivalet resistace eq3 is σ eqn AρN eqn AρN = eq 3 + N A 3N A3 eqn (50).4. The variace of INL Defie z to be the ratio z = (5) TOT ad aa k, k =,, 3, to be the total area of the coarse strig, the fie strig, the replacemet resistors 3, over the total resistor area:

38 30 a A = (5) ATOT a A = (53) A TOT a 3 A3 = (54) A TOT The output voltage at the tap m = p + q, 0 p ad 0 q, of the fie strig ladder for the case p > 0; q > 0 ca be expressed as q p j VEF j V m = = eq,i + eq,p + i= eq,i + eq, p+ j i= i, p+ j= (55) Neglectig the process ad gradiet compoets of the resistor, it follows that V V EF m = p eq,i + eq,i + eq,p+ i i p = = + eqn + eqn q j j q = N + p qn eq,i eq,p+ peqn + + eqn + p eqn eqn j j = N + N (56) where the subscripts ad N deote the radom part ad the omial part of the correspodig radom resistace value. As i the previous sectios, V m is highly oliear i the radom variables but sice the radom part of the resistaces is assumed to be small

39 3 compared to the omial part, this equatio ca be liearized. As the first step i the liearizatio process, each factor of the deomiator will be expaded i a Taylors series trucated after the first-order terms to obtai: p eq,i eq,i V EF i i= i p+ =, eq, p+ V m = p p + eqn eqn eqn q j j eqp + eq,i, j = j = + q + + i= i, p+ eq, p+ eqn q N N eqn eqn Expadig equatio (5) ad eglectig secod-order ad higher terms i the radom variables, we obtai the followig expressio: (57) p eq,i eq,i EF i i i p = =, + eq eqn eqn eqn V = p p p q m V + + (58) q j j eq,i eqp j j ii p, + = = =, + eqp, + + q + q q q eqn N N eqn eqn This expressio is ow i the form of a weighted sum of ucorrelated radom variables. The INL profile i LSB (V LSB =V EF / )is the differece betweee V m ad the ideal tap voltage [m(v EF / )] i LSB. The first two terms i the brackets of equatio (53) are equal to the tap umber m. Thus, the INL m = V m - mv EF / ca be writte as:

40 3 INL = p p q m p eq,i eq,i i i i p eq = =, + eq, p+ + eqn eqn eqn eqn q + q q q j j eq,i j = j = ii =, p + eqp, + N N eqn eqn (59) Thus, the variace of INL m ca be expressed as: σ ( ) ( ) = p q p+ p + q ( p ) INL σ m eq eq N ( q p q ) σ q( q ) q ( q) + σ + + eq eqn N (60) Subsitutig σ eq eqn eqn A ρn A = eqn ρn +, (6) N A N A σ eq eqn = eqn N A ρn A + eqn 3N A ρn A 3 (6) N ρ A N σ = (63) A ad rearragig the order of terms i (55), we get the followig equatio:

41 33 σ A ρn eqn INL ( ) ( ) m A N = p q p+ p + q ( p ) ( ) A ρ N ( ) q p q q q q ( q ) A (64) eqn ( q p q ) N + ρn eqn ( ) ( ) A + p q p p q ( p ) + + A3 3N For otatioal coveiece, defie M, M,M 3, ad M 4 by the expressios ( ) ( ) ( ) M = p q p+ p + q ( p ) + q p q ( ) ( ) M = p q p+ p + q ( p ) ( ) M3 = q p q ( ) ( ) M4 = q q + q q (65) (66) (67) (68) The paramaters M..M 4 are depedet upo the idex umber but idepedet of model parameters, resistace values, ad area. The (59) ca be writte as: A σ ( ) ( N ) z z ρ INL m z = M + M + M 4 + M 3 ATOT a a3 a a (69)

42 34 CHAPTE 3. SIMULATION ESULTS I the previous chapter, aalytical formulatios were preseted that characterizes the statistical performace for three differet types of dual ladder DACs. These parametric formulatios provide the INL m at each DAC output code ad are strogly a fuctio of the umber of bits of resolutio i the coarse strig, the umber of bits of resolutio i the fie strig, as well as the impedace ad area allocatios betwee the coarse ad fid strig resistors. As such, it is challegig to obtai a practical uderstadig of the beefits ad limitatios of various area ad impedace allocatio schemes. I this chapter, computer simulatios are preseted that give isight ito the beefits obtaied by optimally allocatig impedaces ad area betwee the coarse ad fie resistor strigs. 3. Simulatio results of dual-ladder Strig I this sectio the performace of the dual-ladder Strig of Figure 3 will be ivestigated. Mathematically, the INL performace of this structure is characterized by equatio (33) bit dual-ladder -strig DAC with 4-bit MSB ladder Iitially, the performace of a 0-bit dual-ladder -strig DAC with a 4-bit MSB ladder will be cosidered. This structure is defied by the parameters =4 ad =6 i the variace of INL m give i equatio (). This variace is depedet upo the total area, A TOT, ad the process parameter A ρn. By ormalizig the variace by A ρn /A TOT, the effects of x,z, ad m o the INL m ca be practically depicted. With this ormalizatio, (33) simplifies to

43 35 σ NOM ( INL ) m = + z ( z) + ( ) ( ) ( ) p q p + q p q x x ( p + q ) ( p ) + q( q ) + q ( q) ( ) x where x, z, ad m are as defied i (7), (8) ad (5). (70) The ormalized stadard deviatio of the INL m for x ad z {0.0, 0.5, 0.95} are show i Figure 9, 0,. From these plots, it is apparet that the INL assumes a maximum ear the mid-code tap voltage correspodig to code 5. Cosistet with Figure 4, it ca be see from Figure 9 that the maximum ormalized stadard deviatio for x = z = 0.0 is very close to the global miimum of. The plot of Figure 9 which is for x small correspods to the situatio where most of the area is allocated to the fie resistors. Figure 0, where x = 0.5, correspods to the situatio where equal area is allocated to the coarse ad fie resistor strigs whereas Figure, where x=0.95 represets the situatio where most of the area is allocated to the coarse strig. I Figure 9, whe z is large, the voltage at the taps of the coarse strig plays the major role i the oliearity ad sice the area of the coarse resistors is small, there is a large variace i the coarse tap voltages ad that causes the INL to be large throughout most of the output voltage taps. Correspodigly, i the same figure, whe z is small, the impedace at the coarse strig plays oly a small role i determiig the overall INL ad sice most of the area is allocated to the fie strig, the INL is very good. I Figure, whe z is large, the impedace at the taps of the coarse strig plays a major role i the oliearity ad sice the area of the coarse resistors is large, there is a small variace i the coarse tap voltages that causes the INL at the tap voltages to be small for most of the coarse voltage taps. But sice there is little area i the fie resistors, the

44 36 variace i the voltage at itermediate odes i the fie strig gets rather large. Correspodigly, whe z is small, the impedace at the taps of the fie strig plays a major role i the oliearity ad sice the area of the fie resistors is small, the variace is large at most of the fie output voltage taps. It is apparet from these plots that uder certai coditios, there is cosiderable ripple i the INL. This ripple occurs whe the relative area i the fie strig is small (z is large). Whe the ripple is preset, the local maxima ad the local miima occur at coarse ladder taps or at mid tap locatios of the fie ladder depedig upo how the resistace ad area is allocated. There are a total of σ ( INL NOM m ) + critical tap poits i the array. Figure 9. INL profiles of the dual ladder DAC for x = 0.0 tap voltage

45 37 σ ( INL NOM m ) tap voltage Figure 0. INL profiles of the dual ladder DAC for x = 0.5 σ ( INL NOM m ) tap voltage Figure. INL profiles of the dual ladder DAC for x = 0.95 It ca also be see that the INL deviatio icreases with x z ad whe x z is small, it reduces whe x ad z move closer to the origi. Simulatio results of the maximum INL stadard deviatios are summarized i the Table.

46 38 z Table. Simulatio results of σ max NOM x=0.0 x =0.5 x= 0.95 σ max-nom (INL m ) EQ σ max-nom (INL m ) EQ σ max-nom (INL m ) EQ Simulatio results show that whe x ad z are small, for example, x = z = 0.0, the ormalized maximum stadard deviatio, σ max NOM,is approximately ad movig closer to the origi o the x = z lie does ot reduce the stadard deviatio appreciably below. Also show i Table is Δ EQ, the effective umber of bits of resolutio lost relative to what would be achieved with a optimal area/impedace allocatio. Whe choosig x = z to attai the miimum stadard deviatio for a fixed x, the effective umber of bits (ENOB) merely reduces by 0.04 bits whe x = z = 0.5 ad reduces by 0.5 bits whe x = z = However, if x is i the eighborhood of ad z i the eighborhood of 0 or vice versa, the the stadard deviatio will be very large. For example, i the case x =0.95, z = 0.0, the ENOB reduces by. bits ad i the case x= 0.0, z = 0.95, the ENOB reduces by 3.3 bits. It should be apparet that the implicatios of a o-optimal area/impedace allocatio ca have a dramatic impact o the yield of a DAC if the deviatio from the optimal x = z lie is large. Figure shows the effects of differet allocatios of impedace ad area throughout the x-z plae from a differet perspective. The cotiuous loci o this plot correspod to isoarea cotours ad are labeled i terms of the icrease i area eeded to obtai a stadard deviatio equal to that obtaied at the optimal poit x = z = 0. This provides some isight ito the area pealty icurred to obtai the same yield if o-optimal area ad impedace

47 39 allocatios are used. For example, the poit x = 0. ad z= 0.7 lies o the 400% area cotour idicatig that a factor of 4 icrease i area is required to obtai the same yield as would be obtaied for a optimal area/impedace allocatio. z 0 0 x Figure. Icreasig Area to achieve the same INL The parameters x ad z, as defied i (7) ad (8) may partially obscure the relative effects of area ad impedace o yield. The effects of o-ideal impedace ad area allocatio is show i the log( F / C ) x plae i Figure 3 where agai the iso-area cotours are used. As a example, to maitai the same yield as i the optimal case, whe the area of the coarse strig is equal of the total area, the total area icreases by 0% if C = 4 F, it 0 icreases by 50% if C =. F, ad it icreases by more tha 400% if C =.3 F.

48 40 log ( / ) - 0 x Figure 3. Effect of selectio of impedace ad area 3.. Simulatio results for differet values of ad A compariso of the maximum stadard deviatio of the INL m for differet bit DAC area ad impedace partitioig strategies for the dual ladder DAC is also made. I this compariso, it will be assumed that the DAC have the same values of the total area ad the total impedace for all. A Matlab program was used for calculatig the stadard deviatio of INL i the limitig case: x = z, ad x -> 0 for differet values of ad. This limitig case forms a tight lower boud o the stadard deviatio of the INL. The poit (0,0) i the x-z plae is ot realizable sice it does ot lie i the ope uit square but values of x ad z ca be selected i the ope uit square that are arbitrarily close to this poit. These results show that the lower boud is strogly depedet upo but idepedet of. The results are summarized i the Table 3.

49 4 Table 3. The optimum σ NOM ( INL m ) of the dual ladder DAC as varies N σ NOM ( INL m ) Additioal simulatio results for differet values of x ad z are icluded i Appedix A ad Appedix B. It is see that the effective umber of bits (ENOB) reduces very slightly whe (x,z) moves away from (x=0, z=0) o the locus x=z as idicated i the Theorem 4. However, ENOB reduces sigificatly for the case z=-x. 3. Iterpretatio of σ INL m for Iterpolatio with buffer I this sectio, the performace of the Iterpolatio DAC with buffer is characterized mathematically by the equatio (44) i the sectio Simulatio results for =0 To iterpret the aalysis preseted i Sectio.3, graphical results of a iterpolatio DAC with = 4, =0 were characterized by equatio (44) to compare the performace for a variety of impedaces ad layout area allocatios. INL profile curves are i Figure 4 whe x is 0., 0.5 ad ad 0.99, respectively. For each value of x, the INL profile looks like a ripple o which the local maxima ad the local miima occur at coarse ladder taps ad i mid taps of the fie ladders. Thus, there are total + critical taps. The maximum variace happes at a sub-tap of the fie strig located i the eighborhood of the middle tap, depedet o the impedace / area allocatios.

50 4 Figure 4. w.r.t the voltage positio tap =0, =4 The variace of INL is deoted by σ INL m i (30) is a fuctio of 5 variables, the ratio of area x, the umber bits o the coarse strig, the umber bits o the fie strig, the tap positio o the coarse strig p, ad the tap positio o the fie strig q. Aalytical expressio for statistical of INL such as the optimum value of σ INL is ot mathematically implemeted. m However, this iformatio is very ecessary for predictig the liear performace of the circuit as wel as kowledge of efficet desigs. Therefore, computig simulatios were used for guessig the criticals values of σ INL. m Figure 5 is the stadard deviatio σ INL usig a Matlab program. It is clearly that the m miimum of the stadard deviatio σ INL obtaied if the ratio x = A m ATOT is aroud 0.95.

51 43 Otherwise, if most of area is used for layout fie resistors, the stadard deviatio icrease more tha times for x smaller tha.5. σ INLm will Figure 5. w.r.t x for =4, = 6 A compariso of the stadard deviatio of the INL for differet values of the umber bits o the coarse ladder is simulated. Figure 6 show that if icreasig the umber bits o the coarse ladder strig, the stadard deviatio σ INLm beefits is the complexity of the coarse strig layout. will decrease. The compesatio of this

52 44 Figure 6. w.r.t. x for = 3, 4, Simulatio results for differet value of ad A compariso of the maximum stadard deviatio of the INL for the covetioal bit DAC area ad impedace partitioig strategies for the dual ladder DAC is also made. I this compariso, it will be assumed that the DAC have the same values of the total area ad the total impedace for all. A Matlab program was used for calculatig the miimum values the stadard deviatio of INL ad the critical ratio x= summarized i the Table 4. A A TOT. The results are

53 45 Table 4. The miimum of Stadard deviatio of INL ad x to obtai the miimum value of the stadard deviatio of the INL σ max NOM 8.9 x σ max NOM x σ max NOM x σ max NOM x σ max NOM x σ max NOM x σ max NOM x σ max NOM x σ max NOM x

54 46 Icreasig the resolutio of the DAC will icrease the stadard deviatio of the INL. I all cases, the wise strategies are placig most of the area o the coarse strig, oly 0% of the total area is used for the fie strig layout. 3.3 Iterpretatio of σ INL m for Iterpolatio with buffer resistors The performace iterpretatio of iterpolatio with buffer resistors of Figure 8 is ivestigated i this sectio by the formula of σ INL m give by equatio (69) i the sectio Simulatio results for =0 To iterpretate the aalysis preseted i.4, graphical results of a iterpolatio DAC with buffer resistors for = 4, =0 were brought out to compare the performace of variety of impedaces ad layout areas allocatio. The variace i the equatio (69) is depedet o the total area, A TOT, ad the process parameter, A ρn. By ormalizig the variace by A ρn /A TOT, the effects of z, ad m o the INL m ca be practically depicted. With this ormalizatio, (69) simplifies toσ max NOM ( z) ( z) z NOM ( INLm ) M + M + M 3 + M 4 a a3 a a σ (7) INL profile curves are i Figure 7 ad Figure 8 for the case z=0. ad z=0.9 respectively. For each case, the INL profile looks like a ripple o which the local maxima ad the local miima occur at coarse ladder taps ad i mid taps of the fie ladders. The maximum stadard deviatio positio is depedet o the impedace / area allocatios.

55 47 Figure 7. The stadard deviatio profile for z=0. From Figure 7, the maximum stadard deviatio of the red curve placig most the area o the coarse strig while a small area o the fie strig ad buffer resistors is bigger 9 times tha the maximum stadard deviatio of the blue curve placig most the area o buffer resistors while a small area o the fie strig ad the coarse strig.

56 48 Figure 8. The stadard deviatio profile for z=0.9 O the other had, i the Figure 8 for the case z= TOT large, the maximum stadard deviatio of the red curve placig most the area o the coarse strig while a small area o the fie strig ad buffer resistors is smaller times tha the maximum stadard deviatio of the blue curve placig most the area o buffer resistors while a small area o the fie strig ad the coarse strig. These two examples raise a questio what is the optimum area ad impedace allocatio betwee the coarse resistors, the fie resistors ad the buffer resistors. The equatio to calculate the stadard deviatio i (69), (7) is a fuctio of 4 variables: the ratio resistor z, the ratio of areas a, a, a 3. If we ca idicate the regio of the optimum, the cost of the DAC desig will lower by reducig the dice area to achieve the same yield. However, it