M2 EEA Systèmes Microélectroniques Polytech montpellier MEA 4. Analog Integrated Circuits Design
|
|
- Poppy Hopkins
- 6 years ago
- Views:
Transcription
1 M EEA Systèmes Microélectroniques Polytech montpellier MEA 4 Analog ntegrated Circuits Design Chapter Basic and Advanced Current Sources Pascal Nouet / nouet@lirmm.fr ecture material download
2 ntroduction Analog ntegrated Circuits are based on elementary stages oltage references Current mirrors Current sources Amplifier stages Main characteristics of a current mirror Current flow to ss (ground) or from Coicient of recopy Quality of recopy High put resistance ange of put voltages (put dynamic) Outline Elementary current mirror Principle Output resistance Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources
3 Current mirroring principle i S in s Biasing (arge Signal Analysis): is saturated è in ds f( gs ) f( ) T must be saturated to deliver a constant current à Output dynamic: ds Small-Signal Analysis à Output resistance S /g m g m.v gs r ds v T s s dsat µ nc ox in v gs v s r ds i s λ dsat Elementary current mirror: put resistance ds (A) mpact of dsat 5,00E- 0 4,50E- 0 4,00E- 0 g ds (µa /) r ds (MΩ) λ( ) dsat (µa) y 0,0044x in S T s 3,50E- 0 3,00E- 0,50E- 0,00E- 0,50E- 0,00E- 0 gds (µa/) inéaire (gds (µa/)) 5,00E- 0 0,00E+00 ds (µa) 0,00E+00,00E+0 4,00E+0 6,00E+0 8,00E+0,00E+0 ds () 3
4 Elementary current mirror: put resistance ds (A) mpact of transistor length,40e+0,0e+0 rds (Mohms) y 0,093x +,78 in S T s,00e+0 8,00E+00 6,00E+00 4,00E+00,00E+00 0,00E+00 r ds e ( / µm) (µm) + r 0 dsat (A) (µm) 0,00E+00,00E+0 4,00E+0 6,00E+0 8,00E+0,00E+0 ds () Elementary current mirror: put resistance ds (A) mpact of transistor size (/) 4,5 in S 4,0 rds (Mohms) T s 3,5 3,0,5,0,5,0 0,5 0, / ds () 4
5 Elementary current mirror: summary mpact of dsat Output resistance is divided by two when current is multiplied by two mpact of transistor size Output resistance doubled when transistor length is multiplied by two (constant /) in T S s Useful equations orking with constant and transistor length General case à r ds α i s v s r ds ds ds λ( ) dsat (A) r ds e( / µm) (µm) + r 0 dsat (A) Outline Elementary current mirror Elementary stages for increased put resistance Degenerated source current mirror Cascode current mirror Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources 5
6 Degenerated source current mirror i S in S /g m v g g m.v gs r ds T v s v s s s s s arge-signal Analysis T always saturated Output dynamic à saturation of T Small-Signal Analysis Output resistance v i S s dsat µ C n ox > + s S S in rds + in ( g ) m s Degenerated source current mirror mpact of s 5,0 r (MOhms) 0,0 5,0 y 0,994x + 3,467 50µA T S 0,0 s s 5,0 0,0 r r ds + + g m r ds ( ) s g m r ds λ n λ n s(kω) 5 6
7 Outline Elementary current mirror Elementary stages for increased put resistance Degenerated source current mirror Cascode current mirror Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources Cascode current mirror i S in S S /g m3 g m4.v gs4 r ds4 T 3 T 4 vs v g4 v s4 v g T /g m g m.v gs r ds v s d d d3 d 4 in arge-signal Analysis T and T 3 are saturated, T also Output dynamic à saturation of T 4 Small-Signal Analysis Output resistance s dsat µ n C ox S v i S S > + tn g in r r m4 ds ds4 7
8 Cascode current mirror ds (A) mpact of / r (MOhms) / µA S T 3 T 4 T ds () Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources 8
9 ilson current mirror i x in S /g m3 v gs4 g m4.v gs4 r ds4 T 3 T 4 vx T g m.v gs r ds v gs /g m d d d 3 d 4 Similar performance to cascode mirror s dsat µ n C ox Substrate ect: in v in S > tn + S i s vs ( gm4 + gs4 ) rds rds4 i s g m4 r ds r ds4 PMOS Current Mirrors Every NMOS current mirror has a PMOS dual Caracteristics are identical and easy to transpose: smin à smax, r T S S T T T S T T 3 T 4 T 3 T 4 in S S S r r ds in in in r g m r ds r ds 9
10 Non-symetrical mirrors Different ratio / may be used in the put branch (generally X> à put current higher than reference current) Same for all transistors means current proportionnal to /: in S in S in S T 3 T 4 s T 3 T 4 s T s T T : X : X : X Multiple puts current mirrors r S S One reference branch may be connected to as many put branches as recessary for the application Each put may deliver a different ratio of current Each put may have a different put resistance in > λ S X ; n in S nx S S ; r > n λ n in X. in S S n S nx nx S n n in S S n n r r S S S S in X >. + >. λ λ n n tn + tn in X. in 0
11 Overview of put resistance of elementary current mirors,00e+0 (Ω),00E+09,00E+08 Miroir simple SD SD Cascode ilson,00e+07,00e+06,00e+05,00e+04,00e+03 0,00 0,50,00,50,00,50 3,00 S 3,50 ( ) Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources esistance ing Transistor ing mpact of and T C Overview of advanced current sources PMOS current sources
12 From current mirrors towards current sources Analog ntegrated Circuits are based on elementary stages oltage references Current mirrors Current sources Amplifier stages f() Current flowing through ground or from in S T T s deal versus actual current sources S ö OUT 0 Smin ø Output esistance and dynamics S Sensitivity to and T C s0 Power consumption S min
13 esistance ing NMOS current sources > T T 3 T 4 > tn + T 3 T 4 > tn + : X T : X T : X Sizing Output dynamics à Output current ( ) à / of T (T 4 ) X à eference current ( in ) à / of (T 3 ), Output resistance calculation (e.g. ilson Current Source ) i x /g m3 v gs4 g m4.v gs4 r ds4 T 3 T 4 > tn + g m.v gs r ds v gs /g m v x T ( ) r i ds p g mv gs p + rds + gm3 gmrds p vg4 p. i( p) p + rds + gm3 vgs4 : X i ( + A) v ( + A) x ( + g ) gs gm vgs Avgs m ix p gm ix vx + rds4 gm ( vx & + rds4 + ' gm r + gm ( i g v ) x m4 gs4 ( + A) gm4 % rds4 # ix g m $ ( + A) rds ( + gm p ) rds 3
14 Transistor ing NMOS Current Sources T p T p T p > T T 3 T 4 > tn + T 3 T 4 > tn + T T : X : X : X Output dynamics à Output current ( ) à / of T (T 4 ) X à eference current ( in ) à / of (T 3 ), T p Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources esistance ing Transistor ing mpact of and T C Overview of advanced current sources PMOS current sources 4
15 mpact of S ö OUT 0 ø OUT min fixe esistance ing v (> ) i T /g m v g m.v r ds p µ ncox + ( T tn T ) i Δ Δ g m i. v g g m m ( + g ) v + g g m m m ( + gm p ) p p Δ v 5
16 Transistor ing v T 3 (> ) /g m3 i T /g m v g m.v r ds µ nc µ pc + ox ox ( T tn 3 3 T ) ( ) tp i g g m m Δ Δ g g + g m3 m3 i. v g m m + 3 g g m3 m v + g Δ 3 m3 v mpact of on Current Sources (A) Δ Δ, T T 3 Δ Δ,77 T () 6
17 mpact of on Current Sources (A) Δ Δ, T Δ Δ,55 T 4 T 3 T () esistance ing and temperature An increase in temperature reduces the saturation current of a transistor,06e+0 (µa),04e+0,0e+0 Polarisation par résistance (> ) T,00E+0 9,80E+0 9,60E+0-0,08 %/ C 9,40E+0 9,0E+0 Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 7
18 esistance ing and temperature esistance may also change with temperature ( TCT. ),5E+0 (µa) p p0 + ésistance fixe,0e+0 TCe- 3 / C,05E+0 (> ) T,00E+0 9,50E+0 9,00E+0 8,50E+0-0,08 %/ C -0,08%/ C -0,57 %/ C 8,00E+0 Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 Transistor ing and temperature,0e+0 NMOS et PMOS exhibits same phenomenon (µa),5e+0-0, %/ C Polarisation par constante Polarisation par avec TCe- 3 / C Polarisation par PMOS T 3 (> ) T,0E+0,05E+0,00E+0 9,50E+0 9,00E+0-0,08 %/ C 8,50E+0-0,57 %/ C 8,00E+0 Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 8
19 Cascode Source and temperature Feedback may improve results,5e+0 (µa),0e+0,05e+0 Cascode avec et TCe- 3 / C Polarisation par avec TCe- 3 / C Cascode pplarisé par PMOS 0,036 %/ C T 4 T 3 T,00E+0 9,50E+0 9,00E+0 8,50E+0-0,036 %/ C -0,57 %/ C Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 T 3 T 4 T 3 T Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources -independent current sources -independent and increased put resistance ncreasing put dynamic range PMOS current sources 9
20 -independent current sources Principle: a resistor implement a feedback that tends to reduce current variations Sizing methods Choice of and α (generally, 4, 9 or 6) is not sensitive to variations Assuming identical currents in and T leads to an expression of depending of T 4, T 5 et T 4 T α µ pcox 4 & α # $! % α + α " B T A T 3 -independent current sources Other configurations Dual circuit in PMOS (current from ) T 4 ncreased stability by reduction of ds and ds5 Power consumption à asymmetrical current mirror T 3 T α 4 4 T 4 B T 5 D T α T 3 T 6 C T A 0. T 7 0
21 - independent and increased put resistance -independent à, T 4 and T 5 to set value of independently of educed power consumption à asymmetrical current mirror High-voltage operation à T 3 and T 6 are optional T 4 B T T 5 D T 3 T 6 C A 0. T 7 ncreased à Cascode put à Problem à put range of operation T c c T 7c Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources -independent current sources -independent and increased put resistance ncreasing put dynamic range PMOS current sources
22 ncreasing put dynamic range Principle S T 3 s T ds gs3 ds d3 gs gs ds s3. tn tn s3 + tn Trade-off between put range of operation and put resistance ncreasing put dynamic range mplementation: large-swing cascode current source with -independent reference current T 6 T 7 T α ( α > ) + avec B 6 α 7 A T 9 T 5 T 3 T C
23 ncreasing put dynamic range: alternative configurations 5 T 6 T 7 T 8 T 6 T 7 T 8 B A C T 4 T 6 T 7 B T 8 T 9 T 5 A 0. C T 4 T 3 T T 9 T 5 T 3 T Current sources Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources 3
24 Current sources Overview of main characteristics mpact of Output resistance Output range of operation Basic current source ±5% 65kΩ > 0,8 -independent current source ±,3% 500kΩ > 0,9 -independent current source with cascoded put ±0,0% 80MΩ > arge-swing - independent cascoded current source ±9% ±,5% 3,54MΩ 4,88MΩ > 0,3 > 0,3 Contrôle des connaissances 4 Novembre : 3 heures Analyse de ay Source de tension Dimensionnement théorique Ajustement fin Schéma petit-signal Sensibilité à Source de courant Dimensionnement théorique Ajustement fin Schéma petit-signal ésistance de sortie 4
Polytech Montpellier MEA4 M2 EEA Systèmes Microélectroniques. Analog IC Design
Analo C Desin - Academic year 05/06 - Session 3 04/0/5 Polytech Montellier MEA4 M EEA Systèmes Microélectroniques Analo C Desin From transistor in to current sources Pascal Nouet 05/06 - nouet@lirmm.fr
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationECE315 / ECE515 Lecture 11 Date:
ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)
More informationCMOS Analog Circuits
CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100
More informationLecture 18. Common Source Stage
ecture 8 OUTINE Basic MOSFET amplifier MOSFET biasing MOSFET current sources Common source amplifier eading: Chap. 7. 7.7. EE05 Spring 008 ecture 8, Slide Prof. Wu, UC Berkeley Common Source Stage λ =
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationElectronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers
6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION
ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution
ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :
More informationNMOS (N-Channel Metal Oxide Semiconductor) Transistor. NMOS Transistor in Equilibrium
NMOS (N-Cannel Metal Oxide Semiconductor) Transistor e e e oxide insulator e e e NMOS Transistor in Equilibrium oxide insulator Wen te transistor is left alone, some electrons from te wells diffuse into
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationChapter 20. Current Mirrors. Basics. Cascoding. Biasing Circuits. Baker Ch. 20 Current Mirrors. Introduction to VLSI
Chapter 20 Current Mirrors Basics Long Channel Matching Biasing Short Channel Temperature Subthreshold Cascoding Simple Low Voltage, Wide Swing Wide Swing, Short Channel Regulated Drain Biasing Circuits
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMicroelectronic Circuit Design 4th Edition Errata - Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 0-4546 CLASS TEST 08-9 ELECTCAL ENGNEENG Subject
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last
More informationV in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant
More informationCircuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationLecture 28 Field-Effect Transistors
Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationEE40 Lec 20. MOS Circuits
EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences PROBLEM SET #3 (SOLUTION)
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences R. W. Brodersen EECS 140 Fall 2004 PROBLEM SET #3 (SOLUTION) 3) In the above circuit, use V DD
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More informationBJT Biasing Cont. & Small Signal Model
BJT Biasing Cont. & Small Signal Model Conservative Bias Design (1/3, 1/3, 1/3 Rule) Bias Design Example Small-Signal BJT Models Small-Signal Analysis 1 Emitter Feedback Bias Design R B R C V CC R 1 R
More informationBipolar junction transistors
Bipolar junction transistors Find parameters of te BJT in CE configuration at BQ 40 µa and CBQ V. nput caracteristic B / µa 40 0 00 80 60 40 0 0 0, 0,5 0,3 0,35 0,4 BE / V Output caracteristics C / ma
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,
More informationMICROELECTRONIC CIRCUIT DESIGN Second Edition
MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationLecture 310 Open-Loop Comparators (3/28/10) Page 310-1
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop
More informationRandom Offset in CMOS IC Design
Random Offset in CMOS C esign ECEN487/587 Analog C esign October 19, 007 Art Zirger, National Semiconductor art.zirger@nsc.com 303-845-404 Where to start? How do we choose what transistor sizes to use
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationLecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationAmplifiers, Source followers & Cascodes
Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter
Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation
More informationElectronics II. Midterm #2
The University of Toledo EECS:3400 Electronics I Section sums_elct7.fm - StudentName Electronics II Midterm # Problems Points. 8. 3. 7 Total 0 Was the exam fair? yes no The University of Toledo sums_elct7.fm
More informationLecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationMetal-Oxide-Semiconductor Field Effect Transistor (MOSFET)
Metal-Oxide-Semiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n- substrate - SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate
More informationV = = A = ln V
Chapter Problem Solutions. a. b. c. γ + γ + BE + C + + γ + ( γ ( γ C γ + BE + BE γ BE and C γ ( γ + or C BE + C ma.5 kω.7 ( ma + 4. kω.5 kω C. (a ln C BE T S (i μ 6 A,.6 ln.588 μa C BE 4 (ii μ 6 A,.6 ln.5987
More informationRIB. ELECTRICAL ENGINEERING Analog Electronics. 8 Electrical Engineering RIB-R T7. Detailed Explanations. Rank Improvement Batch ANSWERS.
8 Electrical Engineering RIB-R T7 Session 08-9 S.No. : 9078_LS RIB Rank Improvement Batch ELECTRICL ENGINEERING nalog Electronics NSWERS. (d) 7. (a) 3. (c) 9. (a) 5. (d). (d) 8. (c) 4. (c) 0. (c) 6. (b)
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationECE 342 Electronic Circuits. Lecture 25 Frequency Response of CG, CB,SF and EF
ECE 342 Electronic Circuits ecture 25 Frequency esponse of CG, CB,SF and EF Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 342 Jose Schutt Aine 1 Common
More informationStudio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )
Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) 1 Simulation Review: Circuit Fixed V GS, Sweep V DS I
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationP-MOS Device and CMOS Inverters
Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short
More informationUsing MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B
Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationLecture 7: Transistors and Amplifiers
Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many
More informationDigital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman
Digital Microelectronic ircuits (361-1-3021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More information