Random Offset in CMOS IC Design

Transcription

1 Random Offset in CMOS C esign ECEN487/587 Analog C esign October 19, 007 Art Zirger, National Semiconductor art.zirger@nsc.com

2 Where to start? How do we choose what transistor sizes to use in a design? One topic not often discussed in classes is random offset and how transistor sizing affects this phenomenon.

3 ntroduction devices (MOSFE s, resistors, capacitors) of the same size, laid out next to each other, are not identical. How they differ is generally the function of random offsets during processing. hese offsets vary from chip to chip and set a limit on precision attainable which is typically reflected as data sheet specifications.

4 Misc. efinitions/notation he following -V equation for a MOSFE in saturation is used: ( ) W VGS Vt where β µc ox β L A mixture of V t & V is used where both are referring to threshold voltage, not thermal voltage

5 Agenda Systematic vs. random offset Sources & profiles of random offset Current Mirror/iff Pair offset derivation & insights Propagation of uncertainties math Current Mirror/iff Pair exercises

6 Systematic vs. random mismatch Systematic Mismatch in the circuit (or layout) because of poor designer choices (i.e. avoidable) Each copy of the circuit should share this; calculable based on the average values of element parameters Viewable using SPCE C operating point simulation Random Mismatch in the circuit because of wafer processing ifferent chips will have different values, but the value will mostly remain the same (subject to temperature shifts, drift, etc.) Each copy of the circuit should share this; calculable based on the statistical values of element parameters Viewable using Cmatch and Monte Carlo simulations his is what is usually thought of as matching

7 Sources of random mismatch Sources of random mismatch include: Edge effects (rough edges) mplantation (finite number of charges & distribution) Mobility Oxide effects See References (after Summary slide) for more information.

8 Mismatch parameters Commonly investigated mismatch parameters: MOSFE V t, β (mobility and W/L), γ (Body Effect) Resistors ρ (resistivity) Capacitors oxide thickness variation his presentation covers V t & β mismatch

9 Profile of random mismatch Has a gaussian distribution Can be quantified by statistical variables of: mean: ā standard deviation: a variance: a Mismatch is defined as occurring between elements; a single element does not have mismatch, but a self mismatch can be defined.

10 hreshold Voltage Mismatch he threshold voltages among a group of transistors has a gaussian profile about a mean. Experimentally, it has been shown that the difference in threshold voltages between identically sized transistors behaves as: V t AV t WL Note that to reduce the mismatch by ½ takes 4 times the area A fab will create test structures and measure V t multiple times per wafer for various sizes of transistors and collect ongoing statistics to monitor the process over time.

11 hreshold Voltage Mismatch, cont d NFE Our CMOS A V From W. Sansen showing how the mismatch constant, A V, varies roughly linearly with process size (doping concentration affects linearity of the relationship). Also, for p substrates, the PMOS will have A V ~ 1.5*A V NMOS.

12 Current Factor Mismatch Current Factor, β, behaves fractionally, as: ( β ) β A β WL A β ~ %µm, invariant of process National Semiconductor does not have this value characterized, so we may use this approximate value to estimate whether we need to worry about this or not.

13 Offset erivation Given the behavior of sufficiently uncorrelated parameters, want to know the effect of those parameters on common circuits: Current mirror ifferential pair Start with -V equation for MOSFE and apply total differential : f f x x + f y y + f z z +...

14 Offset erivation Current Mirror What is the fractional error in the currents being mirrored in a 1:1 current mirror? β ( V ) gs V g gs β,v, V m β or Vgs V β ( V V ) V ( V V ) + V ( V V ) 1 β β gs gs gs gs variables V gs 0 in a current mirror. ivide by to get fractional error: 1 β β ( V V ) ( V V ) gs gs β V β gs ( V V ) gs ( V V ) β V β β β ( V V ) g m gs V

15 Offset erivation iff Pair What is V GS for transistors operating at the same current? β ( V ) gs V g gs β,v, V m β or Vgs V β ( V V ) V ( V V ) + V ( V V ) 1 β β gs gs gs Constant current so 0 ivide by β β ( V ) ( V ) gs V Vgs 0 1 β β ( V V ) gs ( V V ) gs gs V V + V gs gs V gs β β β g m + V + V

16 Offset erivation Summary/nsights ifferential Pairs and Current Mirrors operate with very different g m / d (i.e. bias point) ratios to minimize mismatch errors: ifferential Pair: High g m / d Current Mirror: Low g m / d V gs β β g low overdrive β g β high overdrive You can achieve this by designing differential pairs with large W/L and current mirrors with small W/L ratios m m + V V

17 Offset erivation w/standard eviations Given the expected functional relationships of the different offset behaviors, for various statistical reasons, you express these relationships in terms of standard deviations as: Current Mirror ifferential Pair m V g β β m gs V g V + β β ( ) ( ) ( ) ( ) m gs V g V + β β ( ) ( ) ( ) + m V g β β

18 Statistics Math You need to know how to propagate uncertainties to get the most out of this material. General form to propagate uncertainties for uncorrelated variables: z f(x,y,z ) ( n # of variables ) n i v i z i v f y x z y f x f

19 Statistics Math, cont d More commonly seen as this: Sum: + z x y r.s.s, (square) root sum of squares Product/Quotient: f(x,y) x*y or x/y f f x x y + y Fractional error of f is the r.s.s of the fractional errors of the individual variables.

20 Statistics Math, cont d o utilize these error propagation formulas, you need to know the individual contributions (e.g. x, y ) which means you need the self-mismatch of the variables in question. his is found by noting that, if: V t V V t1 t and we apply the sum formula, we get: V V t + t V 1 t Vt WL With a self-mismatch defined, we can now calculate the standard deviation of all sorts of mathematical operations of statistical parameters. We can calculate the accuracy of a 50x current mirror, for example, by utilizing the quotient version to propagate the uncertainty of the mirror gain. AV t or V t1, AV t WL

21 Statistics Math - Summary o propagate a sum: z x + y product: z x*y quotient: z x/y y x z + ( ) + y x xy y x z ( ) ( ) y x z x y + + y x y y x z + y x y x y x z

22 Current Mirror Matching Example 1x 1x 1x 50x Ratios: 1:1:1:50 Problem: esign 1:1 to required accuracy (1%), for d 1µA Procedure: Calculate self-mismatch and utilize statistics.

23 Current Mirror Matching, cont d PMOS: µ p C ox 3µA/µm, d 1µA ( ) ( β ) β ( V ) f β mismatch not modeled, ( ) esign 1:1 mirrors for 1%: gm β µ p ox W Vt&, d ( ) d d ( ) self d g + C d µ pcox d W L m L d self. 110 d L L 15.6 L A V t WL AV t L 1 d d self ( ) AV t WL µ pcox d g 1% ( V ) Note: no dependence on W, only L!! Use W/Lu/16u m.01 3mV L 3µ A 1µ A

24 Current Mirror Circuit 1x 1x 1x 50x 1:1:1 all have W u 50x has W u*50 100u

25 Current Mirror Followup id neglecting β mismatch matter? What is the matching for the 50x mirror? See Appendix B

26 iff Pair Example Use analysis to estimate input offset voltage to diff pair. 3 steps: 1.Calculate V gs of input pair.calculate Ι d / d of current mirror and reflect to input using g m of input pair 3.Combine independent sources using sum propagation

27 iff Pair Circuit, Quiescent Conditions Need to know things like g m, d for total offset calculations

28 iff Pair Circuit, Step 1 1. Calculate V gs of input pair ( ) ( β ) V + ( ( V )) gs W/L 0u/.5u, A Vt 16mVµm A t V 16mVµ m V 5. 06mV t WL 0µ m*0.5µ m g m_m0/m1 55.8µA/V, d.5µa, Α β ~ %µm ( β ) β otal β g m.0µ m.5µ A *. 8mV g m m A m 0µ *0.5µ 55.8 µ V ( V gs ) (.8mV ) + ( 5.06mV ) 5. 07mV

29 iff Pair Circuit, Step 1. Calculate d / d of mirror pair Reflect current error to input offset through g mn ( ) ( ) ( ) 05. * * m m m mv A V A m m m V g m µ µ µ µ µ µ µ µ β β ( ) mv V A A g mn Vgs /.05*.5 / * µ µ

30 iff Pair, Step 3 (r.s.s) Last step is to combine these independent sources of error into the total: ( 5.07mV ) + ( 1.1mV ) 5. mv Vgs _ total 19 input pair current mirror Given a choice to add area to current mirrors or input pair, in this example, more to be gained by using the area for the input pair.

31 Summary Points Current mirror accuracy is improved with low W/L ratios f β mismatch is not a factor, current mirror accuracy is determined by selection of L only. ifferential pair accuracy is improved with high W/L ratios Based on surveys of published fabrication data, you can estimate mismatch coefficients for your own process rather easily Uncorrelated statistics provide the basis to propagate individual mismatch information to arbitrary destinations Random mismatch 1can be improved with more area but it s mismatch costly: WL CA tool analyses such as Cmatch and Monte Carlo are a useful tools for getting insight into sources of mismatch (expected and unexpected)

32 Layout: References he Art of Analog Layout, Alan Hastings General nformation: Analog esign Essentials, W. C. Sansen Early classic paper and commentary: Matching properties of MOS transistors, Marcel J. M. Pelgrom, JSSC, Oct sc1.html Recent papers with references: evice mismatch and tradeoffs in the design of analog circuits, Peter Kinget, JSSC, June 005 (in depth, with many references) evice Mismatch: An Analog esign Perspective, Peter Kinget, SCAS 007, (condensed information) Cadence application note on Cmatch: Affirma Spectre C evice Matching Analysis utorial

33 Appendix A CA tools Cadence and other vendors have analyses to assist in propagating mismatch sensitivities to designated voltage nodes or current branches analyses which we use are: CMatch Monte Carlo

34 ools for Checking Matching Local mismatch: CMatch (Spectre analysis) Uses small signal analysis to reflect the combination of modeled mismatches to an arbitrary output node By local, we mean the signal deviations introduced must not alter the dc operating point for the results to be accurate (i.e. small signal assumption) Fast to run

35 ools for Checking Matching Global mismatch: Monte Carlo Alters parameters of individual elements, drawing variation from a statistical distribution. Pro: Unlike CMatch, doesn t rely on linear approximation, so does a (slightly) better estimate of matching, because real components are nonlinear. Con: You need to run 100 s of simulations to develop good statistics which means this takes 100 s of times longer than CMatch (which is 1 C simulation); reported mean should be close to C simulation if enough points are chosen.

36 Procedure for Checking Matching 1. Use hand calculations to estimate required transistor sizes to meet matching. Utilize CMatch to verify hand calculations. n more complicated circuits, a sensitivity from an unexpected transistor can show up 3. Later, utilize Monte Carlo to double check

37 Current Mirror Circuit 1x 1x 1x 50x 1:1:1 all have W u 50x has W u*50 100u

38 Current Matching: CMatch Select dcmatch analysis. he Output is a probe (i.e. current), the voltage source, V_1x_M1. Only sensitivities found are from M1 and M0. Note that sigmabeta 0, since it s not modeled. he sigmads value of % gets added in r.s.s fashion to achieve an overall fractional error of 8.63n/1.007u.84% %*sqrt(). his is a 3- value, so 1- ~.95% < 1%

39 Current Matching: Monte Carlo Salient Features: Matching Gain for M1:M0 and M:M0 have 1%, but about.7% mean error. M:M1 mean error is about.05%. Why (1)? M3:M0 (50x) gain error can be calculated using the quotient formula of the Statistics Math: f f x x y + y (.001) + (.00707) % More detail in Appendix B.7%, why not 1% ()?

40 Current Matching: Monte Carlo, cont d Answers: (1): Any error in the mean is not statistical; the source of the difference in the means is coming from the design and it turns out to be channel length modulation since the input to the mirror s drain is near Vdd and the output to the mirrors drains are near Ground. (): Even though the 50x mirror transistors all share the same length, they don t share the same self-mismatch fractional error. f you look ( at. 001) the + ( r.s.s ) portion ( ), you can see how the largest error dominates the sum. he fractional error of the 50x is actually quite low, so the combination approaches the self-mismatch fractional error of the input transistor or 1%/sqrt().71%. Remember that for any fractional error combinations How to remove the error in the means? (see next slide)

41 on t forget your friend the cascode!

42 on t forget your friend the cascode!

43 iff Pair: Cmatch Similar to Current Mirror except Output is now a voltage and the nodes are the inputs to the diff pair so it reports offset. ( ) ( ) ( ) V mvtwl mvtwl e e + + mvt0 + th WL WL 0µ m*0.5µ m 0µ m* ( 0.5 µ m).6e ( V th ) self 9.9e 3 ( V ) 4 e 3 th self Offset error of 68.3uV (mean or systematic) and 17.73/3 5.9mV 1- random offset. he Cmatch individual parameters are harder to match up to hand calculations. sigmavth for M1 (a differential input transistor) might be expected to be (from Cmatch documentation): + ( 6.14e 9) 0.9e 6 Which doesn t match up well to the 1.3mV reported in the listing. But, we haven t considered W and L to modify the width/length of the transistor. his transistor is a minimum length transistor, so it turns out that has quite an effect. After using Leff L Lint, and recomputing we find: 3 ( V th ) self 1.3e 3 You can also see the gain reflection to the input for M3/M4.!!

44 iff Pair: Monte Carlo Should have similarly modeled effects as CMatch. Also allows for nonlinear -V behavior to be accounted for. Matches better to hand calculations than Cmatch, but not necessary. deally, this is more accurate.

45 Appendix B β mismatch check Quick check on the assumption that β mismatch is not an issue. Fractional β mismatch ~ %/sqrt(*16).35% Might estimate overall error to be really: (.35%) + (.95%) 1.01% idn t really have to oversize the length much (15.6u 16u) to still get very close to meeting the goal of 1% mismatch in the presence of estimated β mismatch. Conclusion is that typically, β mismatch is not really an issue.

46 50x current mirror gain calculation Calculating accuracy of 50x current mirror gain: ( ) ( ) f f x x + y y d _ self _ 50x d _ 50x d _ self _1x Since 50x current transistor utilizes 50x W, use relationships for g m, V t, d to W: W _ 50 L gm µ Cox d gm 50x gm _ 1x ( ) _ self _50x _50x g m _50x _50x ( V ) t _ self _50x + d _1x AV t Vt _1 V t Vt _50x WL 50 50gm _1x V t _ self _1x x d _ 50 x 50 d _ 1x d _1x ( ) _ self _1x _1x f f % 1% + (.001) + (.00714)