The Mismatch Behavior P(x,y)
|
|
- Percival Glenn
- 5 years ago
- Views:
Transcription
1
2
3 The Mismatch Behavior P(x,y) x y σ 2 ( P) = f A ( WL, ) + f D ( D) f A ( W, L) Small random, transistor size dependent component, true mismatch component f D ( D) Gradient surface, transistor distance dependent component, can be eliminated with layout techniques Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
4 Historical Perspective. Mismatch Models in Strong Inversion σ ( P) = fwl (, ) + S P D 2 σ ( β/β) 2 σ ( VT0 ) 2 σ ( θo ) 2 σ ( θ) 2 σ ( θe ) Pelgrom89 Bastos98 Serrano99 2 σ ( γ) V DS sat θ = θ o θ V GS V e T µc ox l d R µ 1 θ o = θ θ L e = C L 2v ox l d R s Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
5 A Continuous Transistor Model from Weak to Strong Inversion. The ACM Model I DS = I s ( i f ( V P V S ) i r ( V P V D )) V P V SD ( ) = φ t ( 1 + i fr ( ) 2 + ln( 1 + i fr ( ) 1) ) n = 1 V G V TO V P = n γ V G V TO + 2φ F + γ 2φ F + 1 4γ 2 1 2γ 2 I S = I S 'n = µnc' ox ( W L) φ t 2 Continuous for all transistor operation regions Based on a reduced set of physically meaningful parameters { I S, V TO, γ, φ F } Drain/Source symmetric Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
6 Introducing Continuosly Second Order Effects traditionally, I S ( i f i r )( 1 + λ( V D V S )) I DS = θ o [ V P V S ] θe V DSeff, V DSeff = V DS in ohmic region; V DSeff = V P V S 0.5 [ x ] + [x]+ E E in saturation. define smoothed rectification [ ] + 0 if x < E [ x] + = ( x + E) if E < x < E 4E x if x > E redefine V DSeff = [ V P V S ] + [ V P V D ] E 0 E x E 0 E 0.5 x with E = 0,3V DS Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
7 A Continuous Mismatch Model Valid from Weak to Strong Inversion I S ( i f i r )( 1 + λ( V D V S )) I DS = θ o [ V P V S ] θe V DSeff I DS I DS = I S I S + 1 I DS V P 1 I DS V P V I DS V P V T T0 I DS V P n 1 n γ n γ 1 I DS 1 I DS θ I DS θ o θ o I DS θ e e I S , V I T0, γ, θ o, θ e S Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
8
9 Mismatch Characterization Chip DN DP S G Bus G S DN DP W /L 1 1 DECODER W 1 /L 2. Bus Enable W 6 /L 5 row select column select Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
10 Measuring Curves: 7 Measured Curves V DS = 1,65V Curve 1: I DS ( V GS ), V SB = 0V, V GS [ 03,3, ] Curve 2: I DS ( V GS ), V SB = 1V, V GS [ 03,3, ] V DS = 0,1V Curve 3: I DS ( V GS ), V SB = 0V, V GS [ 03,3, ] Curve 4: I DS ( V GS ), V SB = 1V, V GS [ 0, 3,3] V G = 1,25V S + α Curve 5: I DS ( V S ),α = α 1, V S [ 0, 3,3] Curve 6: I DS ( V S ), α = α 2,V S [ 03,3, ] Curve 7: I DS ( V S ), α = α 3, V S [ 0, 3,3] where: α 1, α 2 and α 3 are values of V G from curve 1 so that we are in weak, moderate and strong inversion respectively. V g V SB log( I ds ) I ds I ds V DS curves 1, 2, 3, 4 V g curves 5, 6, 7 V s Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
11
12 Computing Statistics x σ I S I S x x x x ( ) σ γ ( ) σ V ( T0 ) x x x x ( ) σ θ o σ θ e ( ) x Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
13 Computing Statistics σ I ( S I S ) 1 ( WL ) 1 ( WL) σ γ ( ) σ V ( T0 ) 1 ( WL) σ θ ( e ) 1 ( WL) σ( θ o ) 1 ( WL) Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
14 Predicting σ I Iof measured curves and errors ( ) ( σ I/I ( ) meas σ I/I ( ) pred ) σ( I/I) meas σ 2 I DS I DS = 2 1 I DS I DS I DS I DS 2 2 σ IS σ I DS VTO VT σ I DS γ γ σ I DS θo θo σ I DS θe θe +correlation 15 σ( I/I) σ( I/I) (σ meas σ ft )/σ meas (σ meas σ ft )/σ meas I mean 10 5 I mean V G V G σ( I/I) σ( I/I) (σ meas σ ft )/σ meas (σ meas σ ft )/σ meas σ( I/I) I mean 10 5 I mean σ( I/I) I 10 1 mean I mean (σ meas σ ft )/σ meas V G V G (σ meas σ ft )/σ meas V G V G Curve 1. V DS = 1,65V V S = 0V Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
15 Correlations θ o θ e γ V T0 I S I S 1 L 1 L 1 L 1 L V T0 1 L 1 L 1 L γ 40µm 20µm 1 L 1 L 10µm 5µm 2µm θ e 0,8µm 1 L Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
16
17 Nominal Measured Curves Mismatch Measurements W = 0.12μm L = 0.1μm W = 12μm L = 10μm CMOS Transistors 90nm process 25 different sizes 64 devices each size Measured Curves with Mismatch Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN terese@imse-cnm.csic.es
18 Mismatch Measurements Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN
19 Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN Extracted Mismatch Parameters Standard NMOS transistors 90nm process
20 Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN Measured vs. Predicted Current Mismatch Standard NMOS transistors 90nm process measured predicted
21 Error in Current Mismatch Prediction Standard NMOS transistors 90nm process Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN
22
23 Spectre Mismatch Model Implementation T - 26 Our intention is to create a model of a MOS transistor that fits with the results of the model. This model has been implemented in AHDL (Analog Hardware Description Language) and can be used in Simulator Spectre The model implementation is based on a current in parallel with a spectre library transistor that emulates the mismatch behavour. I DS I DS Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
24 T - 27 Spectre Mismatch Model Implementation I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
25 T - 28 Spectre Mismatch Model Implementation I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameter box stores the 5 large signal parameters and the standard deviations and correlations of the 5 mismatch parameters Parameters I S θ o Large signal parameters ACM Model Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
26 T - 29 Spectre Mismatch Model Implementation -parameters Generator box obtains the five mismatch parameters using 5 uncorrelated random numbers and data stored on Parameters box I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
27 T - 30 Spectre Mismatch Model Implementation I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters ACM Model box is used to obtain the large signal current using the 5 large signal Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
28 T - 31 Spectre Mismatch Model Implementation I DS I DS I DS Generator box obtains the current in parallel using the 5 large signal parameters calculated in the ACM Model box and the 5 mismatch parameters obtained in the -parameters Generator box Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
29 T - 33 I DS σ I DS Spectre Mismatch Model Implementation 10 1 I DS σ I DS 10 0 I DS σ I DS V GS I DS σ I DS V GS V GS V GS I DS σ I DS I DS σ I DS V GS 10 0 simulated fitted V GS Comparisson between simulated and fitted data for curve 1 and all transistor sizes Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es
30
31 Pelgrom JSSC-89 σ 2 ( P) = A P S WL PD size dependent term distance independent (lot of literature) distance dependent term size independent (little literature)
32 σ 2 ( P) = A P S WL PD By analyzing the mathematical derivation P(x,y) x y
33 Gradient Component (x 2,y 2 ) random planes from die to die (x 1,y 1 ) P( x, y) = Ax + By + C random numbers die average
34 Generate random numbers A and B P( x, y) = Ax + By + C
35 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j )
36 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j ) Statistics over many planes σ 2 ( P grad _ ij ) = σ 2 ( A)x ( i - x j ) 2 + σ 2 ( B) ( y i - y j ) 2
37 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j ) Statistics over many planes σ 2 ( P grad_ij ) = σ 2 ( A)x ( i - x j ) 2 + σ 2 ( B) ( y i - y j ) 2 no preferred directions: σ( A) = σ( B) σ 2 ( P grad_ij ) = σ 2 ( A) [( x i - x j ) 2 + ( y i - y j ) 2 ] = σ 2 ( A)D ij 2
38 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j ) Statistics over many planes σ 2 ( P grad_ij ) = σ 2 ( A)x ( i - x j ) 2 + σ 2 ( B) ( y i - y j ) 2 no preferred directions: σ( A) = σ( B) σ 2 ( P grad_ij ) = σ 2 ( A) [( x i - x j ) 2 + ( y i - y j ) 2 ] = σ 2 ( A)D ij 2 σ 2 ( P ij ) = A P S WL PDij S P = σ( A) = σ( B)
39 Mismatch Modelling in a CAD Tool P i = P mean + P global + P rand_i + P grad_i Technology Average Corner (common for whole die) Size-dependent mismatch (2-10 random numbers per transistor) Gradient-induced mismatch (2 random numbers per die) need layout coordinates
40
41 Motivations: Why? New nano devices are rapidly appearing offering new functionality and memory capabilities 17 memristors in a row. The wires in this image are 50nm about 150 atoms, wide. J. J. Yang, HP Labs NOMFET OG-CNFET Parallely, new circuits and architectures should be devised exploiting new capabilities Models are needed to simulate architectures and circuits Physical modelling is a slow, complex and sophisticated process Fitting new devices to a compact CMOS model has the advantage that circuit simulators are available allowing quick design and simulation of new architectures Hybrid nano-cmos arquitectures can be easily simulated ZnO-MemoryFET Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
42 EKV Compact Model [Enz et al. 1995] log scale I DS I F I R θ( V P min( V D, V S )) I off linear scale I F I R I s i f ( V P, V S ) I s i r ( V P, V D ) linear scale V P V G V TO n i fr ( ) 1 V P ln V SD ( ) + exp U t 2 linear scale Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
43 ACM Compact Model [Cunha et al., 1995] I DS I F I R θ( V P min( V D, V S )) I off I F I R I s i f ( V P, V S ) I s i r ( V P, V D ) V P V P V G V TO n i 2 fr ( ) q' is( d) + V SD ( ) φ t q' is( d) 1 2q' is( d) (( ) + ln q' is( d) ) Other compact models could have been used [Iñiguez et al., 1995] Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
44 NABAB Nano Devices: OG-CNFET OG-CNFET: Optically Gated Carbon Nanotube FET P-type Carbon nanotubes single/network coated with photosensitive polymers act as memory devices Change in conductance four orders of magnitude upon illumination Response to light robust and reversible Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN
45 NABAB Nano Devices: NOMFET NOMFET: Nano Particle Organic Memory FET Transistor Three terminal device p + common gate/200nm Si0 2 /gold source-drain electrodes/interelectrode gap μm Au nanoparticles deposed on the inter-electrode gap before pentacene deposition NPs are afterwards inmobilized using surface chemistry Pentacene (organic p-type semiconductor) deposited on top Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
46 NABAB Nano Devices: ZnO NW memory FETs ZnO nanowires dispersed on a Si0 2 -coated Si substrate 100nm thick Si0 2 Drain/source metal electrodes grown by photolitography Coated with layer of ferroelectric nanoparticles shifts threshold voltage positively or negatively depending on polarization Top gate made easy to change the orientation of polarization completely Long retention times Reversible Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
47 Fitting OG-CNFET to the EKV model. Experimental Results Different type of channel Different oxide thickness Different size * Device L g =200nm, t ox =2nm, single tube: I S =0.4nA n=1.22 V TO =0.7895V θ=1.7530v -1 I off =8.7pA Device L g =8000nm, t ox =10nm, network of nanotubes: I S =17.0nA n=7.78 V TO =0.5396V θ=2.2085v -1 I off =6.6pA r Device L g =8000nm, t ox =20nm, network of nanotubes: I S =28.6nA n=11.82 V TO =1.1904V θ=1.6013v -1 I off =2.5pA Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
48 Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN Fitting OG-CNFET to the EKV model. Experimental Results
49 Fitting NOMFET to the EKV model. Experimental Results Same device Different programming conditions. Writing V GS =-50V for 30 seconds Erasing V GS =50V for 30 seconds * Device W=1000μm, L=1μm, t ox =200nm, initial: I S =58.6μA n=177 V TO =-44.95V θ=0v -1 I off =1.7μA r Device W=1000μm, L=1μm, t ox =200nm, after writing: I S =65.4μA n=199 V TO =-48.74V θ=0v -1 I off =0.6μA Device W=1000μm, L=1μm, t ox =200nm, after erasing: I S =6.7μA n=140 V TO =-28.44V θ=0v -1 I off =0.6μA Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
50 Fitting ZnO Memory FET to the EKV Model. Experimental Results r Device bottom gated ZnO nanowire, L=3μm, t ox =100nm, V GS swept -10V to 15V: I S =0.5521nA n=1.84 V TO = V θ=0.0006v -1 I off =0.0259pA Device bottom gated ZnO nanowire, L=3μm, t ox =100nm, V GS swept 15V to -10V: I S =6.7μA n=10.88 V TO =1.6554V θ=0v -1 I off =0.1926pA Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es
51
52
EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-
EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made?
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationP. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationRFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits
A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits M. Baraani Dastjerdi and H. Krishnaswamy CoSMIC Lab, Columbia University, New
More informationLecture 11: MOSFET Modeling
Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
More informationSystematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation
Analog Integrated Circuits and Signal Processing, 21, 271±296 (1999) # 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Systematic Width-and-Length Dependent CMOS Transistor Mismatch
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationEKV MOS Transistor Modelling & RF Application
HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,
More informationCut-and-Paste Organic FET Customized ICs for Application to Artificial Skin
Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin Takao Someya 1, Hiroshi Kawaguchi 2, Takayasu Sakurai 3 1 School of Engineering, University of Tokyo, Tokyo, JAPAN 2 Institute
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationHW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7
HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationMOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationRandom Offset in CMOS IC Design
Random Offset in CMOS C esign ECEN487/587 Analog C esign October 19, 007 Art Zirger, National Semiconductor art.zirger@nsc.com 303-845-404 Where to start? How do we choose what transistor sizes to use
More informationA nanoparticle-organic memory field-effect transistor behaving as a programmable spiking synapse
A nanoparticle-organic memory field-effect transistor behaving as a programmable spiking synapse F. Alibart,. Pleutin, D. Guerin, K. Lmimouni, D. Vuillaume Molecular Nanostructures & Devices group, Institute
More informationSupporting information
Supporting information Design, Modeling and Fabrication of CVD Grown MoS 2 Circuits with E-Mode FETs for Large-Area Electronics Lili Yu 1*, Dina El-Damak 1*, Ujwal Radhakrishna 1, Xi Ling 1, Ahmad Zubair
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More information3/10/2013. Lecture #1. How small is Nano? (A movie) What is Nanotechnology? What is Nanoelectronics? What are Emerging Devices?
EECS 498/598: Nanocircuits and Nanoarchitectures Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5) Lectures 2: ITRS Nanoelectronics Road Map (Sept 7) Lecture 3: Nanodevices; Guest Lecture by
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationP-MOS Device and CMOS Inverters
Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short
More informationGold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications
Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications D. Tsoukalas, S. Kolliopoulou, P. Dimitrakis, P. Normand Institute of Microelectronics, NCSR Demokritos, Athens, Greece S. Paul,
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationDigital Electronics Part II - Circuits
Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More informationEE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an n-channel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationSemiconductor Memory Classification
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH
More informationEE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor
More informationLecture 210 Physical Aspects of ICs (12/15/01) Page 210-1
Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
More informationLecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationMetal-Oxide-Semiconductor Field Effect Transistor (MOSFET)
Metal-Oxide-Semiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n- substrate - SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate
More informationPart 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics
MOS Device Uses: Part 4: Heterojunctions - MOS Devices MOSCAP capacitor: storing charge, charge-coupled device (CCD), etc. MOSFET transistor: switch, current amplifier, dynamic random access memory (DRAM-volatile),
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationnmos IC Design Report Module: EEE 112
nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the
More informationSimulation of the Temperature Influence in IC-EMC
Simulation of the Temperature Influence in IC-EMC E. Sicard INSA-GEI, 135 Av de Rangueil 31077 Toulouse France Contact : etienne.sicard@insa-toulouse.fr web site : www.ic-emc.org Abstract: We investigate
More informationMetallic: 2n 1. +n 2. =3q Armchair structure always metallic = 2
Properties of CNT d = 2.46 n 2 2 1 + n1n2 + n2 2π Metallic: 2n 1 +n 2 =3q Armchair structure always metallic a) Graphite Valence(π) and Conduction(π*) states touch at six points(fermi points) Carbon Nanotube:
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationThe K-Input Floating-Gate MOS (FGMOS) Transistor
The K-Input Floating-Gate MOS (FGMOS) Transistor C 1 V D C 2 V D I V D I V S Q C 1 C 2 V S V K Q V K C K Layout V B V K C K Circuit Symbols V S Control Gate Floating Gate Interpoly Oxide Field Oxide Gate
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationImpact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies. Philips Research, The Netherlands
Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies Hans Tuinhout, The Netherlands motivation: from deep submicron digital ULSI parametric spread
More informationModeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation
Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004, pp. 1283 1287 Modeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation I.
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More informationEE382M-14 CMOS Analog Integrated Circuit Design
EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationCMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well
6.01 - Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Outline Announcements PS #9 - Will be due next week Friday; no recitation tomorrow. Postings - CMOS scaling (multiple
More informationEE 435. Lecture 22. Offset Voltages
EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationEE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS
EE 240B Spring 2018 Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models Elad Alon Dept. of EECS Square Law Model? Assumptions made to come up with this model: Charge density determined
More informationAnalysis of Transconductances in Deep Submicron CMOS with EKV 3.0
MOS Models & Parameter Extraction Workgroup Arbeitskreis MOS Modelle & Parameterextraktion XFAB, Erfurt, Germany, October 2, 2002 Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0 Matthias
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationCHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS
98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC
More informationInvestigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions
Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Ralf Brederlow 1, Georg Wenig 2, and Roland Thewes 1 1 Infineon Technologies, Corporate Research, 2 Technical
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationEE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More information