RFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits

Size: px

Start display at page:

Download "RFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits"

Marcia Sharp
5 years ago
Views:

1 A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits M. Baraani Dastjerdi and H. Krishnaswamy CoSMIC Lab, Columbia University, New York, United States 1

2 Outline Motivation and Prior Art Simplified Surface Potential Model Short-Channel Effects Simulation and Measurement Results Conclusion 2

3 Outline Motivation and Prior Art Simplified Surface Potential Model Short-Channel Effects Simulation and Measurement Results Conclusion 3

4 Circuits That Use FETs As Switches Passive-Mixers and Mixer-First Receivers N-Path Filters Integrated Circulators [Ghaffari JSSC 13] [Andrews JSSC 10] [Reiskarimian Nature Comm. 16] 4

Out-of-band IIP 3 is calculated using [Yang TCASI 15].

5 Mixer-First Receiver Design Challenges Increasing switch FETs size improves linearity at the cost of power consumption. Increasing series resistance R M improves linearity at the cost of NF. Out-of-band IIP 3 is calculated using [Yang TCASI 15]. Power consumption is calculated for an operating frequency of 1GHz. Linearity simulations are critical during the design phase for the optimization of passive mixer-like circuits. 5

6 FET Operation As a Switch MOSFET switches are symmetric devices and typically experience source-drain reversal during AC operation. 6

7 Gummel Symmetry Test In BSIM4 65nm CMOS; FET size: 96μm 65nm ; V GB = 1.2V and V b =0.3V. In BSIM4 models, the 2 nd derivative of I DS shows discontinuity around V DS =0. 7

8 Two-Tone Test Using BSIM4 Model V out 65nm CMOS; FET size: 96μm 65nm ; V GB = 1.2V. The IM 3 predicted by BSIM4 models shows unphysical characteristics (slope of 2dB/dB). 8

9 Transistor Models Comparison Source-referenced models E.g. BSIM Body-referenced models E.g. PSP Physical driving forces are V GS and V DS. V T appears in the equations. Velocity saturation is easy to handle. Asymmetric around the source-drain reversal point. Symmetry is appealing. Effective mobility is well handled. It is easy to make the drain current continuous at V DS =0. Not provided by most digitallydriven foundries. 9

Prior Work Break the transistor into 2n+1

High processing load (if n=32, 1 FET is replaced by

10 Prior Work Break the transistor into 2n+1 transistors in parallel with small offset voltages in V DS. 3dB/dB slope over limited region [Yuksel RFIC 14] High processing load (if n=32, 1 FET is replaced by 65 FET). Predicts 3dB/dB for IM 3 only for ΔV <V DS < nδv. Need measurements to extract value of ΔV. 10

11 Prior Work Break the transistor into 2n+1 transistors in parallel with small offset voltages in V DS. 3dB/dB slope over limited region [Yuksel RFIC 14] High processing load (if n=32, 1 FET is replaced by 65 FET). Predicts 3dB/dB for IM 3 only for ΔV <V DS < nδv. Need measurements to extract value of ΔV. 11

12 Outline Motivation and Prior Art Simplified Surface Potential Model Short-Channel Effects Simulation and Measurement Results Conclusion 12

13 Simplified Surface Potential Model Simple Verilog-A code is employed to define the I DS based on FET terminal voltages using simplified surface potential (SSP) equations. 13

14 Simplified Surface Potential Model Foundry provided model is used to take into account the 2 nd order parasitics Gate-source and gate-drain capacitance. 14

15 Simplified Surface Potential Model Foundry provided model is used to take into account the 2 nd order parasitics Body-source and body-drain capacitance. 15

16 Simplified Surface Potential Model Foundry provided model is used to take into account the 2 nd order parasitics Gate and body leakage currents. 16

17 Surface Potential Equations Surface potential at source and drain ends can be described by*: ψ s0 = V GB V FB γ ψ sl = V GB V FB γ ψ s0 + φ t e (ψ s0 2φ F V SB )/φ t ψ sl + φ t e (ψ sl 2φ F V DB )/φ t 0 L ψ s0 ψ sl V FB : Flat-band voltage γ: Body coefficient φ F : Fermi voltage φ t : Thermal voltage * Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor. Oxford Univ. Press,

18 Surface Potential Along The Channel Surface Potential along the channel can be approximated linearly. 0 L Surface Potential ψ sl ψ sm ψ s0 0 L Position along channel ψ sm = ψ s0 + ψ sl 2 18

19 Drain-Source Current Equation The drain-source current is a combination of drift and diffusion currents and can be approximated by*: I DS,total = I DS,drift + I DS,diff. I DS,drift = W L μc ox(v GB V FB ψ sm γ ψ sm )(ψ sl ψ s0 ) I DS,diff. = W L μc oxα m φ t (ψ sl ψ s0 ) α m = 1 + γ 2 ψ sm W : Width L : Length μ : Mobility of electron V FB : Flat-band voltage γ: Body coefficient φ F : Fermi voltage Completely symmetric at V DS =0. 19

20 Effective Mobility The mobility of electrons is reduced by the transverse field in the channel*. 0 L μ 0 μ eff = 1 a 0 (Q ε B + η EQ I ) s Q B = C oxγ ψ sm Q I = C ox V GB V FB ψ sm Q B μ 0, a 0 and η E can be treated as curve fitting parameters. 20

21 Outline Motivation and Prior Art Simplified Surface Potential Model Short-Channel Effects Simulation and Measurement Results Conclusion 21

22 Charge Sharing The extension of the drain and source depletion charge into the channel reduces the gate control over the channel charge. γ 1 = γ Q B Q B Q B Q B = 1 d j L ( db d j ) Depletion region is not necessarily same around the source and drain. 22

23 Charge Sharing The extension of the drain and source depletion charge into the channel reduces the gate control over the channel charge. γ 1 = γ Q B Q B Q B Q B = 1 Δ S L (1 db S 2dB ) Δ D L (1 db D 2dB ) Δ S/D = d j db S/D d j db = db S + db D 2 d j : Junction depth Completely symmetric at V DS =0. 23

24 Velocity Saturation Velocity of carriers can saturate even with device operating in triode. Carrier velocity 0 L ε c E X I DS,w Velocity Saturation = I DS,w/o Velocity Saturation 1 + V DS Lε c Second order derivatives are discontinuous. 24

25 Velocity Saturation Velocity of carriers can saturate even with device operating in triode. Carrier velocity 0 L I DS,w Velocity Saturation = I DS,w/o Velocity Saturation 0.5( V DS Lε c Accurately models the current and its derivatives. ε c 2 ) E X 25

26 Channel Length Modulation Channel length modulation can be described as: L eff = L l p l p = l a ln 1 + V DSX V DS,eff V e, l a = 3t ox d j t ox : gate oxide thickness d j : source and drain junction depth V e : Early voltage Smoothing functions are employed to ensure about the continuity of the current around V DS =0*: V DS,eff = V DS (1+( V DS V DS ) 10 ) 0.1, V DSX = V 2 DS V DS : Smoothing function constant *X. Li et al., PSP 102.3, NXP Semiconductors, Tech. Rep

27 Model Parameter Extraction Foundry Foundry provided provided model model Simulator Curve-fitting using using MATLAB SSP model SSP parameters model parameters 27

28 PSP Model Versus SSP Model SSP Model less Less than 20 parameters Ignoring Ignores temperature the temperature variation variation and process and corners process corners simulate Only used transistors for transistors operating as operating a switchas a switch PSP hundreds Hundreds of parameters Includes the temperature variations and process corners all All regions of the operation 28

29 PSP Model Versus SSP Model Only transistors operating as a switch are replaced with the SSP model. 29

30 Outline Motivation and Prior Art Simplified Surface Potential Model Short-Channel Effects Simulation and Measurement Results Conclusion 30

31 Measured Gummel Symmetry Test 65nm CMOS; FET size: 96μm 65nm ; V GB = 1.2V and V b =0.3V. The SSP model accurately predicts I DS and its derivatives. 31

32 Terminal Capacitance Simulation All capacitors: 1F All Inductors: 1H 65nm CMOS; FET size: 96μm 65nm ; V GB = 1.2V and V b =0.3V. The SSP model fixes the discontinuity in the terminal capacitances. 32

33 FET IIP 3 Simulation 65nm CMOS; FET size: 96μm 65nm ; V g = 1.2V. The model predicts 3dB/dB slope for IM 3 for a wide range of drainsource voltage across the FET. 33

65nm CMOS Mixer-First Receiver 4-Path 0.15-2.

34 65nm CMOS Mixer-First Receiver 4-Path GHz passive-mixer-first receiver in 65nm CMOS. 34

35 Mixer-First Receiver Gain 35

36 Mixer-First Receiver Out-of-Band IIP 3 The LO frequency is 300MHz and input tones are applied at 500MHz and 699MHz. The SSP model predicts IIP 3 with better than 3dB precision. 36

37 Comparison Table This work [Yuksel 14] Mixer-first receiver OOB-IIP 3 simulation accuracy Single switch simulation time(s)** Mixer first receiver simulation time(min) 3dB (4-phase) 4dB* (8-phase) *** Not feasible *This is an 8-phase mixer-first receiver reported in [Andrews JSSC 10]. **The computer is equipped with quad-core i7 CPU and 32GB physical memory, and simulations are performed on schematic level. ***Simulation is performed with the PSS-shooting method with number of harmonics equal to 175, the LO frequency is 300MHz and tones are applied at 500MHz and 680MHz and simulation is done for 3 power level point. 37

38 Outline Motivation and Prior Art Simplified Surface Potential Model Short-Channel Effects Simulation and Measurement Results Conclusion 38

39 Conclusion Digitally-driven foundries typically provide BSIM4 models that yield unphysical results when simulating passive mixer-like circuits. A simplified surface potential model is introduced that does not require measurements for model fitting, and leverages the foundry-provided models for capturing second-order parasitics. The SSP model is more computationally relaxed than prior art, and shows greater accuracy in simulating linearity of passive-mixer-like circuits. The model is available at cosmic.ee.columbia.edu for download. 39

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2