Chapter 20. Current Mirrors. Basics. Cascoding. Biasing Circuits. Baker Ch. 20 Current Mirrors. Introduction to VLSI
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1 Chapter 20 Current Mirrors Basics Long Channel Matching Biasing Short Channel Temperature Subthreshold Cascoding Simple Low Voltage, Wide Swing Wide Swing, Short Channel Regulated Drain Biasing Circuits Long Channel Biasing Short Channel Biasing Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 1
2 I ds1 Current Mirrors - Basics LONG CHANNEL DERIVATION IDEAL OUTPUT RESISTANCE=OO OUTPUT CURRENT INDEPENDENT I ds2 Vgs1 Vgs2 OF VOLTAGE ACROSS SOURCE ASSUME M1, M2 SAME W, L D1 SHORTED TO G1 V GS1 =V DS1 =V GS2 DUE TO SAME Vgs, SAME Ids IF RES EQUAL, M2 VD=M1 VD THEREFORE: V GS1 =V DS1 =V GS2 =V DS2 MARTIN CURRENT IN M1: I REF = I D1 = (KP N /2) (W 1 /L 1 ) (V GS1 -V tn ) 2 KNOWN: V GS1 = V GS2 V DS1,SAT = V GS1 -V tn (WHERE V DG =V tn ) CURRENT IN M2: I O = I D2 = (KP N /2) (W 2 /L 2 ) (V GS1 -V tn ) 2 RATIO OF THE CURRENTS: I O / I REF = (W 2 /L 2 ) / (W 1 /L 1 ) IF L 1 =L 2, THEN: I O / I REF = W 2 / W 1 Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 2
3 Current Mirrors - Basics LONG CHANNEL DERIVATION I O / I REF = W 2 / W 1 SCALE W TO GET VARIOUS I O WHAT IS THE RESISTOR VALUE? FOR I REF =20uA, I REF =(VDD-V GS1 )/R R=(5-1.05)/20uA R=200k OHMS HOW IS V GS1 =1.05 FOUND? SWEEP V O TO FIND WHERE I REF =I O SOLVE THE EQUATION: I REF = I D1 = (KP N /2) (W 1 /L 1 ) (V GS1 -V tn ) 2 KNOW I REF, KP, W, L, Vt WHY DOES I O DROP BELOW 250mV? CURRENT SOURCE RANGE: V DS,SAT < V O < VDD IMPORTANT IDEAS: I O = I REF WHEN V O =V DS1 =V GS1 I REF, V GS1 NOT DEPENDENT ON V O Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 3
4 ETCHED MORE ON OUTER POLY Current Mirrors - Basics Baker Ch. 20 Current Mirrors CAP REDUCED BY (n+1)/2n REDUCED RESISTANCE PROCESS CAUSE FIRST-ORDER PROCESS ISSUES: GATE OXIDE THICKNESS LATERAL DIFFUSION OXIDE ENCROACHMENT OXIDE CHARGE DENSITY THRESHOLD MISMATCH MISMATCH IN Vt LEADS TO: I O /I REF ~ 1 [2 Vt / (V GS -Vt) ] = 1 [2 Vt / (V DS,SAT ) ] WANT LARGE VGS REDUCES MISMATCH TRANSCONDUCTANCE MISMATCH MISMATCH IN KP LEADS TO: I O /I REF ~ 1 + [KP N / KP N ] WANT LARGE AREA, KP INCR V DS MISMATCH I O /I REF ~ [1 + 2 V O ] / [1+ 1 V DS1 ] V DS VARIES W/ RESISTANCE DO NOT USE SHORT CHANNEL Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 4
5 Current Mirrors - Basics LAYOUT CONSIDERATIONS DO NOT CHANGE ORIENTATION IMPLANTS ARE ORIENTED INTERDIGITIZE FINGERS COMMON GATE AVERAGES PROCESS VARIATIONS DIFFERING WIDTHS ISSUES LATERAL DIFFUSION L DIFF OXIDE ENCROACHMENT W ENC I O /I REF = (W 2,DRAWN -2W ENC )(L 1,DRAWN -2L DIFF ) / (W 1,DRAWN -2W ENC )(L 2,DRAWN -2L DIFF ) FIX L 1 =L 2, MINIMIZE MISMATCH WIDTHS DETERMINE OFFSET BUILT IN MISMATCH USE FOLDING TO REDUCE MISMATCH Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 5
6 Current Mirrors - Basics BIASING DO NOT WANT TO USE RES VARIES WITH TEMPERATURE WANT I REF VDD-INDEPENDENT REPLACE RES WITH XTOR USE EITHER M1 OR M3 WANT VDS IND OF VDD, GND EXAMPLE CHANGE VS. VDD: I O ~ 8nA / mv I REF (XTOR) ~ 12nA / mv I REF (RES) ~ 5nA / mv USING MODELS FROM BOOK Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 6
7 ADD PMOS CURRENT MIRROR Current Mirrors - Basics SUPPLY INDEPENDENT BIAS WANT I REF VDD-INDEPENDENT LAST EXAMPLES 5-12nA/mV MOVE RESISTOR FROM DS DRAWBACK: V GS2!=V GS5 MOVE RES TO SOURCE ADD M1 DIODE CAN USE M1 AS DIODE MIRROR M1 CURRENT TO M5 NEED M2=M1 CURRENT ADD PMOS CURRENT MIRROR DERIVE I REF AS A FNCT OF VDD V GS1 =V GS2 +(I REF )(R) MAKES SENSE IF V GS1 >V GS2 DONE BY MAKING W 2 >W 1 RESULT: I REF = [ 2 / (R 2 K PN W 1 L 1 ) ] [ 1-(1/(K) 1/2 ) ] 2 I REF INDEPENDENT OF VDD CONSTANT-GM BIAS CIRCUIT K=4, EVALUATE EQUATION g m =[ 2K PN (W/L) I REF ] 1/2 = 1/R Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 7
8 VDD<VG<VDD-Vtp X Current Mirrors - Basics 0 NMOS SWITCH 1 0 Baker Ch. 20 Current Mirrors PARASITIC CAP BIASING-USING STARTUP UNWANTED STATE M1, M2 GATES AT GND M3, M4 GATES AT VDD NO CURRENT FLOWS NEED STARTUP IN THE ZERO-CURRENT STATE MSU1 VG=0 MSU2 VG>=VDD-Vtp MSU3 TURNS ON M3/4 M1/2 M1/2 RISE, CIRCUIT WORKS MSU3 GATE GOES TO GND POSITIVE FEEDBACK ISSUES STABLE IF GAIN < 1 RESISTOR SMALL, GAIN>1 M2 PARASITIC CAP, R0 CIRCUIT WILL OSCILLATE RESULTS VDD MIN =V DS3,SAT +V GS1 ~1.3V I REF / VDD ~ 800pA / mv COMPARE TO 5-12nA / mv Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 8
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