CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices

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1 EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture Dimensions CMOS cross-section Passive devices esistors Capacitors (Inductors 700µm 3nm 00nm 0.8µm 0.6µm Next time: MOS transistor Drawing is not to scale! EECS240 Lecture 2 2 EECS240 Lecture 2 5 CMOS Process EECS µm P6M CMOS Minimum channel length: 0.8µm level of polysilicon 6 levels of metal (Cu.8 supply Other choices Shorter channel length (65nm / Bipolar, SiGe HB SOI Devices Active NMOS, PMOS ertical PNP Diodes Options (e.g. BiCMOS Passive esistors Capacitors Inductors EECS240 Lecture 2 3 EECS240 Lecture 2 6

2 esistors No provisions in standard CMOS esistors are bad for digital circuits Minimized in standard CMOS Sheet resistance of available layers: Layer Aluminum Polysilicon N+/P+ diffusion N-well Sheet resistance 60 mω/ 5 Ω/ 5 Ω/ kω/ EECS240 Lecture 2 7 Silicide Block Option Layer N+ poly P+ poly N+ diffusion P+ diffusion N-well / [Ω/ ] C [ppm/ o 25 o C C [ppm/] ,000 B C [ppm/] ,000 Non-silicided layers have significantly larger sheet resistance esistor nonidealities: emperature coefficient: f( oltage coefficient: f( as EECS240 Lecture 2 0 How about an N-Well esistor? esistor Example Goal: 00 kω, C / x d/d 0 Example Solution: N+ and P+ poly resistors in series N ( + CN + P( + CP N + P + ( NCN + PCP N P 0 CN CP CP CN 20kΩ 200 squares 80kΩ squares EECS240 Lecture 2 8 EECS240 Lecture 2 Process Options Available for many processes oltage Dependence Add features to baseline process E.g. Silicide block option High voltage devices (2.5 & 3.3, >0 Low H devices Capacitor option (2 level poly, MIM EECS240 Lecture 2 9 EECS240 Lecture 2 2

3 oltage Coefficient Common Centroid and Dummies p - substrate n - well 2 B p + diffusion n + diffusion 2 I o + C Example: Diffusion resistor Applied voltage modulates depletion width (cross-section of conductive channel Well acts as a shield o + ( 25 + C ( 2 + BC B 2 2 Example: : 2 : 2 Dummy Dummy gradient 0.5 * * 2 - EECS240 Lecture 2 3 EECS240 Lecture 2 6 esistor Matching ypes of mismatch: un-to-run variations Global differences in thickness, doping, etc. Systematic (e.g. contacts andom variations between devices un-to-run variations in absolute value: 20+% Can be problematic for termination, bias current, etc. Best case: make circuit depend only on ratios E.g., use feedback to control opamp gain With careful layout, can get 0. % matching esistor Layout (cont. Serpentine layout for large values: Better layout (mitigates offset due to thermoelectric effects: See Hastings, he art of analog layout, Prentice Hall, 200. EECS240 Lecture 2 4 EECS240 Lecture 2 7 Systematic ariations from Layout For example, due to contacts: 2? Use unit element instead: 2 EECS240 Lecture 2 5 MOSFEs as esistors riode region ( square law : W L I D µ Cox GS for GS > Small signal resistance: I D W µ Cox ( GS L C GS 2 for W µ Cox ( GS L oltage coefficient: H >> EECS240 Lecture 2 8 GS H

4 MOS esistors Example: MΩ Large -values realizable in small area ery large voltage coefficient C W µ Cox ( GS L W L µ Cox( GS µa 00 MΩ GS 2 H Applications: MOSFE-C filters: (linearization ef: sividis et al, Continuous- ime MOSFE-C Filters in LSI, JSSC, pp. 5-30, Feb Biasing: (>GΩ ef: Geen et al, Single-Chip Surface-Micromachined Integrated Gyroscope with o /hour oot Allen ariance, ISSCC, pp , Feb Capacitors Improved capacitor: substrate Is this only capacitor? EECS240 Lecture 2 9 EECS240 Lecture 2 22 esistor Summary Capacitor Options No or limited support in standard CMOS Large area (compared to FEs Nonidealities: Large run-to-run variations emperature coefficient oltage coefficients (nonlinear Avoid them when you can Especially in critical areas, e.g. Amplifier feedback networks Electronic filters A/D converters We will get back to this point ype Gate Poly-poly (option Metal-metal Metal-substrate Metal-poly Poly-substrate Junction caps C [af/µm 2 ] 0, ~ 000 C [ppm/] Huge 0 20 Big C [ppm/ o C] Big Big EECS240 Lecture 2 20 EECS240 Lecture 2 23 Capacitors Simplest capacitor: MOS Capacitor High capacitance in inversion substrate What s the problem with this? SPICE: I C ω ω C I EECS240 Lecture 2 2 EECS240 Lecture 2 24

5 MOS Capacitor High non-linearity, temperature coefficient But, still useful in many applications, e.g.: (Miller compensation capacitor Bypass capacitor (supply, bias MIM Capacitors Some processes have MIM cap as add-on option Separation between metals is much thinner Higher density Used to be fairly popular But not as popular now that have many metal layers anyways EECS240 Lecture 2 25 EECS240 Lecture 2 28 Poly-Poly Capacitor Applications: Feedback networks Filters (SC and continuous time Charge redistribution DACs & ADCs Saw cross-section Bottom- and top-plate parasitics Shields Capacitor Geometries Horizontal parallel plate ertical parallel plate Combinations ef:. Aparicio and A. Hajimiri, Capacity Limits and Matching Properties of Integrated Capacitors, JSSC March 2002, pp EECS240 Lecture 2 26 EECS240 Lecture 2 29 Capacitor Layout MOM Capacitors Unit elements Shields: Etching Fringing fields Common-centroid Wiring and interconnect parasitics ef.: Y. sividis, Mixed Analog-Digital LSI Design and echnology, McGraw-Hill, 996. Metal-Oxide-Metal capacitor. Free with modern CMOS. Use lateral flux (~L min and multiple metal layers to realize high capacitance values EECS240 Lecture 2 27 EECS240 Lecture 2 30

6 MOM Capacitor Cross Section Capacitor Q Use a wall of metal and vias to realize high density More layers higher density May want to chop off lower layers to reduce C bot easonably good matching and accuracy Current density drops as you go farther from contact edge EECS240 Lecture 2 3 EECS240 Lecture 2 34 Distributed Effects Double Contact Strucutre Can model IC resistors as distributed C circuits. Could use transmission line analysis to find equivalent 2-port parameters. Inductance negligible for small IC structures up to ~0GHz. If contact on both edges, drops 4X Can be a good idea even if not hitting distributed effects EECS240 Lecture 2 32 EECS240 Lecture 2 35 Effective esistance What About Inductors? High frequency resistance depends on W, e.g.: Wµ 0kΩ resistor works fine at GHz W5µ 0kΩ resistor drops to 5kΩ at GHz May need distributed model for accurate freq response EECS240 Lecture 2 33 Mostly not used in analog/mixed-signal design Usually too big More of a pain to model than s and C s But they do occasionally get used Example inductor app.: shunt peaking Can boost bandwidth by up to 85%! Q not that important (L in series with But frequency response may not be flat EECS240 Lecture 2 36

7 Spiral Inductors Used widely in F circuits for small L (~-0nH. Use top metal for Q and high self resonance frequencies. ery good matching and accuracy if you model them right EECS240 Lecture 2 37 Passives EECS240 Lecture 2 38