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1 Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: Ph: CLASS TEST 089 ELECTCAL ENGNEENG Subject : Analog Electronics Date of test : 05/08/08 Answer Key. (d) 7. (a) 3. (c) 9. (d) 5. (b). (a) 8. (a) 4. (c) 0. (a) 6. (d) 3. (b) 9. (b) 5. (b). (c) 7. (d) 4. (b) 0. (b) 6. (a). (b) 8. (a) 5. (a). (d) 7. (a) 3. (a) 9. (a) 6. (c). (c) 8. (c) 4. (a) 30. (b)
2 CT08 EE Analog Electronics 9 Detailed Explanations. (d) The given configuration is a current shunt feedback configuration. So, the input impedance decreases. (a) i if KA and the output impedance increases, of 0 ( KA i ) 3. (b) KCL at node V V V V0 0 V V V 0 V ( V V 0 ) V V ( ) 4. (b) For maximum power dissipation in Zener diode the current through the Zener diode should be maximum Therefore L value should be largest. Ω i S L 0 V Z 0 V L The maximum power dissipation in Zener diode is equal to power rating of the Zener diode. So P max 400 mw Thus z mw z 40 ma Now, s ma So L S z ma So L 0 V.98k Ω L 5. (a) Analyzing the circuit we observed that current is being sampled and current is being mixed. Thus, it is shuntseries feedback.
3 0 Electrical Engineering 6. (c) The given circuit is a potential divider/self biasing. B Stabilibity for self biasing circuit is given by: ( ) B β E S β B E For better stability S should be minimum B So, << E 7. (a) So β(forced) 0 C B 0 B ma The power dissipated in the transistor is P B V BE(on) C V CE(sat) ( ) (0.7) ( 0 3 ) (0.) P.8 mw 8. (a) The output voltage of an opamp integrator is t t VC V () t dt C 0 i ( ) dt C t t 0 C 0 t C At t ms, We want 0 V 9. (b) 0 Which means the time constant is 3 0 C τ C 0. ms Si max V Si kω kω k k kω V V D.7 V 0.7 V V max V kω ma
4 CT08 EE Analog Electronics 0. (b) During positive half cycle n kω kω kω this circuit can be redrawn as, n kω kω kω according to voltage division rule ( Vin )k Ω kω 5 sin ω 0 t this is during positive half cycle. Similarly during negative half cycle 5 sin ω 0 t n kω kω kω. (d) 5 sin ω 0 t 5 kω, 8 kω TH kω V TH ( 4) 5.8 V Thus the circuit is as follows 4 V 3 kω 5.8 V 6.06 kω kω
5 Electrical Engineering 5.8 (6.06 k) ( BQ ) V BE (β ) B ( k) (6.06 k 76 k) BQ BQ 6.4 µa EQ (β ) BQ 4.74 ma CQ β BQ 4.68 ma V CEQ 4 CQ C EQ E 4 (4.68) (3) (4.74) () 5. V. (c) As we know that for proper operation V DS V GS V T V D V S V G V S V T 5 V 5 V 5 V 5 V V D V G V T P Q at P V D V G V T Given V G for all transistor 5 V and V T for all transistors V V D at P V G V T 5 4 V V D at Q V G V T 5 4 V V D at V G V T 5 4 V According to the given options the only condition satisfied for the voltages at P, Q and is only option (c). 3. (c) When early affect is considered then the C  V CE plot is approximated by a straight line so from the given data we get slope of line equal to ma / V 0 So the equation of the straight line (relation between C  V CE ) C V CE 0 CmA value of C can be found by putting (.8 ma, V) in the above equation, V CE Hence, C.7 ma 0 Early voltage is the magnitude of value of V CE where C 0 So from above equation we get V A 34 V 4. (c) With all the parameter we draw the small signal model of the circuit, then we will find equivalent resistance seen across the capacitor. The cut off frequency will be π C eq The small signal model is
6 CT08 EE Analog Electronics 3 gmvbe 0 kω kω 0 kω V be r e r π β kω C 5 µ F The base resistance when seen from emitter get multiplied with. ( β ) So, eq r 0k k ( k ) π Ω Ω Ω β β eq (000) (6.40) 6.05 Ω So, f 97 Hz π C eq 5. (b) Since input impedance i 00 kω for 0 i 00 kω For the circuit shown is given by For 4 0, kω and For 4 0 kω, 0 or, 0 or,
7 4 Electrical Engineering or, 3. kω Hence, for potentiometer in the middle is ( 4 5 kω when potentiometer is set at its centre) or, (a) n the above circuit c B, B Applying KVL in the circuit, we get: (3 kω) (0 kω 68 kω) 0.7 or, (3K) (88 K).3 or, (9K) B (3K) C.3 or, C.58 ma 0 kω 68 kω 0.0µ F V 3 kω Thus, c.58 ma and E β C.60 β ma V T 6 r e 0 Ω and r.60 π βr e.4 kω E The small signal model of the given circuit for calculating the gain is shown below. 0 kω B i B C r π βi B r 0 E 68 kω 3 kω From the above circuit, i B V r π i or, and i B V O βi B (30 kω 68 kω 3 kω) i B ( ) i B So, A V V0 V i ( ) ib ib A V (a) n the circuit given below, ma 5 k
8 CT08 EE Analog Electronics ma.8k V 5 kω C 0 A C Q Q B.8 kω B KCL at node A C B C β C from here C since the circuit is current mirror circuit ma 8. (c) C C ma V kω kω 4 kω 8 kω V kω 7 kω The output of st opamp is represented by V o and output of second opamp is represented by V o. 8 8 So, V o V o 4 4 Vo 3...(i) and V o V o 8
9 6 Electrical Engineering 3 Vo...(ii) 8 Put the value of V o in equation (i), we get 3V V o o 3 8 3V o 6 4 4V o 3V o 8 7V o 8 V o 4 V 9. (d) We can write the dc drain current as 3V o D Q V 0.8 ma D ( 9) which yields V D 5.8 V Now, assume the transistor is biased in the saturation region. We then have D D V GS DSS VP 0.8 V GS.5.5 V GS.086 V Then V S V GS V V SD V S V D (5.8) 5.7 V 0. (a) kω ma kω x kω V Apply KCL at node V O, we get 0 3 x ( 0 ) ma
10 CT08 EE Analog Electronics 7. (c) To begin initially we assume both diode D and D are in their conducting state. Node equations at V A and V B are and ( V ) 5 B V A 0 D V A D 5 V B 0 We note that V B V A 0.7 Combining equations (i) and (ii) we find V A 7.6 V and V B 6.9 V Substituting this values in equation () D D ma Negative diode current shows that our assumption is wrong. Now assuming the diode D is off and D is on. V A V 0 V B (5 0.7) 9.53 V 0 5 The voltages shows that diode D is indeed reverse biased so D 0....(i)...(ii). (b) nitially assume each diode is in its conduction state. Starting with D 3 and considering the voltages, we see that V B 0.7 V and V A 0 KCL at node V A : V 5 ( 0.7) 0 A VA D 0 5K 5K Since V A D ma 5 0 which is inconsistent with the assumption that all diodes are on (an on diode would have a positive diode current). Now assume D and D 3 are on and D is off ( 0) D 5K 5K D.43 ma V A 5 ( ) (5 0 3 ).5 V
11 8 Electrical Engineering 3. (a) The given circuit is a current mirror circuit in which the output current is a mirror image of the input current if both the transistors are identical. i 9.3 kω 0 Q ( 700) β Q ( 75) β 4. (a) 0 V To calculate i, 9.3 i (0) 0 i ma Since the emitter area of transistor Q is half that of transistor Q, So i 0 /. Therefore, 0 ma V0 () s V () s where, z (s) sc z (s) sl i Z() s Z () s (s) LCs i V () s (t) Vm sin( ω0t) dt dt LC V m (t) sin( ω 0t) ω 0 5. (b) bias µ C W V V L n ox D ( ) GS T (V GS V T ) x C W L bias µ n ox µ C W V V L n ox D ( ) GS T...(i)...(ii)
12 CT08 EE Analog Electronics 9 Substituting the value of (V GS V T ) in equation (ii) x µ n Cox W bias L W n C µ ox L x bias 6. (d) Consider D OFF and D ON then Applying KVL in the outer most loop: 0 (00) ma now we calculate V D (9.5 0 )( 0 ) VD 0 V kω 0 Ω V D 0.3 V D 0.5 V since V D < 0.7 V, D is in OFF state i.e. our assumption is correct and hence (d) is correct option. 7. (d) G D V GS MΩ V g V m GS kω r 0 k d Ω z in MΩ z 0 r d D 0 k z 0 0 k Ω 8. (a) The duty cycle of the above astable multivibrator is T % duty cycle ON 00 T A B 00 A B A A 66% > 50% So, duty cycle of the output wave is greater than 50%
13 0 Electrical Engineering 9. (a) When the switch is closed the opamp is in closed loop. Thus, virtual short concept is applicable and current through the capacitor will be 0 ma. i.e., i C (t) 0 0 ma kω v c (t) t () C i C tdt 0 t (0 ma) (0) or, v c (t) dt t F 0 0 Thus, the value of v c at t ms will be 0 V 30. (b) n a CE unbypass amplifier, A V C E 4k k
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