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1 Serial : CH_EE_B_Network Theory_098 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: Ph: 056 CLASS TEST 089 ELECTCAL ENGNEENG Subject : Network Theory Date of test : /09/08 Answer Key. (b) 7. (a). (d) 9. (c) 5. (b). (c) 8. (a). (a) 0. (d) 6. (b). (c) 9. (d) 5. (b). (b) 7. (b). (c) 0. (c) 6. (b). (c) 8. (d) 5. (b). (b) 7. (a). (a) 9. (a) 6. (a). (b) 8. (c). (b) 0. (b)
2 8 Electrical Engineering Detailed Explanations. (b) The equation of line passing through origin is y m x V V y y t x x Vm t T0 V V m t T the instantaneous power for 0 t T 0 is p(t ) 0 Vmt T 0 0 t < 0.5T T t < T 0 0 P avg, observing that the fundamental period is T 0, we have P avg P avg 0.5T0 Vm t dt T 0 0 T0 V m T 0 V m t 0 0 T. (c) V C f f 0 V L V c vs () for f < f 0 V c > V L Since, lead source voltage if f < f 0 Hence V also leads source voltage. V L. (c) f C f 0 f L f β b a C V Applying KVL in loop β ( a c ) c ( a c ) (β c ) Comparing this with standard equation β c
3 CT08 EE Network Theory 9. (c) At ω 0 i.e. s 0 X L 0, X C There is no connection between input and output. so, V 0 At ω i.e. s X L, X C 0 Then also, there is no connection between input and output. so, V 0 Band pass filter 5. (b) At t 0 v c (0 ) v c (0 ) 0 short circuited i L (0 ) i L (0 ) 0 open circuited 0 Ω 0 Ω 50 V Applying KVL A 6. (a) 0 Non zero V α α 0 Here should be independent and V should be dependent with these conditions only parameters are possible. 7. (a) Below resonating frequency, X C > X L Current leads the applied voltage. 8. (a) The graph for the network can be drawn as Number of nodes n 5 Number of branches b 8 Minimum number of equations required b n (d) i(t) / e t (s) s s s ( s) Cs
4 0 Electrical Engineering from here, C F; (s) Ω s Cs C Cs 0. (c) Degree of each node in a fully connected graph is n.. (b) edrawing the circuit j j j 8 j 6 j j Bridge is balanced and circuit can be redrawn as eq Ω 8 Ω 5 Ω j Ω j Ω j6 Ω j5 Ω j Ω Ω 8 Ω eq j Ω j 6 Ω j Ω j Ω eq ( j j) (8 j6 j ) 6 j Ω 5 5. (b) These are networks connected in series for this network a a ( ) a ( ) a 5 a 5 Ω 5 Ω V a ( ) a ( ) a 5 ( ) b ( ) b /s /s s s b b ( ) b ( ) b s b s V b
5 CT08 EE Network Theory so, parameter matrix for series combination is a b s s s s s s s s s s s s. (d) edrawing the circuit Ω i x A i x 8 Ω V b Ω V a A 0i x Ω 0 Ω 50 V i x Applying KVL i x 8(i x ) i x 50 i x A Voltage across Ω resistor V a V b V Power dissipated in Ω (0) 00 W. (a) i i C i 5 u(t) C i i C 5( e t /τ ) A 5 e t/τ A At t t i i C 5( e t /τ ) A 5 e t /τ A / e t τ τ log e () sec 5. (b) Short circuiting V and redrawing the circuit t
6 Electrical Engineering V 0 V 0( 0.5 ) Y 0. V 5 V Ω 0 Ω Y 0.6 V 5 6. (b) The circuit can be represented as A.5 A A 00 Ω emaining Network 9.5 A Applying KCL at node A Total current entering at node A Total current leaving node A A 7. (a) At t 0 E 0 Ω H A At t 0 i(0 ) 6 A i(0 ) i(0 ) 6 A i H i B E
7 CT08 EE Network Theory d i E dt i 0 At t 0 Equation (i) becomes E i(6) 0...(ii) At t i B...(i) E E 8...(iii) From equation (ii) and (iii) 0.5 Ω 8. (c) From the characteristic V(Volts) (Ampere) 80 0 Open circuit 0 8 Short circuit V oc sc Network 80 V 8 A A V AB 0 B SC Th Ω Maximum power that can be transferred is Th V Th (80) 0 60 W 9. (c) h h V h h V h V V 0 Short circuiting the port
8 Electrical Engineering v x 8 Ω 6 Ω v y Ω v y 0vx 8 Ω v x Ω v x Ω v x / v x /6 v x Ω 6 Ω v y 0v x 8 v x v y v x Applying KCL v y 0v x v x v 0 x vx vx 7 v x Applying KVL at port v y v x 7 h 6.8 Ω 0. (d) For current to be in phase with applied voltage imaginary part of impedance should be zero. edrawing the circuit jxl jxl eq jxc jxc ( jx ) ( ) L jxc eq j XC j XC jxl jx L C ( C ) jx jx X C
9 CT08 EE Network Theory 5 equating imaginary part to zero X L C XC X 0 X C XL ( XC) X L C XC X. (b) edrawing the circuit 0 0 j 5 Ω Ω j j5 Ω B Applying Mesh Law Mesh j5 j 0 0 (5 j5) ( j) (i) Mesh j5 j 0 (6 j 5) ( j) 0...(ii) From equations (i) and (ii) V Th V AB () Ω A. (c) at t 0, the circuit will be Ω applying KVL A 5 at t 0 the circuit will be V C Volts 0V Ω C V C Ω V a H i L (0 ) i L (0 ) 0 A V a 7. V V a d i i dt 0 V Ω V i H
10 6 Electrical Engineering at t 0, i d i dt di dt.6 A/s. (a) B Fundamental loop matrix is always written in the form B [ : B T] dentity Matrix Q l [B T ] T and Q [Q l : ] Loop matrix with respect to given tree Q L T Q (b) edrawing the circuit Ω V 0. V () () s s 0 () s V () s 5. s 5. s 5. s Applying KVL in loop (s) (s) 0. V (s).5s V (s) 0 ( s).5 s 5. s 5. s...(i) 5 s ( s) V (s).5 s From equations (i) and (ii) nput admittance ( s) 5. s V( s) 6s...(ii)
11 CT08 EE Network Theory 7 5. (b) At t 0 Ω v c 0 V v c 5 Ω 0 v c...(i) from here 5 v c 0...(ii) for t 0 Applying KCL v c 0 V 0 V Ω V 0 V0 V0 V0 5 V eq 0 v c (t) ve 0 t/ eqc V 0 5 Ω 0 t e 0.5t e Volts 6. (b) 6 0 V V V oc 0 Ω 0 Ω 6 V 0 Ω 0 V V oc sc 0 A 0 Th V oc sc 0 0 Ω 0 Ω 0 V sc
12 8 Electrical Engineering P max oc ( V ) W Th 7. (b) Ω V j Ω L V 0 0 V L j Ω V L V 0 By Nodal Analysis V V V V j j L 0 L L 0 V j 0 VL 0...(i) By equation (i) and (ii) V V j 0 L 0 V L V j 0.5 Ω For power transfer to be maximum L 0 L 0.5 j0.5 Ω 8. (d) From the first circuit 6 V 0 i 6 i...() From the second circuit, Power across 0 Ω 90 W. i L 0 90 i L 9 A. V a.5 Ω 5 Ω Ω V 0 6 Ω 6V a 5 Ω 0 Ω i i 6 Va i L i 6Va Hence 6V a 6 V a i L 6 A V
13 CT08 EE Network Theory 9 From the figure, V a i i So, i A From equation () V 0 i V 9. (a) From the given figure. V The above equations can be rearranged as ( ) ( )... (i) V ( ) ( ) ( )... (ii) generator equivalent is ( ) V 0. (b) Under steady state V C L 5A Ω 0 L 5 V C L 0 Energy stored in capacitor Energy stored in inductor CV c L L or 5 Ω 0 0
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