# Electronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory

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1 Electronic Circuits Prof. Dr. Qiuting Huang 6. Transimpedance Amplifiers, Voltage Regulators, Logarithmic Amplifiers, Anti-Logarithmic Amplifiers

2 Transimpedance Amplifiers Sensing an input current ii in and converting it to an output voltage vv out Conversion is quantified by the transimpedance rr m = vv out ii in Ideally: ZZ in 0, ZZ out 0 [Ω] Applications of transimpedance amplifiers Optical communications: conversion of current detected by a photodiode to a useful voltage Generally: precise measurement of small currents in sensors (e.g., precision light meters, light barriers, X-ray detectors, ) 2

3 Transimpedance Amplifiers Based on Op-Amps Transimpedance amplifiers are most commonly implemented using operational amplifiers: Assuming op-amp to be ideal: Applying KCL at node () yields II in = II o = VV out RR f VV out II in = RR f Virtual ground assumption at node () implies VV in 0, and therefore ZZ in = VV in 0 II in Zero output impedance of ideal op-amp implies that ZZ out 0 Ideal transimpedance amplifier 3

4 Stability Considerations Determine Frequency Response Realistic op-amp model: Real op-amps AA V ss = VV out VV d have finite DC gain AA 0 (virtual ground assumption is not valid in real op-amps!) have finite bandwidth, mainly dominated by one pole pp 0 ( ωω pp0 = pp 0 ) are characterized by their Gain Bandwidth Product GBP = AA 0 ωω pp0 have an input capacitance CC in that further limits bandwidth AA 0 + ss ωω pp0 infinite input resistance and zero output resistance can usually be assumed also for real op-amps Realistic sensor model: Real sensors have a source resistance ( MΩ) show a capacitance CC S pf (e.g. occurring from the depletion region of a photodiode) 4

5 Frequency Response of Transimpedance Amplifiers (I) ZZ S = CC S + CC in = ( CC S ) VV out = AA V ss VV d = AA V ss VV in Feedback current II f stabilizes VV in : II f = VV in VV out RR f = VV in+aa V ss VV in RR f ZZ (ss) = VV in II f = RR f +AA V ss At DC: ZZ = RR f +AA 0 0 Transimpedance ZZ T = VV out II f VV out = AA V ss VV in = AA V ss ZZ II f experiences broadbanding due to feedback: ZZ T ss = AA V ss ZZ = RR f AA V ss +AA V ss = AA 0 RR f + AA 0 = RR faa 0 +AA 0 + ss AA 0 RR f AA0 GBP Bandwidth is limited by GBP = AA 0 ωω pp0 of op-amp 5

6 Frequency Response of Transimpedance Amplifiers (II) Input impedance ZZ in : KCL: II in VV in ZZ S = II f = VV in ZZ II in = VV in ZZ S +ZZ ZZ ZZ S ZZ in (ss) = ZZ S ZZ At DC: ZZ in = RR f +AA 0 RR f +AA 0 0 Closed-loop transimpedance ZZ T = VV out II in : II f = II in VV in ZZ S = II in II fzz ZZ S II f II in = VV out = AA V ss ZZ II f = ZZ ZZ S ZZ +ZZ S AA V ss II in ZZ T (ss) = AA L ss = AA V ss RR f ZZ S +AA V ss RR f AA V ss = RR f ZZ S +AA V ss +ZZ S ZZ S RR f +ZZ S is the loop gain ββ ss = ZZ S RR f +ZZ S is the feedback factor ZZ S ZZ +ZZ S, ZZ = RR f +AA V ss AA V ss +AA V ss ZZ S RR f +ZZ S AA L (ss) 6

7 Frequency Response of Transimpedance Amplifiers (III) Assuming ZZ SS to be fully resistive (ZZ SS = S, CC SS = 00): ZZ T ss = RR f A V ss Feedback factor +AA V ss ZZ T ss = RR f AA 0 RR f + RR f + reduces bandwidth: RR f + +AA 0 AA 0 RR f + RR f + ss, AA0RR f + RR f + < 7

8 Frequency Response of Transimpedance Amplifiers (III) Assuming ZZ SS to be fully resistive (ZZ SS = S, CC SS = 00): ZZ T ss = RR f A V ss Feedback factor +AA V ss ZZ T ss = RR f AA 0 RR f + RR f + reduces bandwidth: RR f + +AA 0 AA 0 RR f + RR f + ss, AA0RR f + RR f + < Example: Fixed = MΩ (): RR f = 0 kω RR f + = 0.99 (2): RR f = 00 kω RR f + = 0.9 (3): RR f = MΩ RR f + = 0.5 Gain-bandwidth trade-off: High transimpedance gain results in lower bandwidth (for fixed ) 8

9 Frequency Response of Transimpedance Amplifiers (IV) Assuming ZZ SS to be fully resistive (ZZ SS = S, CC SS = 00): The non-ideal op-amp leads to an error in transimpedance gain compared to the case with ideal op-amp Ideal transimpedance is RR f Normalized error is εε(ss) = RR f ZZ T ss RR f At DC: εε 0 = RR f+ AA 0 AA 0 0 = RR f + AA 0 +AA 0 AA 0 RR f +S S RR f + AA 0 + ss AA0RR f + A large AA 0 results in a small error Assuming fixed ωω pp0 : the predefined maximum error tolerated (e.g. εε = 0.00 = 60 db) is reached more quickly when AA 0 is small Assuming fixed AA 0 : when ωω pp0 is large, the transimpedance gain is accurate for a larger frequency range 9

10 Frequency Response of Transimpedance Amplifiers (V) ZZ SS = S CC SS = (S (CC SS + CC iiii )): RR f RR f ZZ S = RR f CC S RR f CC S ZZ T ss = RR f ZZ S AA V ss RR f AA 0 +AA V ss +sscc S RR f +AA 0 ZZ S RR f +ZZ S AA 0 RRf = RR f +sscc S RR f AA V ss +sscc S RR f +AA V ss RR f +ss AA0 = +sscc S RRf RR f CC S + AA0ωωpp S +ss 2 AA0 ωω pp S, ωω pps = Due to the capacitance CC S = CC S + CC in, the transimpedance amplifier becomes a second-order system with DC transimpedance gain RR f and loop gain AA 0 AA L ss = AA V ss + ss = ωω pps + ss + ss ωω pp0 ωω pps 0

11 Step Response of Second-Order Systems (I) Time-domain representation of the transimpedance amplifier: ZZ T ss = VV out = RR II f in +ss AA0 + AA0ωωpp S +ss 2 AA0 ωω pp S = RR f ωω n 2 ss 2 +2ζζωω n ss+ωω n 2 = RR f ωω2 n ss pp ss pp 2 This is equivalent to the homogeneous time-domain representation 2 VV out tt + 2ζζωω n VV out + ωω n 2 = 0, with characteristic equation ss 2 + 2ζζωω n ss + ωω n 2 = 0, and ωω n = AA 0 ωω pp0 ωω pps, ζζ = ωω pp 0 + ωω pps 2 AA 0 ωω pp0 ωω pps, pp = ζζωω n + ωω n ζζ 2, pp 2 = ζζωω n ωω n ζζ 2 ωω pp0 = pp 0, AA 0 ωω pp0 = GBP, ωω ppss = RR f CC, QQ = : quality factor S 2ζζ The value of ζζ determines three important cases of system behavior: Overdamped ζζ > : ζζ 2 > 0 the two solutions of the characteristic equation pp and pp 2 are real and negative Critically damped ζζ = : ζζ 2 = 0 the two solutions are identical pp = pp 2 = ωω n Underdamped 00 < ζζ < : ζζ 2 < 0 the two solutions are complex conjugates with pp = ζζωω n + jjωω n ζζ 2 and pp 2 = ζζωω n jjωω n ζζ 2

12 Step Response of Second-Order Systems (II) Overdamped system: ζζ >, QQ < 2 Homogeneous solution: VV out tt = KK ee pptt + KK 2 ee pp 2tt pp = ζζωω n + ωω n ζζ 2, pp 2 = ζζωω n ωω n ζζ 2 Superposition of two decaying exponentials Step response: VV out ss = RR f ss ωω n 2 ss pp ss pp 2 = RR f ss pp 2 pp 2 pp s pp + pp pp 2 pp s pp 2 VV out tt = RR f 2 ζζ ζζ 2 + ee ζζωω n+ωω n ζζ 2 tt + 2 ζζ ζζ 2 ee ζζωω n ωω n ζζ 2 tt The step response reaches steady-state value with no overshoots For larger ζζ, the response approaches the steady-state value more slowly 2

13 Step Response of Second-Order Systems (III) Underdamped system: 0 < ζζ <, QQ > 2 Homogeneous solution: VV out tt = ee ζζωωntt KK cos ωω d tt + KK 2 sin ωω d tt = KKee ζζωωntt cos(ωω d tt θθ), ωω d = ωω n ζζ 2 Superposition of two decaying oscillations Step response: ωω2 VV out ss = RR n f ss ss 2 +2ζζωω n ss+ωω2 = RR f n s ζωω n ss+ζζωω n 2 +ωω n 2 ζζ 2 ss+ζζωω n ss+ζζωω n 2 +ωω n 2 ζζ 2 VV out tt = RR f ζζee ζζωω ntt ζζ 2 sin ωω dtt ee ζζωω ntt cos ωω d tt The step response reaches steady-state value with overshoots and oscillations For larger ζζ, the amplitude of the overshoots decreases 3

14 Step Response of Second-Order Systems (IV) Parameters: Op-amp DC gain AA 0 = 0 4 (80 db) Op-amp GBP = 2ππ MHz ωω pp0 = 2ππ 00 Hz RR f = 0 kω, = 5 MΩ RR f, CC S = pf Example : CC in = pf CC S = CC S + CC in = 2 pf ωω pps = RR f CC S = 2ππ 7.96 MHz ωω n = AA 0 ωω pp0 ωω pps = 2ππ 2.82 MHz ζζ = ωω pp0 +ωω pp S 2 AA 0 ωω pp 0 ωω pp S =.4 overdamped Example 2: CC in = 5 pf ωω pps = 2ππ 2.65 MHz ωω n = 2ππ.63 MHz ζζ = 0.8 slightly underdamped Example 3: CC in = 25 pf ωω pps = 2ππ 62.3 khz ωω n = 2ππ khz ζζ = 0.39 underdamped Large op-amp input capacitances CC in may render the transimpedance amplifier strongly underdamped 4

15 Loop Gain Determines System Behavior (I) The loop gain AA L ss can also be used to determine the closed loop behavior of the transimpedance amplifier: For second-order systems, the phase of the loop gain AA L jjjj may drop close to AA L jjjj = 80 In this case, the negative feedback around the opamp becomes virtually positive. If at the same time AA L jjjj >, then this corresponds to a heavily underdamped system (ζζ ) when the loop is closed. In order to prevent this situation from happening, second-order systems are usually designed such that the loop gain AA L ss shows a large phase margin PM = AA L jjωω (where ωω 0 is defined as the frequency where AA L jjωω 0 = ) Large phase margins are required to achieve an overdamped step response (ζζ > is achieved for PM > 76 ) 5

16 Loop Gain Determines System Behavior (II) Parameters: Op-amp DC gain AA 0 = 0 4 (80 db) Op-amp GBP = 2ππ MHz ωω pp0 = 2ππ 00 Hz RR f = 0 kω, = 5 MΩ RR f, CC S = pf The loop gain was computed as AA L ss = AA 0 ωωpp S Example (as before): CC in = pf ωω pps = 2ππ 7.96 MHz ζζ =.4, PPPP = Example 2 (as before): CC in = 5 pf ωω pps = 2ππ 2.65 MHz ζζ = 0.8, PPPP = Example 3 (as before): CC in = 25 pf ωω pps = 2ππ 62.3 khz ζζ = 0.39, PPPP =

17 Concept of a Linear Voltage Regulator General principle of linear voltage regulators: Non-inverting topology Use feedback to adjust VV out at II L by RR CTRL : Inverting topology 7

18 Line Regulator Concept Practical Implementation Non-inverting topology Inverting topology The reference voltage VV ref can be set accurately relying on the laws of semiconductor physics (e.g., band-gap reference in semiconductor material with VV ref.2 V) Design choice: RR F, RR F2 RR L, so that II L II EE / II CC VV out = + RR F RR F2 VV ref 8

19 Non-Inverting Line Regulator Generalized Load Condition Load components: CC L Bypass capacitor for load RR L Load model resistive part II L tt Dynamic load current (e.g. circuit parts switched on/off) Ideal static behavior AA 0 : Example: integrated.2 V analog-to-digital convertor, 20 MHz BW: CC L = 50 pf (on chip) RR L = 300 Ω II L = 4 ma II E = VV out RR L + II L VV out = + RR F RR F2 VV ref 9

20 Small Signal Analysis (I) Simplifying the model: Neglect RR F, RR F2 RR L Include RR F, RR F2 into loop AA 0 = AA 0 RR F2 RR F +RR F2 Include rr oo into load resistor RR L = RR L rr o Neglect CC ππ, rr ππ since ωωcc ππ, gg rr m at frequencies of interest ππ 20

21 Small Signal Analysis (II) Output impedance ZZ out = vv out ii oo KCL at node (): vv out sscc L + vv out RR L + ( ii oo ) gg m vv BE KVL: vv BE + vv out = AA 0 ii oo = vv out sscc L + RR L + gg m + AA 0 ZZ out = vv out ii o = gg m AA 0 DC output resistance +ss = vv out ii L vv out vv BE = vv out + AA 0 gg m AA 0 vv out CC L ggmaa 0 + AA 0 + ss2 CC L ggmaa 0 ωω pp0 CC L ggmaa + ss 0 AA + ss2 CC L 0 ωω pp0 ggmaa 0 ωω pp0 gg m AA 0 AA 0 CC L ggm Usual design: ωω pp0 AA 0 GBP of loop gg m CC L (output pole) 2

22 Logarithmic and Anti-Logarithmic Amplifiers A logarithmic (anti-logarithmic) amplifier is a non-linear circuit whose output voltage is proportional to the logarithm (exponential) of the input voltage: Logarithmic amplifier Anti-logarithmic amplifier They form the basic building blocks for various applications in electronics: Analog computations such as multiplication and division of voltages as well as computing roots and powers of voltages Compression of voltages with large dynamic range and decompression Measurement and test equipment: RMS detection, direct conversion to decibels, 22

23 Basic Principle of Logarithmic Amplifiers Most logarithmic amplifiers rely on the logarithmic relationship of the collector current II CC and base-emitter voltage VV BBBB in bipolar junction transistors: VV BE II C II S ee VV T VV T 26 mv at room temperature Assuming the op-amp to be ideal, all input current II in flows into the collector of the transistor and modulates the base-emitter voltage VV BE II in = VV VV in BE = II RR C = II S ee VV T = II S ee VV out VV T VV out = VV T ln II in II S = VV T ln VV in RR II S The output voltage must satisfy VV out = VV BE and is thus directly modulated by the input current ln VV in RR II S 26 mv Main drawback of this simple circuit: output VV out depends on the transistor saturation current II S 23

24 Logarithmic Amplifier Circuit Assuming identical transistors QQ and QQ 2 II S = II S2 = II S First stage is identical to the principle circuit seen before: II in = VV VV BE in = II RR C = II S ee VV T VV A = VV BE = VV T ln VV in RR II S ββ VV BE2 VV T ln II ref II S RR P limits current through QQ The second stage is a non-inverting amplifier with gain + RR 3 : RR 2 VV out = VV B + RR 3 = VV RR BE2 + VV A + RR 3 = VV 2 RR T ln II ref ln VV in + RR 3 2 II S RR II S VV VV T ln in + RR 3 RR II ref RR 2 RR 2 = The output is independent of the transistor saturation current II S and can be tuned by a gain + RR 3 RR 2 24

25 Basic Principle of Anti-Logarithmic Amplifiers An anti-logarithmic amplifier can be obtained from a logarithmic amplifier by interchanging the position of the resistor RR with the position of the transistor The input voltage VV in modulates II C according to the exponential relation of base-emitter voltage VV BE and collector current The output voltage VV out must satisfy VV out = II C RR and is therefore proportional to the exponential modulation of the collector current by the input voltage VV BE = VV in, VV BE II C = II S ee VV T VV out = II C RR = II S RR ee VV in VV T = II S ee VV in VV T Main drawback of this simple circuit: transistor is directly connected to the input voltage, which may result in large and destructive collector currents 25

26 Anti-Logarithmic Amplifier Circuit Input stage: VV = RR 3 RR 2 +RR 3 VV in II B RR 2 RR 3 Since II C =II ref is constant, the voltage drop II B RR 2 RR 3 represents a constant offset of VV that is usually small and neglected for simplicity VV BE II ref = II C = II S ee VV T VV BE = VV T ln II ref II S VV A = VV VV BE = VV VV T ln II ref II S RR P limits current through QQ 2 The second stage is identical to the principle anti-logarithmic amplifier seen before with input voltage VV A : VV out = II S RR ee VV A VV T = II S RR ee VV VV T +ln II ref II S = II ref RR ee VV VV T = II ref RR ee RR 3 RR2+RR3 VV in VV T 26

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