Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Transcription

1 Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto University of Toronto 1 of 60

2 Basic Building Blocks Opamps Ideal opamps usually assumed. Important non-idealities dc gain: sets the accuracy of charge transfer, hence, transfer-function accuracy. unity-gain freq, phase margin & slew-rate: sets the max clocking frequency. A general rule is that unity-gain freq should be 5 times (or more) higher than the clock-freq. dc offset: Can create dc offset at output. Circuit techniques to combat this which also reduce 1/f noise. University of Toronto 2 of 60

3 Double-Poly Capacitors metal poly1 Basic Building Blocks metal C p1 poly2 C p2 thin oxide thick oxide bottom plate C p1 C p2 (substrate - ac ground) cross-section view equivalent circuit Substantial parasitics with large bottom plate capacitance (20 percent of ) Also, metal-metal capacitors are used but have even larger parasitic capacitances. University of Toronto 3 of 60

4 Switches Symbol Basic Building Blocks φ φ n-channel v 1 v 2 v 1 v 2 p-channel φ φ φ v 1 v 2 v 1 v 2 transmission gate φ Mosfet switches are good switches. off-resistance near GΩ range on-resistance in 100Ω to 5kΩ range (depends on transistor sizing) However, have non-linear parasitic capacitances. University of Toronto 4 of 60

5 Non-Overlapping Clocks T V on V off V on V off n 2 n 1 n n + 1 n 3 2n 1 2n Basic Building Blocks t T t T 1 f s --- T Non-overlapping clocks both clocks are never on at same time Needed to ensure charge is not inadvertently lost. Integer values occur at end of. φ delay delay End of is 1/2 off integer value. University of Toronto 5 of 60

6 Switched-Capacitor Resistor Equivalent R eq V 1 V V 2 1 V 2 Q = ( V 1 V 2 ) every clock period Q x = C x V x R eq = T (1) charged to V 1 and then V 2 during each clk period. Q 1 = ( V 1 V 2 ) Find equivalent average current ( V 1 V 2 ) I avg = T where T is the clk period. (2) (3) University of Toronto 6 of 60

7 Switched-Capacitor Resistor Equivalent For equivalent resistor circuit Equating two, we have R eq V 1 V 2 I eq = R eq T = = f s (4) (5) This equivalence is useful when looking at low-freq portion of a SC-circuit. For higher frequencies, discrete-time analysis is used. University of Toronto 7 of 60

8 Resistor Equivalence Example What is the equivalent resistance of a 5 pf capacitance sampled at a clock frequency of 100kHz. Using (5), we have 1 R eq = ( ) = 2MΩ ( ) Note that a very large equivalent resistance of 2MΩ can be realized. Requires only 2 transistors, a clock and a relatively small capacitance. In a typical CMOS process, such a large resistor would normally require a huge amount of silicon area. University of Toronto 8 of 60

9 Parasitic-Sensitive Integrator v c2 ( nt) v ci () t v C cx () t 2 v co () t v c1 () t v i () n = v ci ( nt) () = v co ( nt) vo n Start by looking at an integrator which IS affected by parasitic capacitances Want to find output voltage at end of in relation to input sampled at end of. University of Toronto 9 of 60

10 Parasitic-Sensitive Integrator v ci ( nt T) v ( nt T 2) ci v C co ( nt T) 1 vco ( nt T 2) on At end of on v co ( nt T 2) = v co ( nt T) v ci ( nt T) (6) But would like to know the output at end of v co ( nt) = v co ( nt T 2) leading to v co ( nt) = v co ( nt T) v ci ( nt T) (7) (8) University of Toronto 10 of 60

11 Parasitic-Sensitive Integrator Modify above to write v o () n = v o ( n 1) v i ( n 1) (9) and taking z-transform and re-arranging, leads to Hz () V o V i = Note that gain-coefficient is determined by a ratio of two capacitance values. Ratios of capacitors can be set VERY accurately on an integrated circuit (within 0.1 percent) Leads to very accurate transfer-functions z 1 (10) University of Toronto 11 of 60

12 Typical Waveforms v ci () t t t t v cx () t t v co () t t University of Toronto 12 of 60

13 Low Frequency Behavior Equation (10) can be re-written as Hz () z / z 12 / z 12 / To find freq response, recall = z = e jωt = cos( ωt ) + jsin( ωt ) z 12 / ωt ωt = cos + j sin 2 z 12 / ωt ωt = cos j sin 2 ωt ωt cos j He ( jωt 2 sin ) = ωt j2 sin (11) (12) (13) (14) (15) University of Toronto 13 of 60

14 Low Frequency Behavior Above is exact but when ωt «1 (i.e., at low freq) He jωt ( ) jωt (16) Thus, the transfer function is same as a continuoustime integrator having a gain constant of K I C T --- (17) which is a function of the integrator capacitor ratio and clock frequency only. University of Toronto 14 of 60

15 Parasitic Capacitance Effects C p3 C p4 v i () n v o () n C p1 C p2 Accounting for parasitic capacitances, we have Hz () = + C p z 1 (18) Thus, gain coefficient is not well controlled and partially non-linear (due to being non-linear). C p1 University of Toronto 15 of 60

16 Parasitic-Insensitive Integrators v ci () t v co () t v i () n = v ci ( nt) v o () n = v co ( nt) By using 2 extra switches, integrator can be made insensitive to parasitic capacitances more accurate transfer-functions better linearity (since non-linear capacitances unimportant) University of Toronto 16 of 60

17 v ci ( nt T) + - Parasitic-Insensitive Integrators vco ( nt T) on v ci ( nt T 2) - + v co ( nt T 2) on Same analysis as before except that is switched in polarity before discharging into. Hz () V o V i = z 1 (19) A positive integrator (rather than negative as before) University of Toronto 17 of 60

18 Parasitic-Insensitive Integrators C p3 C p4 v i () n v o () n C p1 C p2 has little effect since it is connected to virtual gnd C p3 has little effect since it is driven by output C p4 has little effect since it is either connected to C p2 virtual gnd or physical gnd. University of Toronto 18 of 60

19 Parasitic-Insensitive Integrators C p1 is continuously being charged to v i () n and discharged to ground. on the fact that C p1 is also charged to v i ( n 1) does not affect charge. on C p1 is discharged through the switch attached to its node and does not affect the charge accumulating on. While the parasitic capacitances may slow down settling time behavior, they do not affect the discretetime difference equation University of Toronto 19 of 60

20 Parasitic-Insensitive Inverting Integrator v i () n V i v co ( nt T 2) = v co ( nt T) v o () n V o v co ( nt) = v co ( nt T 2) v ci ( nt) Present output depends on present input(delay-free) Hz () V o V i Delay-free integrator has negative gain while delaying integrator has positive gain. = z z 1 (20) (21) (22) University of Toronto 20 of 60

21 Signal-Flow-Graph Analysis V 1 V 2 C A V 3 V C o 3 V 1 ( 1 z 1 ) V 2 z z 1 C A V o V 3 C 3 University of Toronto 21 of 60

22 First-Order Filter V in () s V out () s Start with an active-rc structure and replace resistors with SC equivalents. Analyze using discrete-time analysis. University of Toronto 22 of 60

23 First-Order Filter C3 C A V i V o C z 1 V i V o ( 1 z 1 ) C A University of Toronto 23 of 60

24 First-Order Filter C A ( 1 z 1 )V o = C 3 V o V i ( 1 z 1 )V i (23) Hz () V o V i = z ( ) A C A z 1 C C A (24) = z C A C A C z 1 C A University of Toronto 24 of 60

25 First-Order Filter The pole of (24) is found by equating the denominator to zero z p = C A C A + C 3 (25) For positive capacitance values, this pole is restricted to the real axis between 0 and 1 circuit is always stable. The zero of (24) is found to be given by z z = (26) Also restricted to real axis between 0 and 1. University of Toronto 25 of 60

26 First-Order Filter The dc gain is found by setting z = 1 which results in H() 1 = C 3 (27) Note that in a fully-differential implementation, effective negative capacitances for, and C 3 can be achieved by simply interchanging the input wires. In this way, a zero at z = 1 could be realized by setting = 0.5 (28) University of Toronto 26 of 60

27 First-Order Example Find the capacitance values needed for a first-order SC-circuit such that its 3dB point is at 10kHz when a clock frequency of 100kHz is used. It is also desired that the filter have zero gain at 50kHz (i.e. z = 1) and the dc gain be unity. Assume = 10 pf. C A Solution Making use of the bilinear transform p = ( z 1) ( z + 1) the zero at 1 is mapped to Ω =. The frequency warping maps the -3dB frequency of 10kHz (or 0.2π rad/sample) to University of Toronto 27 of 60

28 First-Order Example 0.2π Ω = tan = in the continuous-time domain leading to the continuous-time pole,, required being p p p p = (29) (30) This pole is mapped back to given by z p 1 + p p z p = = p p Therefore, H() z is given by Hz () = kz ( + 1) z (31) (32) University of Toronto 28 of 60

29 First-Order Example where k is determined by setting the dc gain to one (i.e. H() 1 = 1) resulting Hz () = ( z + 1) z (33) or equivalently, Hz () = z z 1 (34) Equating these coefficients with those of (24) (and assuming = 10 pf) results in C A = pf = pf C 3 = pf (35) (36) (37) University of Toronto 29 of 60

30 Switch Sharing C 3 C A ) V o Share switches that are always connected to the same potentials. University of Toronto 30 of 60

31 Fully-Differential Filters Most modern SC filters are fully-differential Difference between two voltages represents signal (also balanced around a common-mode voltage). Common-mode noise is rejected. Even order distortion terms cancel v 1 v 1 nonlinear element nonlinear element v p1 = k 1 v 1 + k 2 v 1 + k 3 v 1 + k 4 v v diff = 2k 1 v 1 + 2k 3 v 1 + 2k 5 v v n1 = k 1 v 1 + k 2 v 1 k 3 v 1 + k 4 v 1 + University of Toronto 31 of 60

32 Fully-Differential Filters C 3 C A + φ 1 + V i V o φ C A φ2 C 3 University of Toronto 32 of 60

33 Fully-Differential Filters Negative continuous-time input equivalent to a negative C 3 C A + φ 1 + V i V o φ C A φ2 C 3 University of Toronto 33 of 60

34 Fully-Differential Filters Note that fully-differential version is essentially two copies of single-ended version, however... area penalty not twice. Only one opamp needed (though common-mode circuit also needed) Input and output signal swings have been doubled so that same dynamic range can be achieved with half capacitor sizes (from kt C analysis) Switches can be reduced in size since small caps used. However, there is more wiring in fully-differ version but better noise and distortion performance. University of Toronto 34 of 60

35 H a () s Low-Q Biquad Filter V out () s V in () s = k 2 s 2 + k 1 s + k o s 2 ω o s + ωo Q (38) V in () s ω o k o C A = 1 1 k 1 1 ω o V c1 () s 1 ω o Q ω o C B = 1 V out () s k 2 University of Toronto 35 of 60

36 Low-Q Biquad Filter K 4 K 6 V i K 1 V 1 φ φ2 1 K 5 V o K 2 K 3 University of Toronto 36 of 60

37 Low-Q Biquad Filter K 4 V 1 K 6 K z 1 K 2 ( 1 z 1 ) K 3 K 5 z z 1 V i V o Hz () V o V i = ( K 2 + K 3 )z 2 + ( K 1 K 5 K 2 2K 3 )z+ K ( 1 + K 6 )z 2 + ( K 4 K 5 K 6 2)z + 1 (39) University of Toronto 37 of 60

38 Low-Q Biquad Filter Design Hz () = a 2 z 2 + a 1 z+ a b 2 z 2 + b 1 z + 1 we can equate the individual coefficients of z in (39) and (40), resulting in: K 3 = a 0 K 2 = a 2 a 0 K 1 K 5 = a 0 + a 1 + a 2 K 6 = b 2 1 K 4 K 5 = b 1 + b (40) (41) (42) (43) (44) (45) A degree of freedom is available here in setting internal V 1 output University of Toronto 38 of 60

39 Low-Q Biquad Filter Design Can do proper dynamic range scaling Or let the time-constants of 2 integrators be equal by K 4 = K 5 = b 1 + b Low-Q Biquad Capacitance Ratio Comparing resistor circuit to SC circuit, we have K 4 K 5 ω o T K 6 ω o T Q However, the sampling-rate, 1 T, is typically much larger that the approximated pole-frequency,, ω o (46) (47) (48) ω o T «1 (49) University of Toronto 39 of 60

40 Low-Q Biquad Capacitance Ratio Thus, the largest capacitors determining pole positions are the integrating capacitors, and. If Q < 1, the smallest capacitors are K 4 and K 5 resulting in an approximate capacitance spread of 1 ( ω o T ). If Q > 1, then from (48) the smallest capacitor would be K 6 resulting in an approximate capacitance spread of Q ( ωo T ) can be quite large for Q» 1 University of Toronto 40 of 60

41 High-Q Biquad Filter Use a high-q biquad filter circuit when Q» 1 Q-damping done with a cap around both integrators Active-RC prototype filter 1 ω o 1 Q V in () s ω o k 1 k o ω o = 1 = 1 1 ω o V out () s k 2 University of Toronto 41 of 60

42 High-Q Biquad Filter K 4 K 6 V i V o K 1 φ2 V 1 K 5 K 2 K 3 Q-damping now performed by K 6 University of Toronto 42 of 60

43 Input Input High-Q Biquad Filter K 1 : major path for lowpass K 2 : major path for band-pass filters Input K 3 : major path for high-pass filters General transfer-function is: Hz () V o V i = K 3 z 2 + ( K 1 K 5 + K 2 K 5 2K 3 )z+ ( K 3 K 2 K 5 ) (50) z 2 + ( K 4 K 5 + K 5 K 6 2)z +( 1 K 5 K 6 ) If matched to the following general form Hz () = a 2 z 2 + a 1 z+ a z 2 + b 1 z + b 0 (51) University of Toronto 43 of 60

44 High-Q Biquad Filter K 1 K 5 = a 0 + a 1 + a 2 K 2 K 5 = a 2 a 0 K 3 = a 2 K 4 K 5 = 1 + b 0 + b 1 K 5 K 6 = 1 b 0 (52) (53) (54) (55) (56) And, as in lowpass case, can set K 4 = K 5 = 1 + b 0 + b 1 (57) As before, K 4 and K 5 approx ω o T «1 but K 6 1 Q University of Toronto 44 of 60

45 Charge Injection To reduce charge injection (thereby improving distortion), turn off certain switches first. C3 Q 6 Q 5 C A a V i Q 1 Q 2 Q 4 V o Q 3 a Advance a and a so that only their charge injection affect circuit (result is a dc offset) University of Toronto 45 of 60

46 Charge Injection Note: a connected to ground while a connected to virtual ground, therefore... can use single n-channel transistors charge injection NOT signal dependent Q CH = W LC ox V eff = W LC ox ( V GS V t ) (58) Charge related to V GS and V t and V t related to substrate-source voltage. Source of Q 3 and Q 4 remains at 0 volts amount of charge injected by Q 3, Q 4 is not signal dependent and can be considered as a dc offset. University of Toronto 46 of 60

47 Charge Injection Example Estimate dc offset due to channel-charge injection when = 0 and = C A = 10C 3 = 10 pf. Assume switches Q 3, Q 4 have V tn = 0.8V, W = 30µm, L = 0.8µm, C ox = pf µm 2, and power supplies are ±2.5V. Channel-charge of Q 3, Q 4 (when on) is Q CH3 = Q CH4 = ( 30) ( 0.8) ( ) ( ) = pc (59) dc feedback keeps virtual opamp input at zero volts. University of Toronto 47 of 60

48 Charge Injection Example Charge transfer into given by C 3 Q C3 = C 3 v out (60) We estimate half channel-charges of Q 3, Q 4 are injected to the virtual ground leading to which leads to 1 -- ( Q 2 CH3 + Q CH4 ) = Q C pc v out = = 78 mv 1 pf dc offset affected by the capacitor sizes, switch sizes and power supply voltage. (61) (62) University of Toronto 48 of 60

49 SC Gain Circuits Parallel RC R 2 K R 2 v in K vout t () = Kv in () t K v in () n K v out () n = Kv in () n University of Toronto 49 of 60

50 SC Gain Circuits Resettable Gain v in () n v out () n = vin () n v out V off time University of Toronto 50 of 60

51 SC Gain Circuits Parallel RC Gain Circuit circuit amplifies 1/f noise as well as opamp offset voltage Resettable Gain Circuit performs offset cancellation also highpass filters 1/f noise of opamp However, requires a high slew-rate from opamp V off V off - V off + - V off v in () n V + C1 - + V off - V - C2 + = v out () n vin () n University of Toronto 51 of 60

52 SC Gain Circuits Capacitive-Reset Eliminate slew problem and still cancel offset by coupling opamp s output to invertering input C 3 v in () n ( ) ( ) C 4 v out () n = v in () n is optional de-glitching capacitor C 4 University of Toronto 52 of 60

53 SC Gain Circuits Capacitive-Reset V off V off - V off + - v ( n 1 ) out - C 3 + during reset v out ( n 1) + V off during valid output v in () n V off + - C 3 = v out () n v in () n University of Toronto 53 of 60

54 SC Gain Circuits Differential Cap-Reset a C 3 a + v in + - v out = ( vin v in ) - v in φ2a C 3 a Accepts differential inputs and partially cancels switch clock-feedthrough University of Toronto 54 of 60

55 Correlated Double-Sampling (CDS) Preceeding SC gain amp is an example of CDS Minimizes errors due to opamp offset and 1/f noise When CDS used, opamps should have low thermal noise (often use n-channel input transistors) Often use CDS in only a few stages input stage for oversampling converter some stages in a filter (where low-freq gain high) Basic approach: Calibration phase: store input offset voltage Operation phase: error subtracted from signal University of Toronto 55 of 60

56 Better High-Freq CDS Amplifier v in v out C 1 C 2 ', ' used but include errors, used but here no offset errors University of Toronto 56 of 60

57 CDS Integrator ( ) v in v out ( ) C 2 sample opamp offset on ' ' placed in series with opamp to reduce error Offset errors reduced by opamp gain Can also apply this technique to gain amps University of Toronto 57 of 60

58 SC Amplitude Modulator Square wave modulate by ± 1 (i.e. V out = ± V in ) C 3 v in φ A φ B v out φ B φ A φ A = ( φ ca ) + ( φ ca ) φ B = ( φ ca ) + ( φ ca ) φ ca Makes use of cap-reset gain circuit. is the modulating signal φ ca University of Toronto 58 of 60

59 SC Full-Wave Rectifier v in Square Wave Modulator v out φ ca Use square wave modulator and comparator to make For proper operation, comparator output should changes synchronously with the sampling instances. University of Toronto 59 of 60

60 SC Peak Detector φ V DD v in v in Q 1 comp C H v out opamp Q 2 C H v out Left circuit can be fast but less accurate Right circuit is more accurate due to feedback but slower due to need for compensation (circuit might also slew so opamp s output should be clamped) University of Toronto 60 of 60