V in (min) and V in (min) = (V OH V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs


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1 ECE 642, Spring Final Exam Page FINAL EXAMINATION (ALLEN)  SOLUTION (Average Score = 9/20) Problem  (20 points  This problem is required) An openloop comparator has a gain of 0 4, a dominant pole of 0 5 radians/sec., a slew rate of 5V/µs an output swing of V. (a.) If V in = mv find the propagation delay time of this comparator (the time for the output to go halfway from one state to the other). (b.) Repeat part (a.) if V in = 0mV. (c.) Repeat part (a.) if V in = 00mV. a.) We know that the linear output voltage of a singlepole comparator can be written as, v out (t) = A(e tp )V in which can be solved for the propagation delay time as t p = τ ln 2k 2k where k = V in V in (min) V in (min) = (V OH V OL ) A = V 0 4 = 0.mV We must first determine if the comparator is linear or slewing. The maximum slope occurs at t = 0 is given as dv out (t) dt = A p V in e tp _ The comparator is not slewing t p is given as t p = τ ln 2k 2k = 05 ln = 0.53µs dv out (0) dt = A p V in = = 0 6 = V/µs b.) We see the maximum slope for the linear response is 0V/µs which means that the comparator is slewing. Slewing at a rate of 5V/µs requires 0.µs to go 0.5V. Therefore, t p = 0.00µs c.) The answer is the same as b.) namely t p = 0.00µs
2 ECE 642, Spring Final Exam Page 2 Problem 2  (20 points  This problem is optional) Assume the capacitors connected to the drains of M M2 (C C 2 ) are initially discharged. Express V out = v o2 v o as a function of the applied input, V in = v i v i2, in the M3 M4 v o v o2 time domain assuming V in is a step input. If g m = g m2 = ms, g m3 = g m4 = 00µS, C = C 2 = pf, what is the v i v i2 M M2 propagation delay time ( V out = 0.5(V OH V OL ) ) for a step input of V in = 0.0( V OH V OL )? I BIAS Smallsignal model: S03FEP2 v o C v o2 C g m v gs r ds r ds3  g m3 v gs3 g m2 v gs2 r ds2 r ds4  g m4 v gs4 S03FES2 The nodal equations corresponding two these two circuits are: g m v gs g ds v o g d3 v o sc v o g m3 v gs3 = 0 g m2 v gs2 g ds2 v o2 g d4 v o2 sc 2 v o2 g m4 v gs4 = 0 We can write that, (g ds g ds3 sc ) v o =  g m v gs g m3 v gs3 (g ds2 g ds4 sc 2 ) v o2 =  g m v gs2 g m4 v gs4 Assuming matching, we get (v o2 v o )(g ds g ds3 sc ) = g m (v gs  v gs2 ) g m3 (v gs3  v gs4 ) or (v o2 v o )(g ds g ds3 sc ) = g m (v i  v i2 ) g m3 (v o2 v o ) (v o2 v o )(g ds g ds3 sc  g m3 ) (v o2 v o )( sc  g m3 ) = g m (v i  v i2 ) g m (v o2 v o ) = V out (s) = sc  g V m3 in (s) = g m g m3 g m3 /C s  (g v in m3 /C ) s V out (s) = g m C v in k s k 2 s (g = g m m3 /C ) g m3 g m3 /C s  (g v in m3 /C ) s Solving for k k 2 gives k = (C /g m3 ) k 2 = (C /g m3 ). Thus, V out (s) = g m g m3 s  (g m3 /C )  s in If V in = 0.0( V OH V OL ), then v out (t) = g m g m3 V in [e (g m3/c )t ] or 0.5(V OH V OL ) = 0.(V OH V OL )[e 08 t p ] 5 = e 08 t p  e 08 t p = 6 t p = ln(6) = 0 8 = 9.92 ns
3 ECE 642, Spring Final Exam Page 3 Problem 3  (20 points  This problem is optional) An internallycompensated, cascode op amp is shown. (a) Derive an expression for the commonmode input range. (b) Find W /L, W 2 /L 2, W 5 /L 5, W 6 /L 6 when I BIAS is 80 A the input CMR is .25 V to 2 V. Use K' N = 0 A/V 2, K' p = 50 A/V 2 V T = 0.6 to 0.8V. (c.) Develop an expression for the smallsignal differentialvoltage gain output resistance of the cascode op amp. 40/ M2 M0 M I Bias  v in M3 M = 2.5V M6 M4 I 7 M2 M7 0/ V SS = 2.5V M4 M3 C c M8 M9 C L S03FEP3 (a.) (min) = V SS V DS7 (sat) V DS (sat) V T (max) (max) =  V SD5 (sat)  V T5 (max) V T (min) (we will ignore that M8 M4 cause a more severe upper ICM limit) ICMR = (max)  (min) ICMR = ( V SS )[V DS7 (sat)v DS (sat)v T (max)] [V SD5 (sat)v T5 (max)v T (min)] (b.) I 7 = 4 I BIAS = 20 A Using V DS (sat) = 2I K (W/L) W L = 2I K [V DS (sat)] 2gives, V DS7 (sat) = 0.9V (min) = 2.5V0.9VV DS (sat)0.8v V DS (sat) = 0.259V W = W 2 20 A = L L 2 0Æ0.2592= 2.70 (max) = 2.0V = 2.5V  V SD5 (sat)  0.6V 0.8V V SD5 (sat) = 0.3V W 5 = W 6 = 20 A L 5 L 6 50Æ0.32= 4.44 (c.) By inspection, we can write: g m4 A v = (g m r ds2 ) g m4 g ds3 g ds4 g m8 g ds8 g ds9 v out
4 ECE 642, Spring Final Exam Page 4 Problem 4  (20 points  This problem is optional) George P. Burdell has submitted the following input stage for the design challenge problem in ECE 642. Assuming that the transistor model parameters are K N =0µA/V 2, V TN = 0.7V, λ N =0.04V , K P =/V 2, V TP = 0.7V, λ P =0.05V , your job is to check this op amp out. In particular, what is the upper lower input common mode voltages, what is the minimum power supply that gives zero input common mode range, what is the smallsignal voltage gain, compare this input stage with the classical differential input stage (list advantages disadvantages). M3 22 M4 00µA 00µA M3 22 M Vout  M Vout  M M6 00 M7 M M2 M9 00 M8 M M V i 0 0 V i  V i V i  5µA 0 M0 0 5µA 0 M0 0 S03FEP4 The George P. Burdell Approach GPB Differential Input Stage: Classical Approach = V SD3 (sat) V T  V GS6 (50 A) = V SD3 (sat) V T V GS6 (sat) V T6 V icm = V SD3 (sat) V GS6 (sat) V  icm = V DS5 (sat) V GS (50 A)  V GS6 (50 A) = V DS5 (sat) V DS (sat)  V DS6 (sat) V DS (sat) = V DS6 (sat) = 2Æ50 0Æ0 = 0.30V, V DS5 (sat) = 2Æ00 0Æ0 = 0.426V, 2Æ50 V SD3 (sat) = 50Æ22 = 0.30V V icm = 0.602V  = = 0.426V Note that V DS6 = V GS6 V GS7 = = 0.27 < V DS6 (sat) so that M6 is slightly in the active region but this is not a problem. The minimum is found by letting V icm = V  icm which gives (min) =.028V V out The smallsignal voltage gain is A vd = V i  V  = g m g m2 = i g ds g ds3 g ds2 g ds4 Classical Differential Input Stage: = V SD3 (sat) V T = = 0.4V  = V DS5 (sat) V GS (50 A) =.427V (min) =.027V the smallsignal voltage gain is the same.
5 ECE 642, Spring Final Exam Page 5 Problem 4 Continued Comparison between the two approaches: Characteristic GBP Differential Amplifier Classical Differential Amplifier V icm 0.602V 0.4V V  icm 0.426V.427V (min).028v.027v P diss (360 A) (250 A) Noise Higher Lower Input Offset Voltage Larger Smaller Smallsignal gain Same Same Useable ICMR Within power supply Outside of power supply
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