# Advanced Current Mirrors and Opamps

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1 Advanced Current Mirrors and Opamps David Johns and Ken Martin slide 1 of 26

2 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias W L n W L n Q5 Q4 Q1 ( n + 1) 2 W L Q3 Q2 W L Used to increase signal swing in cascode mirror Bias drains of Q2 and Q3 close to triode region set to nominal or max value of I bias I in slide 2 of 26

3 Wide-Swing Current Mirrors Q3 and Q4 act like a single transistor 2I V eff = V eff 2 = V D2 eff 3 = µ n C ox ( W L) Q 5 has same drain current but ( n + 1) 2 times smaller V eff5 = ( n + 1)V eff Similarily V eff1 = V eff4 = nv eff V G5 = V G4 = V G1 = ( n + 1)V eff + V tn V DS2 = V DS3 = V G5 V GS1 = V G5 ( nv eff + V tn ) = V eff Puts Q2 and Q3 right at edge of triode (1) (2) (3) (4) (5) slide 3 of 26

4 Wide-Swing Current Mirrors Min allowable output voltage If n = 1 V out > V eff1 + V eff2 = ( n + 1)V eff V out > 2V eff With typical value of V eff of 0.2 V, wide-swing mirror can operate down to 0.4 V Analyzed with I bias = I in. If I in varies, setting I bias to max I in will ensure transistors remain in active region Setting I bias to nominal I in will result in low output impedance during slewing (can often be tolerated) (6) (7) slide 4 of 26

5 Design Hints Usually designer would take ( W L) 5 smaller to bias Q 2 and Q 3 slightly larger than minimum To save power, bias Q 5 with lower currents while keeping same current densities (and Veff) Choose lengths of Q 2 and Q 3 close to minimum allowable gate length (since Vds are quite small) maximizes freq response Choose Q 1 and Q 4 to have longer gate lengths since Q 1 often has larger voltages ( perhaps twice minimum allowable gate length) Reduces short-channel effects slide 5 of 26

6 Enhanced Output-Impedance Current Mirror R out Iout I in V bias A V out Q1 Q3 Q2 Use feedback to keep Vds across Q 2 stable R out g m1 r ds1 r ds1 ( 1 + A) Limited by parasitic conductance between drain and substate of Q1 (8) slide 6 of 26

7 Simplified Enhanced Output-Impedance Mirror I in I B2 I B1 I out Q4 Q1 Q6 Q3 Q5 Q2 Rather than build extra opamps, use above Feedback amplifier realized by common-source amplifier of Q 3 and current source I B1 slide 7 of 26

8 Simplified Enhanced Output-Impedance Mirror Assuming output impedance of I B1 is equal to r ds3, loop gain will be ( g m3 r ds3 ) 2, resulting in r out g m1 g m3 r ds1 r ds2 r ds Circuit consisting of Q 4,Q 5,Q 6, I in, and I B2 operates like a diode-connected transistor results in accurate matching of to I out Note that shown circuit is NOT wide-swing requires output to be + above lower supply 2V eff I in V tn (9) slide 8 of 26

9 Wide-Swing with Enhanced Output Impedance Add wide-swing to improve output voltage swing I out 4I bias 4I bias I in 7I bias = I in 70 I bias I bias 70 Q 5 Q Q 7 Q 8 Q 4 Q Q 6 Q 2 Q3 and Q7 biased at 4 times current density 2V eff Requires roughly twice power dissipation Might need local compensation capacitors slide 9 of 26

10 Folded-Cascode Opamp Q11 Q3 Q4 V B1 I bias1 Q12 Q13 Q5 Q6 V in Q1 Q2 Vout CL I bias2 V B2 Q7 Q9 Q8 Q10 slide 10 of 26

11 Folded-Cascode Opamp Compensation achieved using load capacitor As load increases, opamp slower but more stable Useful for driving capacitive loads only Large output impedance (not useful for driving resistive loads) Single-gain stage but dc gain can still be quite large (say 1,000 to 3,000) Shown design makes use of wide-swing mirrors Simplified bias circuit shown Inclusion of Q12 and Q13 for improved slew-rate slide 11 of 26

12 Folded-Cascode Opamp A V V out ( s) = = V in ( s) g Z ( s ) m1 L (10) A V = g m1 r out 1 + sr out C L (11) r out is output impedance of opamp (roughly g m r ds 2) For mid-band freq, capacitor dominates 2 A V g m sc L (12) ω t = g m C L (13) slide 12 of 26

13 Folded-Cascode Opamp Maximizing g m of input maximizes freq response (if not limited by second-poles Choose current of input stage larger than output stage (also maximizes dc gain) Might go as high as 4:1 ratio Large input gm results in better thermal noise Second poles due to nodes at sources of Q5 and Q6 Minimize areas of drains and sources at these nodes with good layout techniques For high-freq, increase current in output stage slide 13 of 26

14 Folded-Cascode Slew-Rate If Q2 turned off due to large input voltage SR = I D C L (14) But if I bias2 > I D3, drain of Q1 pulled near negative power supply Would require a long time to recover from slew-rate Include Q12 (and Q13) to clamp node closer to positive power supply Q12 (and Q13) also dynamically increase bias currents during slew-rate limiting (added benefit) They pull more current through Q11 thereby increasing bias current in Q3 and Q4 slide 14 of 26

15 Folded-Cascode Example Design Goals +-2.5V power supply and 2mW opamp with 4:1 ratio of current in input stage to output stage Set bias current in Q11 to be 1/30 of Q3 (or Q4) Channel lengths of 1.6um and max width of 300um with Veff=0.25 (except input transistors) Load cap = 10pF Circuit Design I total = 2( I D1 + I D6 ) = 24I ( B + I B ) = 10I B (15) I I B I D5 I total ( 2mW) 5V = = D6 = = = 40 µa I D3 = I D4 = 5I D5 = 200 µa (16) (17) slide 15 of 26

16 I D1 = I D2 = 4I D5 = 160 µa To find transistor sizing: W ---- L i = 2I Di µ i C ox V 2 effi rounding to nearest factor of 10 (and limiting to 300um width) results in Q 1 300/1.6 Q 6 60/1.6 Q 11 10/1.6 Q 2 300/1.6 Q 7 20/1.6 Q 12 10/1.6 Q 3 300/1.6 Q 8 20/1.6 Q 13 10/1.6 Q 4 300/1.6 Q 9 20/1.6 Q 5 60/1.6 Q 10 20/1.6 Widths of Q 12 and Q 13 were somewhat arbitrarily chosen to equal the width of Q 11 Transconductance of input transistors (18) (19) slide 16 of 26

17 g m1 = 2 ID1 µ n C ox ( W L) 1 = 2.4 ma/v (20) Unity-gain frequency ω t g m1 = = rad/s f t C L Slew rate without clamp transistors 8 = 38 MHz (21) Slew rate with clamp transistors I D12 SR I D4 = = 20 V/µs C L + I D3 = I bias2 = 320 µa I D3 = 30I D11 I D11 = 6.6 µa + I D12 (22) (23) (24) (25) slide 17 of 26

18 Solving above results in which implies leading to slew-rate I D11 = µa I D3 = I D4 = 30I D11 = 0.32 ma (26) (27) SR I D4 = = 32 V/µs C L (28) More importantly, time to recover from slew-rate limiting is decreased. slide 18 of 26

19 Linear Settling Time Time constant for linear settling time equals inverse of closed-loop 3dB freq, where ω 3dB = ω 3dB βω t where β is feedback factor and ω t is unity-gain freq of amplifier (not including feedback factor) For 2-stage opamp, ω t is relatively independent of load capacitance This is NOT the case where load capacitor is compensation capacitor (folded-cascode and currentmirror opamps) Need to find equivalent load capacitance (29) slide 19 of 26

20 Linear Settling Time C 2 C 1 V in C p C load C C β 1 [ sc ( 1 + C p )] = = 1 [ sc ( 1 + C p )] + 1 ( sc 2 ) C C L C C C 2 ( C 1 + C p ) = + load C 1 + C p + C 2 C C 1 + C p + C 2 (30) (31) slide 20 of 26

21 Linear Settling Time Example Given C 1 = C 2 = C C = C load = 5pFand C p = 0.46 pf, find settling time for 0.1 percent accuracy (i.e. 7 τ) for the current-mirror opamp Solution: Equivalent load capacitance 5( ) C L = = pf which results in a unity gain freq of ω t Kg m1 C L ma/v = = = rad/s pf (32) (33) slide 21 of 26

22 Linear Settling Time Example Feedback factor given by 5 β = = causing a first-order time constant 1 τ = = 7.8 ns βω t For 0.1 percent accuracy, we need a linear settling time of 7τ or 54 ns. (34) (35) This does not account for any slew-rate limiting time. slide 22 of 26

23 Advantages Fully Differential Opamps Use of fully-differential signals helps to reject common-mode noise and even-order linearities rejection only partial due to non-linearities but much better than single-ended designs Fast since no extra current mirror needed Disadvantages Requires common-mode feedback (CMFB) circuitry sets average output voltage level, should be fast adds some capacitance to output stage might limit output signal swing Negative going single-ended slew-rate slower since set by bias current not dynamic slide 23 of 26

24 Fully Differential Folded-Cascode Opamp Q3 V B1 Q4 Q11 Q12 V B2 Q5 Q6 Q1 Q2 V out V in I bias V B3 CMFB circuit Q8 Q10 Q7 Q9 V cntrl slide 24 of 26

25 Common-Mode Feedback Circuits Q1 I B I B/2 + I B/2 I I I B Q4 V out+ Q2 Q3 V out V cntrl I B/2 I I B Q5 I B/2 + I I B Balanced signal on Vout does not affect Vcntrl Does not depend on small-signal analysis Q6 slide 25 of 26

26 Common-Mode Feedback Circuits V out+ V out φ 1 φ 2 φ 2 φ 1 φ 1 C S C C C C φ 2 φ 2 C S φ 1 V bias V cntrl Useful for switched-capacitor circuits Caps Cs set nominal dc bias at bottom of Cc Large output signal swing allowed slide 26 of 26

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