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1 Serial : LS_B_EC_Network Theory_0098 CLASS TEST (GATE) Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubanewar Kolkata Patna Web: info@madeeay.in Ph: CLASS TEST 08-9 ELECTRONCS ENGNEERNG Subject : Network Theory Date of tet : 0/09/08 Anwer Key. (c) 7. (d) 3. (b) 9. (a) 5. (d). (d) 8. (c) 4. (d) 0. (b) 6. (b) 3. (b) 9. (b) 5. (a). (c) 7. (b) 4. (b) 0. (d) 6. (c). (c) 8. (b) 5. (d). (b) 7. (d) 3. (a) 9. (c) 6. (b). (b) 8. (d) 4. (c) 30. (b)

2 8 Electronic Engineering Detailed Explanation. (c) deal voltage ource ha zero internal reitance, Time contant τ RC 0 Hence capacitor will charge intantaneouly.. (d) The time contant τ R eq C eq Here, R eq R R /3 R and C eq C C 3C τ 3 3 R C RC 3. (b) n order to inject the 00 C charge to the 50 ource the current in the loop mut be anticlockwie 30 i 0 Ω 50 Q 00 i.67 A t 60 applying KL in the circuit 0i (0 i 0) (b) For power tranfer to be maximum R L R Th Redrawing the circuit R Th OC OC - open circuit voltage SC 60 6 Ω v x Ω vx a Open Circuit b OC v x Applying KL in loop 6 v x (i) v x...(ii) Solving thee, 5 A

3 OC v x 5 0 SC 60 0 A 6 R Th 0 R L Ω 0 CT-08 EC Network Theory 6 Ω 60 Ω a b SC 9 Short circuit 5. (d) Since the d and e column are identical. Hence d and e branch are parallel. 6. (b) On careful obervation, we find ; ; Uing the ame logic, we try to work out the miing number a and To verify the correctne, we check (d) Z() ( R L) C ( R L) C R L R L LC RC C LC RC 0 for pole to be real (RC) 4LC 0 RC LC R L C 8. (c) Two Port Network 4 Ω overall Z 0 4 putting Z Ω 4 3

4 0 Electronic Engineering 9. (b) Under teady tate L 0 5 R R R C L R 0 R R Energy tored in capacitor Energy tored in inductor C c L L 6 0R R R or R 5 Ω 5A Ω C L 0. (d) Given circuit, Ω Ω 0 i 30 8 Ω 4 A 3 0 By applying nodal analyi, () and () Subtituting () in () 3( 4) Current upplied by dependent ource i A Power delivered 3 0 i 30 (3 6) (4) 7 W

5 CT-08 EC Network Theory. (b) at reonance, X L X C Current through L i identical to current through C. X π fl L L C where f π LC C π L L π LC A. (b) Conidering one unit /...(i) and ( ) from equation (i) and (ii)...(ii) and Two uch unit are connected in cacade (b) For t < 0 0 Ω A 0 Ω k k L L 0 6H H A

6 Electronic Engineering L 0.5 A 8 At t 0 L A 8 Applying KL (0 5) 0.5 L L 3.75 olt 5 Ω 0 Ω L 0.5 A 4. (d) Power conumed in 5 Ω reitor 0 W P 0 R 5 A Total power conumed in reitor 5 Ω and 0 Ω ( ) [5 0] 30 W Total power upplied by ource 50 50W Power factor Since it i an R-L circuit, the power factor i lagging. 5. (a) oc 0 Ω 0 Ω 6 0 Ω 0 oc c 0 A 0 R Th oc 0 0 Ω c 0 Ω 0 c P max oc ( ) 0 4R 5 W 4 0 Th

7 CT-08 EC Network Theory 3 6. (c) Z 0 Redrawing the circuit and open circuiting the port Z 0 Ω 0 0 Ω 0 Ω 5 Ω 0 7. (d) From the firt circuit i 3 6 3i...() From the econd circuit, Power acro 0 Ω 90 W. i L 0 90 i L 9 3A. a.5 Ω 5 Ω Ω 0 3 Ω 6 Ω 6 a 5 Ω 0 Ω i i 6 a i L i 6a i L 3 6 A Hence 6 a 6 a From the figure, a i i So, i A From equation () 0 3i (d) Redrawing the circuit R 3 x g R m x a 0 R 0 R b R Th : x 0 0 g m x R 0 R R R 0 3

8 4 Electronic Engineering ( m ) ( ) 0 g R 0 R R R 3 0 R Th 0 0 R3( R R) ( g R ) R ( R R ) m 3 9. (a) From the given figure. Z Z Z Z Z Z The above equation can be rearranged a (Z Z ) Z ( )... (i) (Z Z ) (Z Z ) Z ( )... (ii) generator equivalent i Z Z Z Z ( ) Z Z Z 0. (b) Redrawing the circuit 50 Ω ( b ) 0 Ω 0 Ω b a 4 b Ω (0. a ) A 0. a Applying KL 50 a 40( 0. a ) (i) ( b ) 0 a... (ii) a 0 b 4 b 0... (iii) By equation (i), (ii) and (iii) b 0.96 A.. (c) Putting 0 Applying KCL at node A h 0

9 CT-08 EC Network Theory Ω 0 Ω A 50 Ω 00 Ω x 0 x x x x 0 0 x x x x h 85 Ω. (c) 0...(i) 0....(ii) For maximum power tranfer 0 Ω Port Network Z Th From equation (i), (ii) and (iii), we get R L Z Th 0...(iii) Z Th 7.5 Ω 0 Ω 00 Port Network OC

10 6 Electronic Engineering (iv) when 0...(v) OC 5 Maximum power tranferred OC 4Z Th (5) W. 3. (a) For t 0 Energy tored at t 0 i 0 A 0 40 i L (0 ) i L (0 ) A 0 0 Ω 0 H 40 Ω J L i ( ) At t 0 (0 R) L 0 R 40 Ω τ L R eq 0 0.ec ( ) R Ω 0 Ω A 40 Ω i(t) e 0t A At t t 90% energy i diipated remaining energy 0 0 Joule 00 ( ) L i t 5 i (t ) i (t ) i(t ) 0t e 0.4 t 0.5 ec 5. mec 4. (c) Q(0 ) C(0 ) (0 ) Q(0 ) 90 µ 3 C 30 µ (8 8)k 9 ( ) 8 8 k 8

11 CT-08 EC Network Theory 7 kω 8 kω 9 u( t) 8 kω τ t / oltage acro capacitor ( ) (0 ) ( ) e ( ) τ C(k (8 8)k) τ (t) ec t e (0 mec) e 3.85 Q(0 mec) µ 5.5 mc 5. (d) h h h h (i) 0 A, A, 4.5,.5 h h (ii) 4 A, 0, 6,.5 h h 0 h h 0.5 h h 6 h h Ω h parameter matrix i

12 8 Electronic Engineering 6. (b) For t < 0: 6 Ω 60 6 Ω 40 6 Ω 0 / H 0 i(t) v(t) The equivalent circuit i R eq 6 (6 6) 6 6 4Ω R eq 60 R eq 4 Ω / H i(t) 0 i(0) A Hence i(0 ) 0 A. (0 ) 40. For t > 0: 6 Ω 6 Ω 6 Ω i(t) H 0 8 F The equivalent circuit i 4 Ω i(t) H i (t) 40 8 F 0 Applying Laplace tranform to the above circuit () 4 () () 5 0

13 CT-08 EC Network Theory () () Ω () () (b) 40 0 () 8 6 (40 0 ) () () 8 6 () 0 ( 4) By applying invere Laplace tranform i(t) 0e 4t A 0 Ω 0 Ω A 0 0 Ω 0 Ω 0 Ω 0 Ω B R in Th : R in 0 0 (0 0 0) 0 R in 7.5 Ω 0 A A 7.5 Th AB R Th : 0 0 Ω 0 Ω 0 Ω 0 Ω R Ω 0 Ω 0 Ω R th

14 0 Electronic Engineering R Th Ω R 0 Ω R th 0 Ω Maximum power can be tranferred 8. (b) H() Th mw 4R 4 80 Th Y () X () x( t) inωt / Ω Ω Ω yt () Ain( ωt 45 ) () X () Y() () ( Ω) () Y () X () ( ) X( ) () 4 H() H(jω) jω j ω H(jω) j jω ω

15 CT-08 EC Network Theory j ω ω H(jω) tan ω ω given, H( jω) 45 ω ω tan () tan ω ω ω ω ω ω ω ω 0 ω ± 4() ± 9 ± 3 4 ω 4 4 rad/ec ω i alway poitive. 9. (c) For erie reonance X L X C X C X L j Ω j j8 jm X L j0 jk 6 X L j0 j8k j j0 j8k j j8k ( M k LL) k (b) Conidering only DC ource 0 i R () t Ω i R (t) 0 5 A Conidering only AC ource

16 Electronic Engineering H j Ω / j Ω i i R () t Ω 5 cot i R (t) i(t) i(t) j i() t j 5cot A j ( j ) 5cot 5cot j 4 j( j) 0.5j 0.5j j 4 4 A i(t) A 8( j j) 0.5j j 0.5j A 0.5j i R (t) 5 0 j A 0.5 j ( j) (.8) i R (t) A when both the ource are acting imultaneouly, i R (t) co (t 8.44 ) A

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