# CHAPTER 7 - CD COMPANION

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1 Chapter 7 - CD companion 1 CHAPTER 7 - CD COMPANION CD-7.2 Biasing of Single-Stage Amplifiers This companion section to the text contains detailed treatments of biasing circuits for both bipolar and field-effect transistors. CD BJT Amplifiers; Detailed Treatment In order to perform a detailed comparison of different biasing schemes it is useful to have a quantitative way of comparing their stability. So, before proceeding with any circuit analysis we take a short break to present a tool that is very useful in many different situations; the normalized small-signal sensitivity. ASIDE CD-A7.1 Normalized Small-Signal Sensitivity There are many occasions where we are interested in determining how sensitive some parameter is to one of the variables that determines it. For example, consider the diode circuit shown in Figure CD-A I 1 R V 1 IN I D I2 R Figure CD-A7-1 A circuit containing a diode. Assume that V IN = 10 V. We can solve for the currents in this circuit using the large-signal DC equivalent circuit of Figure CD-A7-2.

2 Chapter 7 - CD companion 2 + I 1 V R 1 IN I2 R V D - Figure CD-A7-2 The large-signal DC equivalent circuit for Figure CD-A7-1. As usual, we approximate V D as 0.7 V. For example, the current I 1 is given by I 1 = V IN V D R 1 (CD-A7.1) It is reasonable to ask just how sensitive this solution is to the value of the diode voltage V D. If the answer is too sensitive, then our crude approximation for V D is probably not reasonable and our solution is not likely to be correct and, more significantly, if V D changes with temperature, or from one circuit to the next, the value of I 1 will also change. Therefore, we want to find how much how much I 1 will change as V D is changed. It is most useful to examine the fractional change in I 1 (i.e., I 1 I 1 ) versus the fractional change in V D that produced it ( V D V D ). If we take the limit as the changes go to zero, we get the normalized small-signal sensitivity of I 1 with respect to V D ; I S 1 VD = lim V D 0 I 1 I 1 = V D di 1. V D V D I 1 dv D (CD-A7.2) The normalized small-signal sensitivity is also called the classical sensitivity. Evaluating this sensitivity for our example using (CD-A7.1) we get I S 1 VD = V D I 1 d dv D V IN V D R 1 = V D I 1 R 1 where we have assumed that V IN and R 1 are not functions of V D. Plugging in the numbers for the current example reveals that S VD = Therefore, if we increase V D by 1%, we expect a fractional change in I 1 of about %. The minus sign on the sensitivity indicates that I 1 will decrease if V D is increased. We must be careful in applying this sensitivity however. Since we use a derivative in the definition, the answer will only be accurate for small (differential) changes I 1

3 Chapter 7 - CD companion 3 about the nominal point; that is why we call it the small-signal sensitivity. For accurate results with large deviations we must use differences rather than differentials. For example, going back to (CD-A7.1), we find that the nominal value of I 1 (i.e., assuming V D = 0.7 V) is 10 ma. Now suppose that V D changes by 0.1 V. We can solve for the difference between I 1 calculated when V D = 0.7 and I 1 calculated when V D = 0.8 I 1 = I 1 (V D = 0.8) I 1 (V D = 0.7) = = 0.1. = ma Using the small-signal sensitivity we obtain I ( V D V D )I 1 and, plugging in we find I 1 = ma again. In this case, the answer is the same, but only because the function is linear. In general, we can define the normalized small-signal sensitivity of a variable Y with respect to changes in X by S X Y X Y dy dx. If Y is a function of two different parameters X and Z, we can write dy = dy dy dx + dx dz dz (CD-A7.3) or, by normalizing the differentials we get dy Y = X Y dy dx dx X + Z Y dy dz dz Z, so that we can write the resulting normalized change in Y in terms of the sensitivities as dy Y = S X Y dx X + S Z Y dz Z. (CD-A7.4) This equation can be generalized to more than two parameters and allows us to estimate the fractional change in Y due to simultaneous small changes in the different parameters that determine Y. We are now ready to start our detailed comparison of BJT biasing circuits. Let's begin by considering the common-emitter biasing scheme shown in Figure CD-7-

4 Chapter 7 - CD companion 4 1 where reasonable values have been chosen for the elements in order to illustrate the operation of the circuit. Assume that β = 50 for the transistor. The coupling capacitors would be chosen to be large enough that their impedances are negligible at the signal frequencies of interest as before. 12 V C IN R B R C 200 k 2 k C OUT v out v in Figure CD-7-1 A bias circuit for npn transistors. We can solve for the currents and voltages in this circuit by using our large-signal DC model of the BJT. The resulting equivalent circuit is shown in Figure CD V R B 200 k I C R C 2 k V B V C I B V - βi B Figure CD-7-2 The large-signal DC equivalent circuit for the circuit in Figure CD-7-1. The base current of the transistor is given by I B = V CC V BE = = 56 µa. (CD-7.1) R B 200 k

5 Chapter 7 - CD companion 5 The collector current is therefore I C = βi B = 2.8 ma and the collector voltage is V C =V CC -I C R C = 6.3 V. We can now see that the transistor is in fact in the forward active region of operation as assumed. Some useful insight will be gained if we notice that we could also have solved for the collector voltage and current of the circuit in Figure CD-7-1 graphically by writing the loop equation in the collector circuit, V CC = V CE + I C R C, (CD-7.2) which leads to I C = V CC V CE R C. (CD-7.3) We can use (CD-7.3) to plot a line on the collector characteristics of the transistor as shown in Figure CD-7-3. Because this line describes the constraint placed on possible values of I C and V CE by the components external to the transistor, and because these components can be thought of as the load connected to the transistor (assuming the collector is the output), we call the line described by (CD- 7.3) the load line for this circuit as introduced in Chapter Six. Using the load line shown in Figure CD-7-3, and using the curve that approximately corresponds to the base current found in (CD-7.1) (blue in the figure), we find the Q point as being the intersection of the load line and the appropriate transistor curve. As noted in Chapter Six, this method of solution is not typically used, but it is still educational to consider this view while learning about biasing.

6 Chapter 7 - CD companion 6 6 I C (ma) 5 I B = 80 A 4 3 Q Q 60 A A 20 A 25 ßC 75 ßC V CE (V) Figure CD-7-3 Typical low-power npn transistor output characteristic at two different temperatures, with the DC load line for Figure CD-7-2. Using Figure CD-7-3, and the base current given by (CD-7.1), we can see what happens when the temperature of this circuit is increased from 25 ûc to 75 ûc. The value of V BE will decrease by about 100 mv for this 50 ûc rise in temperature, but this will have a negligible effect on I B. The β F of the transistor increases quite rapidly with temperature however, so using the transistor curve for 75 ûc indicates that the new Q point (labeled Q ) is significantly different from the original Q point. This shift in the Q point with temperature is undesirable. Although it is certainly simple, the biasing scheme of Figure CD-7-1 is usually not satisfactory because the Q point is far too sensitive to the beta of the transistor. The following example will illustrate this point. Example CD-7.1 Problem: Solution: Find the Q point of the circuit in Figure CD-7-1 if the transistor used has (a) β = 25, and (b) β = 100.

7 Chapter 7 - CD companion 7 Equation (CD-7.1) shows that the base current of this circuit will not change with changes in β, therefore the base current stays fixed at 56 µa. The collector current is I C = βi B, so for part (a) we get I C = 1.4 ma, which then leads to V CE = 9.2 V. In this case the transistor is still forward active, although the Q point is substantially different than we found with β = 50. For part (b) we get I C = 5.6 ma, which then leads to V CE = 0.8 V. This bias point is getting close to saturating the transistor! This large a variation in the Q point is usually unacceptable. The sensitivity of the Q point to changes in β can also be examined by calculating I the sensitivity of I C with respect to β, S C β. For this circuit the base current is not a function of β, so we have I C = βi B and, using the definition of the sensitivity from (CD-A7.3), we get S β I C = β I C di C dβ = β I C I B =1, (CD-7.4) which makes sense since the collector current is proportional to β. In other words, a 1% change in β causes a 1% change in I C. Since large variations in β can be expected, this sensitivity is unacceptably large. Using (CD-7.4) to predict the results of Example CD-7.1 works quite well, but remember that the sensitivity will not, in general, give accurate results for large deviations; it is only accurate in this case because the function being differentiated is linear. It is also worthwhile to derive the sensitivity of I C with respect to V BE. For this circuit, V BE only affects the base current as shown by (CD-7.1) and because V BE is much less than V CC, the effect will be minor. Using the fact that I C = βi B along with (CD-7.1) and the definition of sensitivity, (CD-A7.3), we get I S C VBE = V BE I C d dv BE ( ) β V CC V BE = βv BE R B I C R B = V BE V = BE, I B R B V CC V BE (CD-7.5)

8 Chapter 7 - CD companion 8 which evaluates to 0.062, a very good value. Since the collector current is directly proportional to the base current, the normalized sensitivities of I B and I C are the I same, so we could have derived (CD-7.5) by finding S B VBE directly. We will soon see that other bias configurations are less sensitive to device parameters than the circuit considered thus far. In order to have some feel for the magnitude of the variations seen in the large-signal DC model parameters of BJT s, the following aside presents typical values. ASIDE CD-A7.2 Device-to-Device Variation in BJT Large-Signal DC Model Parameters The large-signal DC model parameters for transistors are variable from one device to the next. How predictable a given parameter is depends on the parameter and whether we are considering discrete or integrated transistors. Discrete transistors are packaged individually and may have been fabricated at completely different times by different companies. Therefore, no assumptions can be made about any two transistors matching; the safest assumption is that they are both at opposite extremes of the allowable specifications (highly unlikely, but definitely leads to a safe design). The data sheets for individual transistors will sometimes list both minimum and maximum values, but usually only one or the other is given. For example, it is common to only list the minimum and typical values for β, the assumption being that no one will complain if it turns out to be much larger than typical. Only specifying one end of the range does not usually pose a problem since β ceases to have any noticeable effect on the operation of a circuit once it gets large enough. Data sheets do not specify I S even though it is a parameter of fundamental importance (and is needed for the SPICE model). The value for I S must be deduced from values given for V BE at different collector currents. Table CD-A7.1 shows typical ranges for the different parameters of interest for a given type of discrete transistor, the variations are much larger if different types of transistors are compared. For integrated transistors, the variations from one IC to the next will be just as large as for discrete transistors, but the matching from one transistor to another on the same IC is much better since the devices are fabricated at the same time and are physically close to each other. The closer the transistors are to each other the better the matching will be. Larger area transistors also match better, and transistors made as a parallel combination of devices laid out symmetrically about a common center point also match better (this is called

9 Chapter 7 - CD companion 9 common-centroid layout [7.1]). It is quite possible for two large BJT's to have V BE s that match to within less than 100 µv. The matching listed in the table is only meant to be typical for medium size BJT's that are next to each other. The matching is different for each process and these numbers must be taken as only a rough indication of typical values. As a final note, there are packaged arrays of transistors available that provide two or more transistors that match very well (e.g., LM394). Also, how well the temperatures of two transistors match is often of importance in design (see Aside CD-A7.3), and the thermal matching of discrete transistors is very poor unless they are mounted on the same heat sink. Even when mounted on the same heat sink however, the thermal matching of discrete transistors will never be as good as that achievable with integrated transistors. Parameter Typical range for 2N2222 Typical matching for medium-size npn s adjacent to each other on an IC Minimum Maximum β ± % V BE a fixed I C ) 0.64 V 0.76 V ± 2 mv I S 2.0x10-15 A 2.0x10-13 A ± 10 % Table CD-A7.1 Matching data for discrete npn BJT s (2N2222 type) and typical medium-size integrated npn transistors that are adjacent to each other. This table is reproduced in the printed text as Table 7.2. We next investigate how typical BJT model parameters vary with temperature. The following aside will provide some typical values as well as providing a definition of the temperature coefficient (TC). The TC is a commonly specified parameter for both circuit specifications and individual component specifications. ASIDE CD-A7.3 Temperature Coefficients and the Variation of Large- Signal DC BJT Model Parameters with Temperature All of the terms shown in our standard large-signal DC model of a forward-active BJT are temperature dependent. The value of V BE decreases by approximately 2 mv for every 1 ûc rise in temperature if the current is held constant, while β roughly doubles for an 80 ûc increase above room temperature. Because α is

10 Chapter 7 - CD companion 10 equal to β/(β+1), it is not nearly as sensitive to temperature as β is. For example, with a nominal β of 100, if β doubles, α increases from to In addition to these parameters of the forward active model, the collector leakage current is strongly temperature dependent (as are most leakage currents); I CO approximately doubles for every 6 ûc rise in temperature for silicon transistors. It is common to quote temperature sensitivities in terms of a temperature coefficient, or TC. The TC of a parameter X is defined by TC X 1 X dx dt = 1 T S T X. (CD-A7.5) Examination of (CD-A7.5) reveals that a TC is normalized with respect to the parameter of interest, but it is not normalized with respect to temperature. Since a TC is normalized with respect to the parameter, the proper units are ûc -1 and a common choice is to use parts-per-million per degree Celsius (ppm/ûc), where 10-6 ûc -1 = 1 ppm/ûc. Depending on the parameter however, it is also common to just use the derivative in (CD-A7.5) and not normalize the value at all. This is still called a TC and is only distinguishable from the TC defined above by the units; since no normalization has taken place, the units will be something like mv/ûc or ma/ûc. Table CD-A7.2 summarizes the BJT parameters, their typical values at room temperature, the equations for how they vary with temperature, and their temperature coefficients (quoted in the most common units). Parameter Typical value at 25 ûc Variation with Temperature Typical Temperature Coefficient at 25 ûc I CO 1 na I CO (T) = I CO (25) 2 ( T 25) 6 A 116 pa/ûc β 100 β(t) = β(25) [ 1+ ( T 25) 80] 12,500 ppm/ûc I S V BE (I C constant) 1x10-15 A ( T ) I T = I 1.7x10-16 A/ûC S( ) S(25) 10 A 0.7 V V BE (T) = 0.7 (T 25)0.002 V -2 mv/ûc Table CD-A7.2 Variation of large-signal DC BJT parameters with temperature. All temperatures are in ûc. For pnp transistors V BE should be replaced by V EB. This table is reproduced in the printed text as Table 7.3.

11 Chapter 7 - CD companion 11 Now that we have some information about how the parameters of the large-signal DC model for a BJT will change with temperature, we can use this information to predict how sensitive our circuit is to changes in temperature. Starting from (CD- 7.1) and allowing for variation in everything except the power supply, we can show that S T I C = T 1 dβ β dt 1 V CC V BE dv BE ( ) dt 1 R B dr B dt. (CD-7.6) Assuming for now that the resistor does not change with temperature, and using the data presented in Aside CD-A7.3, we get I S C T = T = T. (CD-7.7) It would be common to express (CD-7.7) as a temperature coefficient; TC IC = 1 T S T I C = ÞC 1 = 12,300 ppm /ÞC. (CD-7.8) This temperature coefficient is quite large and is almost entirely due to the variation in β. As a final note on the sensitivity of circuits to component variations, we point out that the resistors, capacitors, inductors, and other non solid-state devices also vary from device to device and with temperature. The typical variations seen are presented in Aside A7.4 in the text. Although the values of passive components do vary, resistors can be purchased with very small tolerances and very low temperature coefficients, so the final stability of resistive bias circuits is limited by the active components rather than the passive ones. Let us now return to the circuit of Figure CD-7-1 and consider how to calculate the resistor values to yield a desired operating point. The value we choose for R B will determine the base current and, therefore, the collector current as well. The value chosen for R C will then determine the collector voltage. So, given a desired operating point, one first uses (CD-7.1) to determine the required value of R B, and then uses (CD-7.3) to find the required value of R C.

12 Chapter 7 - CD companion 12 Example CD-7.2 Problem: Solution: Find the values for R B and R C required to set I C to 2 ma and V CE to 6 V in the circuit of Figure CD-7-1. Assume the transistor has a nominal beta of 100. The base current needs to be set to 0.002/100 = 20 µa. From (CD-7.1) we get R B = V CC V BE I B, (CD-7.9) which leads to R B = 565 k. Then, in order to set V CE to 6 V we use (CD-7.3) to get which leads to R C =3 k. R C = V CC V CE I C, (CD-7.10) We are now ready to move on to consider better biasing arrangements for the BJT. One circuit that has a reduced sensitivity to changes in β is shown in Figure CD-7-4. Although it is less sensitive to β, the circuit s sensitivity to changes in V BE is the same as the previous circuit. To see why this circuit is less sensitive to the value of β, consider what happens if β changes. If the value of β increases (e.g., from putting in a different transistor), then the collector current will increase. The increase in collector current causes a decrease in the collector voltage, which tends to decrease the base current and, therefore, the collector current. In other words, the circuit has negative feedback that opposes the original change.

13 Chapter 7 - CD companion V R f R C 1.4 k 86 k Figure CD-7-4 An improved biasing arrangement. The circuit in Figure CD-7-4 is more difficult to analyze than the topology shown in Figure CD-7-1 because the circuit is no longer unilateral. In other words, we cannot write an equation for I B that is independent of I C ; the feedback resistor R f connects the input and output directly. We start our analysis by assuming that the transistor is forward active and replacing it by the appropriate large-signal DC model as shown in Figure CD V i R C RC 1.4 k R f I B V - 86 k βi B Figure CD-7-5 The large-signal DC equivalent circuit for Figure CD-7-4. Using KCL at the collector node we see that I RC = ( β +1)I B. (CD-7.11)

14 Chapter 7 - CD companion 14 We can now write KVL from the positive supply to ground using I B as the only variable; V CC ( β +1)I B R C I B R f V BE = 0. (CD-7.12) Solving this equation for I B and plugging in the values (assume β = 100) leads to I B = V CC V BE = = 50 µa. (CD-7.13) R f + ( β +1)R C 86 k + (101)1.4 k The resulting collector current is 5 ma and the collector voltage is then 5 volts. We can now check and find that the transistor is in fact forward active as assumed. Exercise CD-7.1 Find the bias point for the circuit shown in Figure CD-7-6. Assume that β F = V R f R C 1.4 k 56 k Figure CD-7-6 Circuit for Exercise CD-7.1 Exercise CD-7.2 Find the sensitivities of I C with respect to β and V BE for the circuit in Figure CD- 7-4 and compare them with the values found for the circuit of Figure CD-7-1; see (CD-7.4) and (CD-7.5).

15 Chapter 7 - CD companion 15 At this point we are led to reconsider the circuit from Figure 7-46 in the text. The large-signal DC equivalent was given in Figure 7-47 and is repeated in Figure CD-7-7 for convenience. V CC R C R BB I B V BB V - βi B R E IE Figure CD-7-7 The large-signal DC equivalent circuit for the circuit in Figure We now repeat a couple of the equations derived earlier so that we can consider them further. Writing KVL around the base-emitter loop in Figure CD-7-7 yields V BB I B R BB 0.7 I E R E = 0 (CD-7.14) and replacing I E with (β +1)I B yields V BB I B R BB 0.7 ( β +1)I B R E = 0 (CD-7.15) which can be solved directly for I B. Notice that (CD-7.15) illustrates the principle of impedance reflection as explained in Aside A7.1 in the text. Now let s examine the stability of the bias point for this circuit using normalized small-signal sensitivities. Solving (CD-7.15) for I B and multiplying the result by β we can write V I C = β BB V BE, (CD-7.16) R BB + ( β +1)R E

16 Chapter 7 - CD companion 16 which allows us to find the sensitivity of I C to both β and V BE. Applying the definition to find the sensitivity with respect to β is complicated by the fact that V BE is itself a function of β (i.e., V BE = V T ln(i C /I S ) = V T ln(βi B /I S )). If we tried to include this variation in V BE (as we should to evaluate the true derivative) we would be in trouble since V BE depends on I B, which in turn depends on V BE. The equation is a transcendental equation and we cannot derive a closed-form equation for I B, which means we can t perform the required differentiation. Nevertheless, it is not unreasonable to assume that the small change in V BE can be ignored while finding the sensitivity of I C with respect to β. Holding V BE constant yields I S C β = β ( β R BB + ( β +1)R E) 0 ( V BB V BE )R E I C R BB + ( β +1)R E which can be simplified to ( ) 2 + S β I C = V BB V BE R BB + β +1 ( )R E, (CD-7.17) R BB + R E. (CD-7.18) R BB + ( β +1)R E Using the component values from Example 7.10 in the text (V CC = 20 V, R C =5 I kω, R E =1 kω, R 1 = 20 kω, R 2 =3 kω, V BE = 0.7 and β = 100) gives S C β = 0.035, which is less than one-tenth the value for the circuit in Figure CD-7-4 (see Exercise CD-7.2). Using (CD-7.16) again, we find the sensitivity with respect to changes in V BE is given by I S C VBE = V BE I C di C dv BE = V BE I C β R BB + ( β +1)R E = V BE V BB V BE, (CD-7.19) which is the same form as was found for the previous two circuits except that we have V BB instead of V CC in the denominator. Since the value of V BB is usually less than half the value of V CC this circuit is actually slightly more sensitive to changes in V BE than the previous circuits. Using the component values from Example 7.10 I gives S C VBE = which is larger than was found for the numerical example in Exercise CD-7.2, the difference is due to the difference between V BB and V CC as noted above. Using (CD-A7.4) we can now estimate the total fractional change in I C given simultaneous variations in both β and V BE ;

17 Chapter 7 - CD companion 17 I C I S C β I I β C β + S C VBE V BE V BE. (CD-7.20) The changes examined in Example 7.11 (V BE = 0.6 V and β = 50) lead to I C I I C S C 50 β 100 S I C 0.1 V BE ( 0.5)+ 0.37( 0.143) [ ] ma = ma (CD-7.21) which leads to I C = 1.90 ma. The correct value is I C = 1.93 ma, or I C = 0.10 ma as can be seen by comparing Examples 7.10 and 7.11 in the text. Therefore, the small-signal sensitivities are not very accurate at predicting large changes as expected (the absolute error in I C is not large, but the error in I C is quite large as a percentage of the correct I C ). Nonetheless, they still provide us with useful quantitative comparisons between different topologies and with equations that indicate how we might reduce a given sensitivity by our choice of component values. Even though this circuit is somewhat more sensitive to changes in V BE than either of the two preceding circuits, the sensitivity with respect to changes in β is much smaller for practical values. In addition, the circuit provides more flexibility to the designer in terms of setting different characteristics of the amplifier independently. For example, the feedback resistor for the circuit of Figure CD-7-4 cannot be chosen independent of the small-signal AC gain, whereas greater freedom of choice is allowed in the circuit in Figure These issues will be clearer after you have covered small-signal AC analysis in Chapter Eight. At this point you are familiar with analyzing bias circuits for BJT amplifiers and have a basic understanding of how the resulting bias point depends on the device parameters and the topology of the biasing network. As a result of this understanding it is possible to select a bias network that will satisfy the requirements of a given application. Once the bias circuit topology is selected, the design reduces to determining the component values required to achieve the desired operating point. The desired operating point is based to a large extent on the small-signal AC performance of the amplifier and will be discussed in Chapter Eight.

18 Chapter 7 - CD companion 18 Even if we know the desired operating point and the chosen topology however, they do not uniquely determine a set of component values. It is the purpose of this section to discuss how the choice of component values affects the stability of the operating point, the power dissipation, and other factors, and then to present some reasonable guidelines and procedures for carrying out the design. The rules of thumb presented in Section in the text are derived here so that the underlying assumptions are clear. You will then be able to modify these rules as needed to better fit a given situation. We will concentrate on the circuit of Figure 7-46 since it is the most common discrete biasing circuit and because the design of the other circuits is more straightforward (because they offer fewer degrees of freedom). The large-signal DC equivalent circuit for the topology of Figure 7-46 is shown in Figure CD-7-7 and (CD-7.16) gives the collector current of the circuit. We are primarily concerned at first with choosing values for the biasing elements that will produce a collector current that is insensitive to the transistor parameters. In other words, we want the bias current to depend only on the supply voltage and the biasing resistors since these are typically more accurate and less temperature dependent than the transistor parameters. The transistor parameters we are most concerned with are β and V BE. Notice from (CD-7.16) that if we can guarantee that (β +1)R E >> R BB then we have ( ) V I C = β BB V BE β V BB V BE V BB V BE, (CD-7.22) R BB + ( β +1)R E ( β +1)R E R E where the final approximation is valid so long as β is greater than ten or so. The final approximation in (CD-7.22) makes good sense. Stated in words it says that if the voltage drop across R BB in Figure CD-7-7 is negligible, then the base voltage of the transistor is approximately V BB, the resulting emitter voltage is V E = V BB - V BE, the emitter current is V E /R E, and the collector current is approximately equal to the emitter current (i.e., α = β/(β+1) 1). Notice that so long as we satisfy the stated condition (i.e., (β +1)R E >> R BB ), the resulting bias current is almost independent of β. Therefore, we can now state our first rule of thumb for intelligent bias circuit design; Pick component values so that (β+1)r E >> R BB. This rule of thumb ensures that the voltage drop across R BB is negligible. In other words, the rule

19 Chapter 7 - CD companion 19 guarantees that the base voltage of the transistor is about equal to the open-circuit voltage of the Thévenin equivalent driving the base, V BB. By thinking of the Thévenin equivalent circuit as shown in Figure CD-7-7 we realize that reducing the base current will reduce the drop across R BB. By examining the equation for R BB we also note that if R 1 and R 2 are smaller, that will reduce R BB. Since R 1 and R 2 are inversely proportional to the current flowing through them (assuming fixed voltages across them), the drop across R BB will be reduced if the current in R 1 and R 2 is increased. These two observations can be combined to express our first rule of thumb in an alternate form that is often more useful; The current in the resistor string biasing the base should be greater than or equal to ten times the base current. Following this rule of thumb ensures that the base voltage of the transistor is roughly equal to V BB and is not sensitive to changes in the base current of the transistor (brought about by changes in β). Now examine (CD-7.22) and notice that so long as V BB -V BE is significantly larger than any expected deviation in V BE, the bias current will not be a strong function of V BE. Suppose we rather arbitrarily, but quite reasonably, say that a ±5% variation in I C is acceptable. We then know that we can live with a ±5% variation in V BB - V BE as well. Assuming that V BE can vary by ±60 mv as stated in Table CD-A7.1, we have 0.06 V 0.05( V BB V BE ). (CD-7.23) Assuming a nominal V BE of 700 mv, (CD-7.23) leads to requiring V BB 1.9 V. By adding a small margin for safety and rounding to a whole number we can state a second rule of thumb for intelligent bias design; Set V BB greater than or equal to 2 volts. Equivalently, we can state this rule as: Set V E greater than or equal to 1.3 volts. It is worthwhile to notice that a tradeoff is being made in our choice for R BB. On the one hand, we want a small value for R BB to ensure that the bias point is insensitive to changes in β. On the other hand, a small R BB implies a large current in the bias string (R 1 + R 2 ) which implies greater power dissipation. In addition, we will see in Chapter Eight that a smaller R BB also implies a smaller input impedance, which is not desirable in most applications.

20 Chapter 7 - CD companion 20 Let s now compare the three topologies we have discussed so far. These circuits are shown in Figure CD-7-8, which is just a repeat of the circuits from Figures CD-7-1, CD-7-4, and The topologies in parts (a) and (b) of the figure have the lowest power dissipation for a given I C, although the differences are unlikely to be large enough to be a concern. In both cases the total current drawn from the supply is I C + I B and the resulting power dissipation is V CC (I C + I B ). The circuit in part (c) of the figure has greater power dissipation because the supply must provide the current through R 2 in addition to I C and I B. The circuits in parts (a) and (b) also use fewer components than the circuit in part (c), so they would cost less. The advantages of the circuit in part (c) are that it affords the designer greater flexibility in meeting different specifications and it has a more stable operating point. V CC V CC V CC R B R C R f R C R 1 R C R 2 R E (a) (b) (c) Figure CD-7-8 The three topologies considered for biasing BJT s. One final point about circuit design should be made prior to leaving this section. It probably comes as no surprise to you that discrete components can only be purchased in a finite number of different values. It is typically not possible, for example, to get a Ω resistor or a pf capacitor. After we have done a first pass calculation of the desired component values for a discrete circuit we

21 Chapter 7 - CD companion 21 must then choose the closest standard values available. This restriction is not present in integrated circuit design since the values of the resistors and capacitors are determined by layout and can have any value, although very large values are prohibited because the components would be too large and, therefore, costly. Aside A7.5 in the text presents the standard values typically available for discrete resistors and some other elements. CD FET Amplifiers; Detailed Treatment We begin by considering the common-source biasing scheme shown in Figure CD-7-9. Reasonable values have been chosen for the elements in the circuit in order to illustrate the operation and analysis. Assume that K = 200 µa/v 2 and V th = 1 V for the FET. The coupling capacitors would be chosen to be large enough that their impedances are negligible at the signal frequencies of interest. This circuit contains a feedback resistor, R f, which not only sets the gate voltage, but also makes the circuit oppose any changes in the operating point. For example, if the drain current increases (perhaps due to a change in temperature or from changing the transistor) the voltage across R D will increase and, therefore, the drain voltage will decrease. This decrease will be fed back to the gate via R f and will tend to decrease V GS and, therefore, the drain current. In other words, the change that would have been seen in I D if V GS were held constant has been decreased. This operation is an example of negative feedback. V DD = 10 V R f R D 1 k C OUT v in C IN 1 M v out Figure CD-7-9 A bias circuit for a FET amplifier. An enhancement-mode n-channel FET is shown in this example.

22 Chapter 7 - CD companion 22 We can solve for the currents and voltages in this circuit by using our large-signal DC model for the FET. Notice that since the DC gate current is zero, the gate and drain voltages are equal. Therefore, so long as V GS >V th the device will be forward active. The resulting equivalent circuit is shown in Figure CD V DD R f R D 1 k + V GS - 1 M K( V V ) 2 GS th Figure CD-7-10 The large-signal DC equivalent circuit for the circuit in Figure CD-7-9. Because the current through R f is zero we know that V GS = V D and this circuit has a single independent node, V D. We can solve for this voltage directly from the circuit; V D = V DD I D R D, (CD-7.24) or, using the fact that V GS = V D and substituting the equation for I D, V GS = V DD I D R D = V DD KR D ( V GS V th ) 2. (CD-7.25) By expanding the square in (CD-7.25) and rearranging the terms we get 2 2 KR D V GS + ( 1 2KRD V th )V GS + KR D V th VDD = 0, (CD-7.26) which can be solved using the quadratic formula to obtain V GS = 2KR DV th 1± ( ) 2KR D. (CD-7.27) ( 1 2KR D V th ) 2 4KR D KR D V 2 th V DD

23 Chapter 7 - CD companion 23 One of the two solutions in (CD-7.27) will always be impossible and can be discarded. For example, using the values for the circuit in Figure CD-7-9 we get V GS = 5.7 V or 8.7 V. (CD-7.28) The -8.7 V solution is not possible since all the voltages in this circuit must be in the range from 0 to 10 V. Therefore, V GS is 5.7 V and the resulting drain current is 4.3 ma. Some useful insight will be gained if we notice that we could also have solved for the drain voltage and current of the circuit in Figure CD-7-9 graphically by writing the loop equation in the drain circuit, V DD = V DS + I D R D, (CD-7.29) which leads to I D = V DD V DS R D. (CD-7.30) This equation describes the constraint placed on possible values of I D and V DS by the circuit external to the transistor. Assuming that the drain voltage is the output of the circuit, we think of (CD-7.30) as describing the load presented to the transistor and a plot of (CD-7.30) is called the load line for this circuit. Because V GS = V DS in this circuit however, and because V GS controls the value of I D, it is more convenient to rewrite (CD-7.30) in terms of V GS ; I D = V DD V GS R D. (CD-7.31) Figure CD-7-11 shows a plot of (CD-7.31) along with the I D -V GS characteristics of the transistor. The Q point is determined by the intersection of the load line and the transistor s I D -V GS characteristic as shown in the figure. As noted in Chapter Six, this graphical method of solution is not typically used, but it is still educational to consider this view while learning about biasing.

24 Chapter 7 - CD companion 24 I D V DD R D 25 ßC I D = K(V GS - V th ) 2 Q point 75 ßC Q load line 0 V th V DD V GS Figure CD-7-11 Typical n-channel MOSFET I D -V GS characteristic at two different temperatures, with the DC load line for Figure CD-7-9. Using Figure CD-7-11 we can also see what happens when the temperature of this circuit is increased from 25 ûc to 75 ûc. Using the transistor curve for 75 ûc indicates that the new Q point (labeled Q ) is significantly different from the original one. This shift in Q point with temperature is undesirable. Before exploring the issue of parameter variations further, the following example will examine how the Q point of this circuit varies with V th alone. Example CD-7.3 Problem: Solution: Find the Q point of the circuit in Figure CD-7-9 if the transistor used has (a) V th = 0.5 V and (b) V th =2 V. Plugging the new values into (CD-7.27) and discarding the negative solutions leads to (a) V D = 5.33 V and (b) V D = 6.3 V. Plugging these values back into the drain current equation yields (a) I D = 4.7 ma and (b) I D = 3.7 ma. This variation in I D is large, but due to the feedback, it isn t nearly as large as the variation in V th.

25 Chapter 7 - CD companion 25 The variation seen in the bias point in Example CD-7.3 is fairly large even though this bias arrangement has some negative feedback to stabilize the bias point. A more rigorous way of examining the stability of the bias point is to use the normalized small-signal sensitivity presented in Aside CD-A7.1. If you are not familiar with small-signal sensitivity you should review that aside now and then return for the following analysis. We start by recognizing that the negative solution in (CD-7.27) will be discarded so we can take the positive solution to get V GS = 2KR DV th 1+ ( ) 2KR D. (CD-7.32) ( 1 2KR D V th ) 2 4KR D KR D V 2 th V DD Using this equation and the drain current equation for the MOSFET we find 2KR D V th 1+ I D = K = K ( ) ( 1 2KR D V th ) 2 4KR D KR D V 2 th V DD 2KR D ( ) 1+ ( 1 2KR D V th ) 2 4KR D KR D V 2 th V DD 2KR D 2 V th 2. (CD-7.33) Using the definition of small-signal sensitivity from (CD-A7.3) along with (CD- 7.33) we get I S D Vth = V th I D di D dv th = 2V th ( ). (CD-7.34) ( V GS V th ) ( 1 2KR D V th ) 2 4KR D KR D V 2 th V DD I Using the values for the circuit in Figure CD-7-9 we find that S D Vth = -0.15, which is not terrible, but not very good either. It is interesting to compare the changes predicted in I D using (CD-7.34) with the results of Example CD-7.3. Since the variations in V th were not small in that example, we don t expect the results to be the same, but they shouldn t be too far off. Using the sensitivity we predict that when V th decreases from 1 V to 0.5 V the drain current will increase by 0.32 ma. The resulting current would then be I D = = 4.6 ma, which compares fairly well with the value of 4.7 ma found in the example. Similarly, when V th is

26 Chapter 7 - CD companion 26 S K I D = increased to 2 V, the sensitivity predicts that I D will decrease by 0.65 ma to 3.65 ma. This value is again fairly close to the correct value of 3.7 ma. Applying the small-signal sensitivity to (CD-7.33) again we can also find 4K ˆ V th ( 1 2K ˆ V th ) 2 4K ˆ ( K ˆ V 2 th V DD ) 1 2K ˆ V th ( ) 2 4K ˆ ( K ˆ V 2 th V DD ) 1 (CD-7.35) where we have used K ˆ = KR D to simplify the expression. Plugging in the values I for the circuit in Figure CD-7-9 yields S D K = This sensitivity is quite large, but fortunately the variation in K is not as large as the variation in V th, so this may be acceptable. Before moving on to consider a better biasing arrangement we need to have some idea of what to expect for the magnitudes of the variations in the large-signal DC model parameters of FET s. The following aside presents some typical values. ASIDE CD-A7.4 Device-to-Device Variation in FET Large-Signal DC Model Parameters The large-signal DC model parameters for transistors vary from one device to the next. How predictable a given parameter is depends on the parameter and whether we are considering discrete or integrated transistors. Discrete transistors are packaged individually and may have been fabricated at completely different times by different companies. Therefore, no assumptions can be made about any two transistors matching; the safest assumption is that they are both at opposite extremes of the allowable specifications (highly unlikely, but definitely leads to a safe design). The data sheets for individual transistors will usually list both minimum and maximum values for V th, but will usually only list a minimum or maximum for other parameters (e.g., only a minimum g m is usually given since it is assumed that a larger value will be even better). Data sheets do not specify K for MOSFET s, it must be deduced from either g m or R DS. Table CD-A7.3 shows typical ranges for the different parameters of interest for a given type of discrete transistor, the variations are much larger if different types of transistors are compared. For integrated transistors, the variations from one IC to the next will be just as large as for discrete transistors, but the matching from one transistor to another on the same IC is much better since the devices are fabricated

27 Chapter 7 - CD companion 27 at the same time and are physically close to each other. The closer the transistors are to each other, the better the matching will be. Larger area transistors also match better, and transistors made as a parallel combination of devices laid out symmetrically about a common center point also match better (this is called common-centroid layout [7.1]). It is quite possible to have two large MOSFET's with threshold voltages that match to better than 1 mv. The matching listed in the table is only meant to be typical for medium size transistors that are right next to each other. The matching is different for each process and these numbers must be taken as only a rough indication of typical values. How well the temperatures of two transistors match is often of importance in design (see Aside CD-A7.5), and the thermal matching of discrete transistors is very poor unless they are mounted on the same heat sink. Even when mounted on the same heat sink however, the thermal matching of discrete transistors is never as good as that achievable with integrated transistors. Parameter Typical range for discrete transistors of the same type Typical matching for medium-size FET s adjacent to each other on an IC Minimum Maximum V p (1) -1-6 ± 3 mv V th 0.5 V 2.5 V ± 3 mv K (2) 10 ma/v ma/v 2 ± 1 % I DSS 1 ma 5 ma ± 4 % Table CD-A7.3 Matching data for discrete n-channel FET s and typical medium-size (W = 10 µm & L = 2 µm) integrated n-channel MOSFET s that are adjacent to each other. NOTES: (1) V th applies to MOSFET s and V p applies to JFET s. (2) K applies for MOSFET s and I DSS applies for JFET s. This table is reproduced in the printed text as Table 7.4. We next briefly examine how MOSFET parameters vary with temperature. The following aside will provide some typical values as well as providing a definition of the temperature coefficient (TC). The TC is a commonly specified parameter for both circuit specifications and individual component specifications.

28 Chapter 7 - CD companion 28 ASIDE CD-A7.5 Temperature Coefficients and the Variation of Large- Signal DC MOSFET Model Parameters with Temperature All of the terms shown in our standard large-signal DC model of a forward-active MOSFET are temperature dependent. The value of V th decreases by approximately 2 mv for every 1 ûc rise in temperature if the current is held constant, while K varies as T due to the decrease in mobility as temperature increases. Therefore, as temperature increases, the decrease in V th tends to increase the drain current and the drop in K tends to decrease the drain current. Which of these effects will dominate depends on the bias point. A typical set of I D -V GS curves for a MOSFET at 25ûC and 75ûC are shown in Figure CD-A7-3. An interesting result of the opposing changes in K and V th is that a MOSFET has a bias point at which the variation in I D with temperature is zero. This point is labeled in the figure as the zero temperature coefficient point. I D 25 ßC 75 ßC zero temperature coefficient point 0 V th V GS Figure CD-A7-3 The I D -V GS characteristics of a MOSFET at 25ûC and 75ûC. It is common to quote temperature sensitivities in terms of a temperature coefficient, or TC. The TC of a parameter X is defined by TC X 1 X dx dt = 1 T S T X. (CD-A7.6) Examination of (CD-A7.6) reveals that a TC is normalized with respect to the parameter of interest, but it is not normalized with respect to temperature. Since a TC is normalized with respect to the parameter, the proper units are ûc -1 and a common choice is to use parts-per-million per degree Celsius (ppm/ûc), where

29 Chapter 7 - CD companion ûc -1 = 1 ppm/ûc. Depending on the parameter however, it is also common to just use the derivative in (CD-A7.6) and not normalize the value at all. This is still called a TC and is only distinguishable from the TC defined above by the units; since no normalization has taken place, the units will be something like mv/ûc or ma/ûc. Table CD-A7.4 summarizes the MOSFET parameters, typical values at room temperature, the equations for how they vary with temperature, and their temperature coefficients (quoted in the most common units). Parameter Typical value at 25 ûc Variation with Temperature Typical Temperature Coefficient at 25 ûc K 10-5 to 10-3 A/V 2 K(T) = K(T o )( T o T) ûc -1 V th (I D constant) n-channel V th (I D constant) p-channel 0 to 5 V V th (T) = V th (T o ).002 T T o ( ) -2 mv/ûc 0 to -5 V V th (T) = V th (T o ) +.002( T T o ) 2 mv/ûc Table CD-A7.4 Variation of large-signal DC MOSFET parameters with temperature. All temperatures are in Kelvin for the equations. Data taken from [7.3, pp ] and [7.4, pp ]. This table is reproduced in the printed text as Table 7.5. As a final note on the sensitivity of circuits to component variations, we point out that the resistors, capacitors, inductors, and other non solid-state devices also vary from device to device and with temperature. The typical variations seen are presented in Aside A7.4 in the text. Although the values of passive components do vary, resistors can be purchased with very small tolerances and very low 1 Note that (5.5-18) has a printing error in the copy we examined, it shows TT o ( ) 1.5, which is incorrect.

30 Chapter 7 - CD companion 30 temperature coefficients, so the final stability of resistive bias circuits is limited by the active components rather than the passive ones. We now return to the circuit of Figure CD-7-9 and consider how to choose the component values to achieve the desired operating point. It turns out that R f will, in general, affect the small-signal AC performance of the circuit and so we won t know how to choose it until Chapter Eight. Nevertheless, if we make R f big enough, it s effect on the small-signal AC performance will be negligible. Therefore, for now just choose R f = 1 MΩ. Assuming the desired drain current is known, the problem of choosing R D then reduces to using Ohm s law, R D = V DD V DS I D = V DD V GS I D, (CD-7.36) and V GS can be determined from the desired I D. Example CD-7.4 Problem: Solution: Find values for R f and R D for the circuit of Figure CD-7-9 that will produce a drain current of 2 ma. Assume the transistor has K =1 ma/v 2 and V th =2 V. Set R f =1 MΩ. In order to achieve I D = 2 ma we must have or, in other words KV ( GS V th ) 2 = 2 ma, V GS = V th K = = 3.4 V Since V DS = V GS we can now find R D ; R D = V DD V DS = = 3.3 kω. I D 0.002

31 Chapter 7 - CD companion 31 At this point we are led to reconsider the circuit from Section in the text. That circuit was shown in Figure 7-49 and the large-signal DC equivalent from Figure 7-50 is repeated in Figure CD-7-12 for convenience. V DD R D V GG + - R GG G + V GS - S D K(V GS - V th ) 2 R S Figure CD-7-12 The large-signal DC equivalent for the circuit in Figure In Section we considered the sensitivity of the bias point in this circuit to changes in V th and K. We derived an equation for the drain current that was given in (7.42) and is repeated here for convenience; I D = V GG V GS R S. (CD-7.37) We concluded earlier that so long as the quantity V GG -V GS is much larger than any expected variation in V GS, the drain current will be approximately constant. We would now like to revisit that statement and look at it in another way. Equation (CD-7.37) allows us to plot a line that represents the constraints imposed by the circuit on the I D -V GS plot as shown in Figure CD Because this line defines the constraints placed on the values of I D and V GS by the bias circuitry, we will call it the bias line as shown in the figure. This line is analogous to the load line we introduced before. Figure CD-7-13 also shows the transistor s I D -V GS characteristics for two different values of V th.

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