Whereas the diode was a 1junction device, the transistor contains two junctions. This leads to two possibilities:


 Randell Shelton
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1 Part Recall: two types of charge carriers in semiconductors: electrons & holes two types of doped semiconductors: ntype (favor e), ptype (favor holes) for conduction Whereas the diode was a junction device, the transistor contains two junctions. This leads to two possibilities: i) arrow indicates direction of current flow ii) BC, BE have diode drops. But transistors are NOT equivalent to two backtoback diodes. (BC, BE junctions are also asymmetric, larger drop across BC junction) Notation: i) V B, V C, V E = voltage at base, collector, emitter w.r.t. ground ii) V BE = voltage at base w.r.t emitter iii)v CE = voltage at collector w.r.t emitter iv)v CC  usually the positive power supply voltage v) V EE  usually the negative power supply voltage If V CE > V BE BE junction is forward biased therefore current should flow... CE junction is reversed biased. If CE formed a normal diode, no current would flow through the collector. The difference is that the base region is very thin and a strong E field exists at the CB junction which collects any electrons that come nearby. ) Electrons are injected into base from emitter (from the diode equation I E ~I 0 exp qv BE /kt ) 2) e's arriving at the base have two possibilities i) recombine with holes and flow out of the base ii) if an electron drifts near the CB junction it will be sucked across the junction due to the large E field If I E is large enough (ii) usually dominates. A 'logjam' of electrons looking for holes in the thin base material make the electrons likely to jump into the collector. In this case I C ~ I E where
2 Early transistors had ~0.9 today typical transistors have values ~0.99 More convenient notation uses the parameter to distinguish transistors. I C = I B And typical values of range from ~ I C I B is the current gain of the transistor at (DC). A small base current cause a much larger current to flow through the collector/emitter. = note: =00=.99 =50=.98 is a much more sensitive measure of transistor properties Common Emitter Configuration There are 4 variables of interest: V BE, I B,V CE, I C The most useful relationships among these are: Input characterisic V BE = f I B,V CE Output characteristic I C = f 2 I B,V CE So long as V CE >~ 0.6V, V BE and I C depend only weakly on V CE i.e. V BE ~ f ' I B ~fairly constant I C ~ f 2 ' I B 2
3 Three regions of operation ) Active Region V BE ~0.6V V CE >~V BE (I C > 0) defined as: I C /I B is large ~ 00 This mode is used in linear amplifiers 2) Saturation V BE ~0.8V V CE < V BE Still have I C > 0, but is small ~ 0 Transistor is used as a switch in this mode 3) Cutoff V BE <~0.5V therefore I E,I C = 0 Transistor does not conduct Comments: for pnp reverse the above signs and inequalities I C is never < 0 in normal operation (large reverse voltages can cause breakdown and frequently ruin a transistor) Simple model of transistor in active region V CE >V BE (or for pnp type V CE <V BE ) ) 'current gain' picture I C / I B =~00 since I E = I B +I C, I C = I E ~I E 2) Assume simple VI diode characteristics for BE junction I E 0 V BE ~0.6V I E =0if V BE 0.6V or for pnp I E 0 V BE ~ 0.6V I E =0if V BE 0.6V 3
4 Emitter follower (aka common collector) Used to buffer a higher output impedance source to drive a lower input impedance load. V L =V S R L R L R S V S if R L R S Black Box emitter follower R in = V S L R in R R L R L R S V S~V S if R in R S and R out R L Constructing an emitter follower V KVL: in V BE =V out V out =V in 0.6V V in V BE I E =V EE The output simply follows the input when the transistor is in the active region. RB, C are optional (they spoil Q of resonant circuits formed by stray L,C in circuit. (greater importance at high frequencies) Emitter follower in cutoff region at cutoff V in < V EE 0.6V The transistor can do no more that shut off current flow, allowing the base to sit at V EE (very large negative biases can cause breakdown and damage to transistor) 4
5 Emitter follower at saturation If V in > V C, then the V CB junction is forward biased I in ~ V in V CC 0.6V V B ~V CC 0.6V V sat CE typically ~0.2V Analysis of input and output impedance of the emitter follower V in I B V BE =V out V in I B V BE I E =V EE nonlinear relationship for I E,V BE I E e qv BE /kt makes it difficult to define impedance by using V/I Instead we use small signal analysis to define the impedances for time varying signals. Express V,I as a time invariant part + a time varying part then define Z = V I = (for AC signals) V V DC V t V DC I I DC I t I DC In the simple transistor model V BE =0 and V EE =V CC =0 (they are power supplies!) therefore for the small signal analysis we can write in b = out in b e =0 Note: we now adopt a notation where lower case letters will generally refer to small signal equivalents in a circuit analysis 5
6 Small signal equivalent analysis of the emitter follower power supplies are replaced by AC shorts to ground Small signal current gain h FE c / b h FE need not equal, but in practice they tend to agree w/in ~ 20% and are both large (>>). We'll generally assume ~h FE Input impedance Z in = in b = out b b then use e = b Z in = (usually << ) This is the input impedance looking into the base note: Z in To find the output impedance, we replace the circuit by its small signal Thevenin equivalent. O.C. thev = out Z thev = O.C. out S.C. out finding the open circuit output: O.C. out = in b = in / Z in = in in finding the short circuit current: S.C. out = S.C. b = in / Z out = O.C. out = S.C. out = R E if ~ note: Z out What is in this case? 6
7 Limitations of the emitter follower Consider a typical application: driving a 50 Ohm terminated coaxial cable. Assume t RC so that we are in the DC blocking regime for the high pass filter. For the transistor to remain in the active region we need I E >0 positive input increases I E, no problems as long as V in < V CC negative input pulses will decrease I E and may cause cutoff KVL: V in V BE I S =V SS V in V BE V cap I L R L =0 assume V BE =0 and the capacitor is a short for our signal frequencies small signal form of KVL: in in s =0 in L R L =0 then using e= s cap e = R L The transistor cutsoff when e = I E D.C. or (equivalently) when in I E D.C. R L Note: The cutoff voltage depends strongly on the load if R L <~ Circuit simulation illustrating cutoff effect 7
8 The problem of reproducing negative pulses can solved by using a pnp transistor In this case a negative pulse increase I E, keeping the transistor active (but a positive pulse can cause it to cutoff in the same way illustrated above) The general solution for bidirectional pulses is to use a complementary follower This simple approach has an unfortunate drawback. It does not work for small signals in 0.6V Large cross over distortion, output only follows input if in 0.6V, otherwise V out = 0 A better design that compensates much of the cross over distortion In this design: D, D 2 keep V BE ~ ±0.6V (the downside is that Z in ~ R/2!) 8
9 Strategy for biasing an emitter follower ) choose quiescent current I Q, where I Q is the current drawn by the largest pulse which would tend to shut off the transistor. I Q max in max in (if is symmetric) in R L R L 2) choose (assuming AC coupled load otherwise load would affect I Q ) V B 0.6V I Q =VEE = V B 0.6V I Q I Q For maximum symmetric voltage swing at output, V B is set to ~midpoint between the two power supplies V B ~ 2 V CCV EE = 2 V CC V EE.2V I Q 3) Choose the appropriate resistor divider to set the base voltage V B ~ 2 V CC V EE for our example R R 2 and V CC V EE R R 2 ~0. I Q this is the current through the divider Solving for R: R V CC V EE I Q Note: ~00 therefore above relation guarantees that I divider ~0 I B so the base voltage is roughly independent of the base current 4) Finally choose the appropriate AC coupling capacitors for the input signal Z in = R R 2 R L R in choose C in, C out by the necessary low frequency signal cutoff C in ~ 3dB R in C out ~ 3dB R L 9
10 Building a simple current source I in = I E~I E I E = V BB 0.6 V EE for negligible I B This circuit is a good constant current source a long as V C > V BB (small rise of I C w/ V BB ) Otherwise, decreases as we approach saturation. Compliance A current source can only provide constant current for a limited range of voltage at the collector. This output voltage range is called the output compliance of the current source. The compliance is set by the requirement that the transistor stay in the active region. A current source such at the one to the right has limited compliance related to : Compliance ~ V CC V sat I E V EE 0
11 Inverting amplifier (aka common emitter amplifier) Assume the transistor is in the active region, then the analysis of this circuit is identical to the emitter follower e = e = in using c ~ e out = c R C = R C in GainG= R C Z in is identical to the emitter follower Z out is different The collector looks like a very large resistance Z out =R C R C cross checking with the Thevenin equivalent O.C. out = R C R in E S.C. out = c = in here we have use the small signal short: This circuit cannot maintain a large gain while driving a low impedance load G RL = R C R L R C The solution to allow driving a heavier load is to add an emitter follower G= R C R L ~ R C
12 Hybrid Parameters Part 2 In our simple analysis of transistor circuits thus far we have assumed the applicability of a simple model V BE ~0.6V,V BE = BE =0 in the active region. These assumptions lead to unphysical results in some cases ) G= R C implies infinite gain of inverting amplifier 2) Z out = 0 implies zero (or at least arbitrarily small) output impedance We can refine the simple model for small signal analysis by making a Taylor expansion of the input and output characteristics that we saw earlier. Using V=IR V BE = f I B,V CE BE = f I B V CE b f V CE I B ce h ie is a resistance h re is unit less =h ie b h re ce h fe is unit less h oe is /resistance I C = f 2 I B,V CE C = f 2 I B V CE b f 2 V CE I B ce =h fe b h oe ce 2
13 The transistor model circuit described by these equations is shown in the figure below: Equivalent circuit for a transistor In practice V BE, I C depend only weakly on V CE, in this limit h re and h eo ~ 0 With this approximation we get be =h ie b c =h fe b this should look somewhat familiar, recalling that h fe ~ The transistor model the simplifies to An alternate and more convenient model commonly used is here r e h ie This is called the T equivalent circuit 3
14 EbersMoll Approximation Above we have abandoned simple assumptions V BE ~0.6V,V BE = BE =0 to fully describe a transistor in the active region. More precisely I E and V BE are related by (the diode equation): I E ~I 0 e V /V BE T ~I C where V T kt /q 25 mv at room temperature then I E = I E D.C. V V BE T e =g m BE and BE = e r e where r e = = V T g m I = 25 D.C. in ma at E I room temperature Small signal T equivalent circuit of the transistor looks like:  a current source controlled by b voltage drop across BE junction depends on current flowing through the device EbersMoll illustrated. Logarithmic increase in V BE with increasing I E while in active region. The lower plot zooms in on the effect of I B on the saturation voltage. 4
15 Small signal analysis of the inverting amplifier Assume: R 3 C 2, R R 2 C 2 time intervals of interest i.e. DC blocking (refer to Lab manual pp. 56 for a review of methods to establish proper DC biasing) Equivalent circuit (for small signal analysis): in e r e ' =0 Gain: out = c R C Gain= out = R C R C ' in r e r e R 3 if R 3 c ~ e ) Gain < infinity even when R 3 = 0 2) When R 3 = 0, G = R C /r e Since r e =V T / I E =V T / I E DC e the gain will depend on the amplitude of the signal. One can get a well defined G by setting R 3 >> r e for the entire signal range. But then the maximum gain is limited by the R C constraint namely, V CC I DC C R C /2V CC (for max. symmetric voltage swings at output) 5
16 Grounded emitter amplifier consider the following circuit G= R C /r e Z in =R R 2 r e Z out R C We obtain a large gain but pay the cost with: small Z in large Z out But the more serious problem with this design is in the stability of the DC operating point. Consider the effect of temperature variations: At constant I E ~I C V BE = 2.mV / o C (see text) 2 I At constant V C BE I 0T 2 T /30 o C C As a consequence, a G.E. Initially biased so that V C = 2 V cc will saturate (i.e. V C ~0.6V ) when T =8 o C Also V BE necessary to give a specific I C will vary ~ 00mV for different transistors of the same type The above circuit is a lousy design for these reasons! A stable operating point can be obtained by adding an Choose R, R 2 so I E ~V i.e. V BE C E so r e C e f 3dB The DC bias is now stable and the large gain for AC signals is unaffected. But we may experience significant signal distortion due to variations in r e with emitter current. 6
17 Analysis of grounded CE amplifier with a triangle waveform as input. Output distortions are obvious for changing currents in the transistor. The bottom plot shows how the gain of the circuit changes as the input wave form varies G= out R C R C ma. The gain varies a in r e 25/ I E factor of two over the input signal shape from ~ 300 to almost
18 Simple current source I in = I E~I E I E = V BB 0.6 V EE for negligible I B This circuit is a good current source a long as V C > V BB (small rise I C w/ V CE ) Otherwise, decreases as we approach saturation. of A current source such at the one to the right has very limited compliance due to : Compliance ~ V CC V sat I E V EE A current mirror can increase compliance range to within a few 0ths of a volt of the power supply and also improve Z out. A simple current mirror No to limit compliance of output transistor in this design. V 2 BE =V BE I,2 I 0,2 e qv BE /kt,2 (V BE < 0 for pnp transistor in active region) substituting V BE =kt ln I I 0 I 2 =I 2 I /T 2 0 T I 2 0 I 0 I 0 I { T in the expression for I_2 T 2 ln I I } 0 I 2 'mirrors' or is 'programmed by' I 8
19 Comments on the current mirror: i) I =V CC 0.6/ R P (nearly constant in the active region) then 2 ii) if T =T 2 I 2 = I 0 I I (area scaling current is 'mirrored') 0 iii)thermal dependence: if T 2 T I 2 0 Saturation current grows w/ temp, leading to a I 0 net INCREASE in I C with temperature (for fixed V BE ), net DECREASE in V BE with temperature of ~ 2.mV/ o C for fixed I C. That's not obvious from looking at EbersMoll/diode equation. Ideally Z out should be ~ infinity for a current source. I =0= V R This is not the case. Use the Early Effect to understand the finite Z out. The Early Effect The Early Effect describes I C dependence on V CE It is parameterized as I C =I 0 e V BE /V T V BC V A (for V CB > 0) ~% effect / volt In the mirror above V BE will break the symmetry due to the Early Effect. Z out =[ r o I C V CE] [ I C V BC 2 remains constant with changes in V CB ] =[ I C V A] is related to the hybrid parameter r o Recall: in our T equivalent model we took h oe ~00 ma,2, but differences in V CE I C V CE goes as h oe ~0 as one of our simplifying assumptions. 9 r o
20 The two following methods can be used to increase Z out for the current source, however the cost is a slight reduction in compliance. ()Emitter resistors (neglecting base currents) V CC I C V BE =V B =I C R P I C I P V CC 0.6V R P To find Z out V BE =V B V CC I T C subs. I C =I 0 e V BE/V V BC V A find changes in V BE so be = be I c r e I C V BE be I C V BC bc V A bc E= R be r e r o bc noting that be = c (V B2 is fixed by Q) = r bc Z out = bc =r o o R E c r e c r e The increase above r o seems plausible since any increase in I C would increase V BE thereby decreasing I C. The emitter resistors work as a negative feedback system to help keep the current stable. But compliance is reduced somewhat by addition of to the output transistor. 20
21 (2) Wilson Mirror Both V CE(2) and V CE(3) are fixed (to fight Early effect) Say I C wants to increase due to an increase in V CE(). This will also increase V BE(2) thus increasing I P thus increasing V BE() thus decreasing I C I C is held stable against Early Effect For this circuit Z out =r 0 R P r e Compliance is reduced somewhat by addition of a second diode drop. 2
22 Differential Amplifier Part 3 i) basis of most op amps and comparators ii) good for sensing low level signals in a noisy environment DC analysis of a basic differential amplifier Assume: I C = I E V BE = 0.6V (operate in active region: I C >0, V CB >=0) To find V out in terms of V,V 2 it is sufficient to find I,I 2 KVL (from base to base 2): V V BE I I 2 V BE V 2 =0 I 2 = V V I T where I T =I I 2 V out =V CC I 2 R C To find I T use KVL from base (base2) to V EE V V BE I I T R T =V EE V 2 V BE I 2 I T R T =V EE V I T = V therefore I V 2 2 V V 2 0.6V V EE V 2.2V 2V 2,= EE 2 2 R T 2 R T differential mode common mode define V Dif =V V 2 V CM = 2 V V 2 so I,2 = V dif 2 V CM 0.6V V EE 2 R T large V Dif = large I 2 small V Dif current suppressed by 2 R T Therefore if << R T, Gain is much larger for differential voltages than for common voltages at the two inputs. 22
23 Small signal analysis of a differential amplifier Assumptions: V DC DC =V 2 I DC DC =I 2 V T r e =r e2 = /2 I T Using KVL from base to base 2 b r e b2 r e 2 =0 use b c and 2 = T 2 = 2 2r e 2 T therefore o = 2 R C = 2 Dif R C 2r e Differential Gain G Dif 2 2 CM R C r e 2 R T Common Mode Gain G CM Common Mode Rejection Ratio: CMRR= G Dif = 2 R T r e G CM 2R e r e r e CMRR is large in a good differential amplifier. R T is often replaced by a current source to give maximum common mode rejection. R T 23
24 The CMMR of the differential amplifier may be significantly improved by adding a current source to the tail. Assuming a perfect current source, we again solve for I,2 as a function of V,2 KVL: V V BE I I 2 V BE2 V 2 =0 use I I 2 =I T and I I S e V BE/V T to write: V V 2 I T 2 I 2 I T V T ln I T I 2 =0 this relates I 2 to V dif for the perfect current source (constant I T ), the output ( I 2 ) only depends on V dif. Consider two limiting cases: i) if I T V T (25 mv at room temperature) then the current reduces to: I 2 = V V I Differential gain is similar to above case. T ii) if =0 then = I T e V V 2 /V T I 2 =I T for small V V 2 I 2 Amplifier quickly saturates to one of two states I 2 =0 or 24
25 The Miller Effect Consider a high gain CE amplifier. o b and o 0 (Large dv/dt across C BC) b An intrinsic capacitance connects the base to the collector. At high frequencies current can be diverted from the base to the collector via this capacitive coupling. (This current flow is not related to the DC case of forward biasing the BC junction.) The effects of this are two fold: i) Z in looking into the base is reduced at large frequencies ii) The gain is reduced because of the voltage divider effect of R S and Z in Millers Theorem Consider a 3terminal network: In the equivalent circuit: Z = Z K Z 2 = ZK K K 2 proof: = 2 = Z K Z = Z 2 = 2 = Z 2 / K Z = 2 Z 2 How much current flows through C BC? dv I =C Cap BC =C dt BC b o C CB G b C CB looks like a capacitor that is G times larger (remember G is negative...) 25
26 Analysis of the Miller effect in an amplifier circuit Assume we have an ideal inverting amplifier (Z in =, Z out =0, Gain = A) Applying Miller's theorem, we can redraw the circuit as: K = 2 = A Z C = Z C A = = j C j C A C =C A The negative gain effectively increases the input capacitance. Note: we can ignore C 2 in this analysis, because it's tied to the low Z output of the amplifier and thus has no effect on the signal. Next we compute the overall gain of the amplifier circuit which is the product of the attenuation due to the voltage divider (R S C ) and the gain of the ideal amplifier (A). 2 = A = A s j R S C = s A Gain= j R S C A A A j R S C A j R S C i) In the limit of low source impedance, the gain is simply A as per the design of the amplifier subcircuit. ii) For finite source impedance, the device becomes a perfect integrator as the gain approaches infinity. i.e. for in =e j t out j e j t 26
27 Miller Effect in the Grounded CE Amplifier This is more complex that the ideal case above,because of finite input and output impedances. However, we can simplify matters for nottoolarge values of the input frequency. Begin by calculating K: (KCL) c = L f (Trans. Eqn.) c e = /r e where: L = 2 / R C f = 2 j C CB Then (KCL) becomes r e = 2 R C 2 j C CB K 2 = R C r e j R C C CB j R C C CB K R C r e K K for R C C CB and r e R C i.e. current flow through C CB is small Z C CB R C =Z out output not loaded Therefore the equivalent circuit can be modeled as below (using C =C CB R C /r e C 2 =C CB ) 27
28 Since the impedance looking into the base of the transistor is r e the input signal sees Z in at the base to be Z C r e Z = in Z C S = r e r Z in R S = e S Z C r e R S S R S r e[ j C R S r e ] R 2 = C from our assumption that r e R C C CB Solving for the circuit's gain G= 2 = R C e[ S R S r j R C r e ] C R r CB S e This has the form of a low pass filter with 3dB = R C r C R r CB S e e Notice that for large R S r e 3dB 2 R R C C C C CB CB then (and above derivations are still valid) This means that the Miller Effect becomes the dominant cause of gain loss at high frequencies. Summary: The Miller Effect arises when the following conditions are present: ) large inverting gain 2) nonnegligible output impedance of signal source 3) capacitance between input and output of amplifier circuit 28
29 Designs that avoid the Miller Effect Differential amp w/ one input grounded Cascode connection Input and output have the same phase At base of Q2 Z out =0 (grounded) preventing local Miller effect at Q2 collector resistor for Q is r e2, thus G () ~  (not large) Z out =0 at the base of Q2 29
30 The Bootstrap Technique On the flipside, the Miller Technique may also be used to raise the input impedance of a circuit. In order to provide a stiff DC bias voltage at the base of the transistor in an emitter follower, we required R R 2 0 for a single supply follower like the one show above. From the small signal equiv. circuit we calculated Z in =R Div R Div where R Div 20 This is much less that what is possible for an emitter follower, namely Z in The circuit below has a much larger input impedance Z in ~. Almost no (A.C.) current flows through because both ends are at nearly the same (A.C.) voltage. R L = R div R' B = R L R' ' B = R L r e K 2 = R L R L r e K = r e R L R e r e R L K K = R L r e (large and negative) ' ' = R L r e and R L ' ' R L therefore Z in r e R L 30
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